STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal.h
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1 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef STM32L4xx_HAL_H
23 #define STM32L4xx_HAL_H
24 
25 #ifdef __cplusplus
26  extern "C" {
27 #endif
28 
29 /* Includes ------------------------------------------------------------------*/
30 #include "stm32l4xx_hal_conf.h"
31 
40 /* Exported types ------------------------------------------------------------*/
41 /* Exported constants --------------------------------------------------------*/
42 
50 #define HAL_TICK_FREQ_10HZ 100U
51 #define HAL_TICK_FREQ_100HZ 10U
52 #define HAL_TICK_FREQ_1KHZ 1U
53 #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
54 
70 #define SYSCFG_BOOT_MAINFLASH 0U
71 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
72 
73 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
74  defined (STM32L496xx) || defined (STM32L4A6xx) || \
75  defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
76 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
77 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
78  /* STM32L496xx || STM32L4A6xx || */
79  /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
80 
81 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
82 
83 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
84 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2)
85 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0)
86 #else
87 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
88 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
89 
97 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0
98 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1
99 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2
100 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3
101 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4
102 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5
111 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0
112 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1
113 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2
114 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3
115 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4
116 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5
117 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6
118 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7
119 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8
120 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9
121 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10
122 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11
123 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12
124 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13
125 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14
126 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15
127 #if defined(SYSCFG_SWPR_PAGE31)
128 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16
129 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17
130 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18
131 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19
132 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20
133 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21
134 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22
135 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23
136 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24
137 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25
138 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26
139 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27
140 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28
141 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29
142 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30
143 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31
144 #endif /* SYSCFG_SWPR_PAGE31 */
145 
150 #if defined(SYSCFG_SWPR2_PAGE63)
151 
154 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32
155 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33
156 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34
157 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35
158 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36
159 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37
160 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38
161 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39
162 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40
163 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41
164 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42
165 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43
166 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44
167 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45
168 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46
169 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47
170 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48
171 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49
172 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50
173 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51
174 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52
175 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53
176 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54
177 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55
178 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56
179 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57
180 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58
181 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59
182 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60
183 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61
184 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62
185 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63
190 #endif /* SYSCFG_SWPR2_PAGE63 */
191 
192 #if defined(VREFBUF)
193 
196 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U
197 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS
206 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U
207 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ
212 #endif /* VREFBUF */
213 
218 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF
219 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY
231 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
232 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
233 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
234 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
235 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
236 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
237 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
238 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
239 
248 /* Exported macros -----------------------------------------------------------*/
249 
256 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
257 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
258 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
259 #endif
260 
261 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
262 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
263 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
264 #endif
265 
266 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
267 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
268 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
269 #endif
270 
271 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
272 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
273 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
274 #endif
275 
276 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
277 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
278 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
279 #endif
280 
281 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
282 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
283 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
284 #endif
285 
286 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
287 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
288 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
289 #endif
290 
291 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
292 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
293 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
294 #endif
295 
296 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
297 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
298 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
299 #endif
300 
301 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
302 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
303 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
304 #endif
305 
306 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
307 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
308 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
309 #endif
310 
311 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
312 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
313 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
314 #endif
315 
316 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
317 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
318 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
319 #endif
320 
321 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
322 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
323 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
324 #endif
325 
326 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
327 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
328 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
329 #endif
330 
331 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
332 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
333 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
334 #endif
335 
336 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
337 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
338 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
339 #endif
340 
341 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
342 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
343 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
344 #endif
345 
346 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
347 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
348 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
349 #endif
350 
351 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
352 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
353 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
354 #endif
355 
356 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
357 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
358 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
359 #endif
360 
361 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
362 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
363 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
364 #endif
365 
376 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
377 
380 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
381 
384 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
385 
386 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
387  defined (STM32L496xx) || defined (STM32L4A6xx) || \
388  defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
389 
392 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
393 
394 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
395  /* STM32L496xx || STM32L4A6xx || */
396  /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
397 
398 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
399 
402 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))
403 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))
404 
405 #else
406 
409 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
410 
411 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
412 
425 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
426 
431 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
432  SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
433  }while(0)
434 
435 #if defined(SYSCFG_SWPR2_PAGE63)
436 
440 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
441  SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
442  }while(0)
443 #endif /* SYSCFG_SWPR2_PAGE63 */
444 
448 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
449  SYSCFG->SKR = 0x53;\
450  }while(0)
451 
455 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
456 
460 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
461  SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
462  }while(0)
463 
464 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
465  CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
466  }while(0)
467 
472 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
473 
478 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
479 
484 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
485 
490 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
491 
499 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
500 
503 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
504 
512 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
513  SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
514  }while(0)
515 
516 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
517  CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
518  }while(0)
519 
524 /* Private macros ------------------------------------------------------------*/
529 #define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \
530  ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \
531  ((__FREQ__) == HAL_TICK_FREQ_1KHZ))
532 
541 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
542  (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
543  (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
544  (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
545  (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
546  (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
547 
548 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
549  ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
550  ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
551  ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
552 
553 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
554 
555 #if defined(VREFBUF)
556 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
557  ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
558 
559 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
560  ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
561 
562 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
563 #endif /* VREFBUF */
564 
565 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
566 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
567  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
568  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
569  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
570 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
571 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
572  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
573  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
574 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
575 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
576  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
577  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
578 #else
579 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
580  (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
581 #endif
582 
586 /* Exported variables --------------------------------------------------------*/
587 
591 extern __IO uint32_t uwTick;
592 extern uint32_t uwTickPrio;
593 extern uint32_t uwTickFreq;
598 /* Exported functions --------------------------------------------------------*/
599 
608 /* Initialization and de-initialization functions ******************************/
609 HAL_StatusTypeDef HAL_Init(void);
610 HAL_StatusTypeDef HAL_DeInit(void);
611 void HAL_MspInit(void);
612 void HAL_MspDeInit(void);
613 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
614 
623 /* Peripheral Control functions ************************************************/
624 void HAL_IncTick(void);
625 void HAL_Delay(uint32_t Delay);
626 uint32_t HAL_GetTick(void);
627 uint32_t HAL_GetTickPrio(void);
628 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
629 uint32_t HAL_GetTickFreq(void);
630 void HAL_SuspendTick(void);
631 void HAL_ResumeTick(void);
632 uint32_t HAL_GetHalVersion(void);
633 uint32_t HAL_GetREVID(void);
634 uint32_t HAL_GetDEVID(void);
635 uint32_t HAL_GetUIDw0(void);
636 uint32_t HAL_GetUIDw1(void);
637 uint32_t HAL_GetUIDw2(void);
638 
647 /* DBGMCU Peripheral Control functions *****************************************/
648 void HAL_DBGMCU_EnableDBGSleepMode(void);
649 void HAL_DBGMCU_DisableDBGSleepMode(void);
650 void HAL_DBGMCU_EnableDBGStopMode(void);
651 void HAL_DBGMCU_DisableDBGStopMode(void);
652 void HAL_DBGMCU_EnableDBGStandbyMode(void);
653 void HAL_DBGMCU_DisableDBGStandbyMode(void);
654 
663 /* SYSCFG Control functions ****************************************************/
664 void HAL_SYSCFG_SRAM2Erase(void);
665 void HAL_SYSCFG_EnableMemorySwappingBank(void);
666 void HAL_SYSCFG_DisableMemorySwappingBank(void);
667 
668 #if defined(VREFBUF)
669 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
670 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
671 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
672 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
673 void HAL_SYSCFG_DisableVREFBUF(void);
674 #endif /* VREFBUF */
675 
676 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
677 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
678 
695 #ifdef __cplusplus
696 }
697 #endif
698 
699 #endif /* STM32L4xx_HAL_H */
700 
701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_GetTickPrio
uint32_t HAL_GetTickPrio(void)
This function returns a tick priority.
Definition: stm32l4xx_hal.c:346
HAL_SYSCFG_VREFBUF_VoltageScalingConfig
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
Configure the internal voltage reference buffer voltage scale.
Definition: stm32l4xx_hal.c:649
HAL_DBGMCU_DisableDBGSleepMode
void HAL_DBGMCU_DisableDBGSleepMode(void)
Disable the Debug Module during SLEEP mode.
Definition: stm32l4xx_hal.c:529
HAL_DBGMCU_DisableDBGStopMode
void HAL_DBGMCU_DisableDBGStopMode(void)
Disable the Debug Module during STOP0/STOP1/STOP2 modes.
Definition: stm32l4xx_hal.c:547
HAL_SYSCFG_DisableMemorySwappingBank
void HAL_SYSCFG_DisableMemorySwappingBank(void)
Disable the Internal FLASH Bank Swapping.
Definition: stm32l4xx_hal.c:632
HAL_DBGMCU_EnableDBGStopMode
void HAL_DBGMCU_EnableDBGStopMode(void)
Enable the Debug Module during STOP0/STOP1/STOP2 modes.
Definition: stm32l4xx_hal.c:538
HAL_SuspendTick
void HAL_SuspendTick(void)
Suspend Tick increment.
Definition: stm32l4xx_hal.c:420
HAL_SYSCFG_EnableIOAnalogSwitchBooster
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
Enable the I/O analog switch voltage booster.
Definition: stm32l4xx_hal.c:726
HAL_MspDeInit
void HAL_MspDeInit(void)
DeInitialize the MSP.
Definition: stm32l4xx_hal.c:236
HAL_DeInit
HAL_StatusTypeDef HAL_DeInit(void)
De-initialize common part of the HAL and stop the source of time base.
Definition: stm32l4xx_hal.c:196
HAL_DBGMCU_DisableDBGStandbyMode
void HAL_DBGMCU_DisableDBGStandbyMode(void)
Disable the Debug Module during STANDBY mode.
Definition: stm32l4xx_hal.c:565
HAL_SYSCFG_VREFBUF_HighImpedanceConfig
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
Configure the internal voltage reference buffer high impedance mode.
Definition: stm32l4xx_hal.c:665
HAL_Delay
void HAL_Delay(uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
Definition: stm32l4xx_hal.c:394
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
HAL_DBGMCU_EnableDBGStandbyMode
void HAL_DBGMCU_EnableDBGStandbyMode(void)
Enable the Debug Module during STANDBY mode.
Definition: stm32l4xx_hal.c:556
HAL_SetTickFreq
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
Set new tick Freq.
Definition: stm32l4xx_hal.c:356
HAL_DBGMCU_EnableDBGSleepMode
void HAL_DBGMCU_EnableDBGSleepMode(void)
Enable the Debug Module during SLEEP mode.
Definition: stm32l4xx_hal.c:520
HAL_GetHalVersion
uint32_t HAL_GetHalVersion(void)
Return the HAL revision.
Definition: stm32l4xx_hal.c:446
HAL_IncTick
void HAL_IncTick(void)
This function is called to increment a global variable "uwTick" used as application time base...
Definition: stm32l4xx_hal.c:326
HAL_GetUIDw2
uint32_t HAL_GetUIDw2(void)
Return the third word of the unique device identifier (UID based on 96 bits)
Definition: stm32l4xx_hal.c:491
HAL_GetREVID
uint32_t HAL_GetREVID(void)
Return the device revision identifier.
Definition: stm32l4xx_hal.c:455
HAL_GetDEVID
uint32_t HAL_GetDEVID(void)
Return the device identifier.
Definition: stm32l4xx_hal.c:464
HAL_MspInit
void HAL_MspInit(void)
Initialize the MSP.
Definition: stm32l4xx_hal.c:225
HAL_SYSCFG_DisableVREFBUF
void HAL_SYSCFG_DisableVREFBUF(void)
Disable the Internal Voltage Reference buffer (VREFBUF).
Definition: stm32l4xx_hal.c:715
HAL_Init
HAL_StatusTypeDef HAL_Init(void)
Configure the Flash prefetch, the Instruction and Data caches, the time base source, NVIC and any required global low level hardware by calling the HAL_MspInit() callback function to be optionally defined in user file stm32l4xx_hal_msp.c.
Definition: stm32l4xx_hal.c:152
HAL_GetUIDw0
uint32_t HAL_GetUIDw0(void)
Return the first word of the unique device identifier (UID based on 96 bits)
Definition: stm32l4xx_hal.c:473
uwTick
__IO uint32_t uwTick
Definition: stm32l4xx_hal.c:90
HAL_InitTick
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
This function configures the source of the time base: The time source is configured to have 1ms time ...
Definition: stm32l4xx_hal.c:259
HAL_SYSCFG_VREFBUF_TrimmingConfig
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
Tune the Internal Voltage Reference buffer (VREFBUF).
Definition: stm32l4xx_hal.c:677
HAL_GetUIDw1
uint32_t HAL_GetUIDw1(void)
Return the second word of the unique device identifier (UID based on 96 bits)
Definition: stm32l4xx_hal.c:482
HAL_SYSCFG_EnableVREFBUF
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
Enable the Internal Voltage Reference buffer (VREFBUF).
Definition: stm32l4xx_hal.c:689
HAL_SYSCFG_DisableIOAnalogSwitchBooster
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
Disable the I/O analog switch voltage booster.
Definition: stm32l4xx_hal.c:736
HAL_SYSCFG_SRAM2Erase
void HAL_SYSCFG_SRAM2Erase(void)
Start a hardware SRAM2 erase operation.
Definition: stm32l4xx_hal.c:598
uwTickFreq
uint32_t uwTickFreq
Definition: stm32l4xx_hal.c:92
HAL_ResumeTick
void HAL_ResumeTick(void)
Resume Tick increment.
Definition: stm32l4xx_hal.c:436
uwTickPrio
uint32_t uwTickPrio
Definition: stm32l4xx_hal.c:91
HAL_GetTickFreq
uint32_t HAL_GetTickFreq(void)
Return tick frequency.
Definition: stm32l4xx_hal.c:378
HAL_SYSCFG_EnableMemorySwappingBank
void HAL_SYSCFG_EnableMemorySwappingBank(void)
Enable the Internal FLASH Bank Swapping.
Definition: stm32l4xx_hal.c:617