STM32L4xx_HAL_Driver  1.14.0
Functions
AHB1
STM32L4xx_LL_Driver » BUS » BUS Exported Functions

Functions

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
 Enable AHB1 peripherals clock. AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock
AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock. More...
 
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
 Check if AHB1 peripheral clock is enabled or not AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
 Disable AHB1 peripherals clock. AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock
AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
 Force AHB1 peripherals reset. AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
 Release AHB1 peripherals reset. AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
 Enable AHB1 peripheral clocks in Sleep and Stop modes AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
 Disable AHB1 peripheral clocks in Sleep and Stop modes AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep. More...
 

Detailed Description

Function Documentation

◆ LL_AHB1_GRP1_DisableClock()

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t  Periphs)

Disable AHB1 peripherals clock. AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock
AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
None

Definition at line 386 of file stm32l4xx_ll_bus.h.

387 {
388  CLEAR_BIT(RCC->AHB1ENR, Periphs);
389 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_AHB1_GRP1_DisableClockStopSleep()

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep ( uint32_t  Periphs)

Disable AHB1 peripheral clocks in Sleep and Stop modes AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep
AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
None

Definition at line 508 of file stm32l4xx_ll_bus.h.

509 {
510  CLEAR_BIT(RCC->AHB1SMENR, Periphs);
511 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_AHB1_GRP1_EnableClock()

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t  Periphs)

Enable AHB1 peripherals clock. AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock
AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock
AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
None

Definition at line 326 of file stm32l4xx_ll_bus.h.

327 {
328  __IO uint32_t tmpreg;
329  SET_BIT(RCC->AHB1ENR, Periphs);
330  /* Delay after an RCC peripheral clock enabling */
331  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
332  (void)tmpreg;
333 }

◆ LL_AHB1_GRP1_EnableClockStopSleep()

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep ( uint32_t  Periphs)

Enable AHB1 peripheral clocks in Sleep and Stop modes AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep
AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
None

Definition at line 474 of file stm32l4xx_ll_bus.h.

475 {
476  __IO uint32_t tmpreg;
477  SET_BIT(RCC->AHB1SMENR, Periphs);
478  /* Delay after an RCC peripheral clock enabling */
479  tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
480  (void)tmpreg;
481 }

◆ LL_AHB1_GRP1_ForceReset()

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t  Periphs)

Force AHB1 peripherals reset. AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
None

Definition at line 415 of file stm32l4xx_ll_bus.h.

416 {
417  SET_BIT(RCC->AHB1RSTR, Periphs);
418 }

◆ LL_AHB1_GRP1_IsEnabledClock()

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t  Periphs)

Check if AHB1 peripheral clock is enabled or not AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
Stateof Periphs (1 or 0).

Definition at line 358 of file stm32l4xx_ll_bus.h.

359 {
360  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
361 }

◆ LL_AHB1_GRP1_ReleaseReset()

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t  Periphs)

Release AHB1 peripherals reset. AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_TSC
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_GFXMMU (*)
(*) value not defined in all devices.
Return values
None

Definition at line 444 of file stm32l4xx_ll_bus.h.

445 {
446  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
447 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)