STM32L4xx_HAL_Driver  1.14.0
Functions
AHB2
STM32L4xx_LL_Driver » BUS » BUS Exported Functions

Functions

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
 Enable AHB2 peripherals clock. AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock
AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock
AHB2ENR AESEN LL_AHB2_GRP1_EnableClock
AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock
AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock
AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock. More...
 
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
 Check if AHB2 peripheral clock is enabled or not AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock. More...
 
__STATIC_INLINE void LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
 Disable AHB2 peripherals clock. AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock
AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock
AHB2ENR AESEN LL_AHB2_GRP1_DisableClock
AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock
AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock
AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock. More...
 
__STATIC_INLINE void LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
 Force AHB2 peripherals reset. AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset
AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset
AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset
AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset
AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset. More...
 
__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
 Release AHB2 peripherals reset. AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset. More...
 
__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
 Enable AHB2 peripheral clocks in Sleep and Stop modes AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep. More...
 
__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
 Disable AHB2 peripheral clocks in Sleep and Stop modes AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep. More...
 

Detailed Description

Function Documentation

◆ LL_AHB2_GRP1_DisableClock()

__STATIC_INLINE void LL_AHB2_GRP1_DisableClock ( uint32_t  Periphs)

Disable AHB2 peripherals clock. AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock
AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock
AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock
AHB2ENR AESEN LL_AHB2_GRP1_DisableClock
AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock
AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock
AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
None

Definition at line 658 of file stm32l4xx_ll_bus.h.

659 {
660  CLEAR_BIT(RCC->AHB2ENR, Periphs);
661 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_AHB2_GRP1_DisableClockStopSleep()

__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep ( uint32_t  Periphs)

Disable AHB2 peripheral clocks in Sleep and Stop modes AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep
AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_SRAM2
  • LL_AHB2_GRP1_PERIPH_SRAM3 (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
None

Definition at line 856 of file stm32l4xx_ll_bus.h.

857 {
858  CLEAR_BIT(RCC->AHB2SMENR, Periphs);
859 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_AHB2_GRP1_EnableClock()

__STATIC_INLINE void LL_AHB2_GRP1_EnableClock ( uint32_t  Periphs)

Enable AHB2 peripherals clock. AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock
AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock
AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock
AHB2ENR AESEN LL_AHB2_GRP1_EnableClock
AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock
AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock
AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
None

Definition at line 562 of file stm32l4xx_ll_bus.h.

563 {
564  __IO uint32_t tmpreg;
565  SET_BIT(RCC->AHB2ENR, Periphs);
566  /* Delay after an RCC peripheral clock enabling */
567  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
568  (void)tmpreg;
569 }

◆ LL_AHB2_GRP1_EnableClockStopSleep()

__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep ( uint32_t  Periphs)

Enable AHB2 peripheral clocks in Sleep and Stop modes AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep
AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_SRAM2
  • LL_AHB2_GRP1_PERIPH_SRAM3 (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
None

Definition at line 802 of file stm32l4xx_ll_bus.h.

803 {
804  __IO uint32_t tmpreg;
805  SET_BIT(RCC->AHB2SMENR, Periphs);
806  /* Delay after an RCC peripheral clock enabling */
807  tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
808  (void)tmpreg;
809 }

◆ LL_AHB2_GRP1_ForceReset()

__STATIC_INLINE void LL_AHB2_GRP1_ForceReset ( uint32_t  Periphs)

Force AHB2 peripherals reset. AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset
AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset
AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset
AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset
AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset
AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset
AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
None

Definition at line 705 of file stm32l4xx_ll_bus.h.

706 {
707  SET_BIT(RCC->AHB2RSTR, Periphs);
708 }

◆ LL_AHB2_GRP1_IsEnabledClock()

__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock ( uint32_t  Periphs)

Check if AHB2 peripheral clock is enabled or not AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock
AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
Stateof Periphs (1 or 0).

Definition at line 612 of file stm32l4xx_ll_bus.h.

613 {
614  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
615 }

◆ LL_AHB2_GRP1_ReleaseReset()

__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset ( uint32_t  Periphs)

Release AHB2 peripherals reset. AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset
AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB2_GRP1_PERIPH_ALL
  • LL_AHB2_GRP1_PERIPH_GPIOA
  • LL_AHB2_GRP1_PERIPH_GPIOB
  • LL_AHB2_GRP1_PERIPH_GPIOC
  • LL_AHB2_GRP1_PERIPH_GPIOD (*)
  • LL_AHB2_GRP1_PERIPH_GPIOE (*)
  • LL_AHB2_GRP1_PERIPH_GPIOF (*)
  • LL_AHB2_GRP1_PERIPH_GPIOG (*)
  • LL_AHB2_GRP1_PERIPH_GPIOH
  • LL_AHB2_GRP1_PERIPH_GPIOI (*)
  • LL_AHB2_GRP1_PERIPH_OTGFS (*)
  • LL_AHB2_GRP1_PERIPH_ADC
  • LL_AHB2_GRP1_PERIPH_DCMI (*)
  • LL_AHB2_GRP1_PERIPH_AES (*)
  • LL_AHB2_GRP1_PERIPH_HASH (*)
  • LL_AHB2_GRP1_PERIPH_RNG
  • LL_AHB2_GRP1_PERIPH_OSPIM (*)
  • LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
(*) value not defined in all devices.
Return values
None

Definition at line 752 of file stm32l4xx_ll_bus.h.

753 {
754  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
755 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)