STM32L4xx_HAL_Driver  1.14.0
Slave Select Pin Management

Functions

__STATIC_INLINE void LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
 Set NSS mode. More...
 
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
 Get NSS mode CR1 SSM LL_SPI_GetNSSMode
CR2 SSOE LL_SPI_GetNSSMode. More...
 
__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx)
 Enable NSS pulse management. More...
 
__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx)
 Disable NSS pulse management. More...
 
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx)
 Check if NSS pulse is enabled. More...
 

Detailed Description

Function Documentation

◆ LL_SPI_DisableNSSPulseMgt()

__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt ( SPI_TypeDef *  SPIx)

Disable NSS pulse management.

Note
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. CR2 NSSP LL_SPI_DisableNSSPulseMgt
Parameters
SPIxSPI Instance
Return values
None

Definition at line 875 of file stm32l4xx_ll_spi.h.

876 {
877  CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
878 }
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_SPI_EnableNSSPulseMgt()

__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt ( SPI_TypeDef *  SPIx)

Enable NSS pulse management.

Note
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. CR2 NSSP LL_SPI_EnableNSSPulseMgt
Parameters
SPIxSPI Instance
Return values
None

Definition at line 863 of file stm32l4xx_ll_spi.h.

864 {
865  SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
866 }

◆ LL_SPI_GetNSSMode()

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef *  SPIx)

Get NSS mode CR1 SSM LL_SPI_GetNSSMode
CR2 SSOE LL_SPI_GetNSSMode.

Parameters
SPIxSPI Instance
Return values
Returnedvalue can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 849 of file stm32l4xx_ll_spi.h.

850 {
851  register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
852  register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
853  return (Ssm | Ssoe);
854 }

◆ LL_SPI_IsEnabledNSSPulse()

__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse ( SPI_TypeDef *  SPIx)

Check if NSS pulse is enabled.

Note
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. CR2 NSSP LL_SPI_IsEnabledNSSPulse
Parameters
SPIxSPI Instance
Return values
Stateof bit (1 or 0).

Definition at line 887 of file stm32l4xx_ll_spi.h.

888 {
889  return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
890 }

◆ LL_SPI_SetNSSMode()

__STATIC_INLINE void LL_SPI_SetNSSMode ( SPI_TypeDef *  SPIx,
uint32_t  NSS 
)

Set NSS mode.

Note
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. CR1 SSM LL_SPI_SetNSSMode
CR2 SSOE LL_SPI_SetNSSMode
Parameters
SPIxSPI Instance
NSSThis parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values
None

Definition at line 833 of file stm32l4xx_ll_spi.h.

834 {
835  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
836  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
837 }
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)