STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_adc_ex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_HAL_ADC_EX_H
22 #define STM32L4xx_HAL_ADC_EX_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Ratio;
52  uint32_t RightBitShift;
54 } ADC_InjOversamplingTypeDef;
55 
72 typedef struct
73 {
74  uint32_t InjectedChannel;
78  uint32_t InjectedRank;
83  uint32_t InjectedSamplingTime;
94  uint32_t InjectedSingleDiff;
106  uint32_t InjectedOffsetNumber;
110  uint32_t InjectedOffset;
117  uint32_t InjectedNbrOfConversion;
123  FunctionalState InjectedDiscontinuousConvMode;
133  FunctionalState AutoInjectedConv;
142  FunctionalState QueueInjectedContext;
153  uint32_t ExternalTrigInjecConv;
159  uint32_t ExternalTrigInjecConvEdge;
165  FunctionalState InjecOversamplingMode;
169  ADC_InjOversamplingTypeDef InjecOversampling;
172 } ADC_InjectionConfTypeDef;
173 
174 #if defined(ADC_MULTIMODE_SUPPORT)
175 
180 typedef struct
181 {
182  uint32_t Mode;
185  uint32_t DMAAccessMode;
189  uint32_t TwoSamplingDelay;
194 } ADC_MultiModeTypeDef;
195 #endif /* ADC_MULTIMODE_SUPPORT */
196 
201 /* Exported constants --------------------------------------------------------*/
202 
210 /* ADC group regular trigger sources for all ADC instances */
211 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE)
212 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)
213 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)
214 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
215 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)
216 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
217 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)
218 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
219 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
220 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
221 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)
222 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)
223 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
224 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)
225 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)
226 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)
227 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)
235 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL)
236 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0)
237 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1)
238 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN)
246 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED)
247 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED)
255 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U)
256 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1)
257 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2)
258 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3)
259 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4)
267 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1)
268 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2)
269 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3)
270 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4)
275 #if defined(ADC_MULTIMODE_SUPPORT)
276 
279 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT)
280 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT)
281 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL)
282 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT)
283 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN)
284 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)
285 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)
286 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)
291 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL)
292 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1)
293 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA)
301 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)
302 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)
303 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)
304 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)
305 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)
306 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)
307 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)
308 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)
309 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)
310 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)
311 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)
312 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)
320 #endif /* ADC_MULTIMODE_SUPPORT */
321 
325 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR)
326 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED)
327 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED)
335 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
336 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
337  ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
338  ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
339  ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
340  ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
341  ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
342 #else
343 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
344  ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
345  ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
346  ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
347  ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
348  ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
349 #endif
350 
357 #if defined(ADC_SMPR1_SMPPLUS)
358 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
359  ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
360  ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
361  ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
362 #else
363 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
364  ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
365  ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
366  ADC_SMPR1_SMP0)
367 #endif
368 
375 /* ADC_CFGR fields of parameters that can be updated when no conversion
376  (neither regular nor injected) is on-going */
377 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
378 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
379 #else
380 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
381 #endif
382 
386 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
387 
390 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL)
391 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE)
395 #endif
396 
401 /* Exported macros -----------------------------------------------------------*/
402 
403 #if defined(ADC_MULTIMODE_SUPPORT)
404 
422 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
423  LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
424 
428 #endif /* ADC_MULTIMODE_SUPPORT */
429 
430 /* Private macros ------------------------------------------------------------*/
431 
435 /* Macro reserved for internal HAL driver usage, not intended to be used in */
436 /* code of final user. */
437 
444 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
445  (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
446 
452 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
453  (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
454  ) ? RESET : SET)
455 
461 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
462  (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
463 
470 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
471 #define ADC_IS_INDEPENDENT(__HANDLE__) \
472  ( ( ( ((__HANDLE__)->Instance) == ADC3) \
473  )? \
474  SET \
475  : \
476  RESET \
477  )
478 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
479 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
480 #elif defined (STM32L412xx) || defined (STM32L422xx)
481 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
482 #endif
483 
490 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
491 
497 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
498 
504 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
505 
511 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
512 
518 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
519 
525 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
526 
532 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
533 
539 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
540 
546 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
547 
553 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
554 
560 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
561 
567 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
568 
574 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
575 
576 #if defined(ADC_MULTIMODE_SUPPORT)
577 
582 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
583 #endif /* ADC_MULTIMODE_SUPPORT */
584 
597 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
598  ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
599 
612 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
613  ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
614 
626 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
627  ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
628  ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
629  ((__THRESHOLD__) << 2UL) \
630  )
631 
637 #if defined(ADC_MULTIMODE_SUPPORT)
638 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
639  ADC_CCR_CKMODE | \
640  ADC_CCR_PRESC | \
641  ADC_CCR_VBATEN | \
642  ADC_CCR_TSEN | \
643  ADC_CCR_VREFEN | \
644  ADC_CCR_MDMA | \
645  ADC_CCR_DMACFG | \
646  ADC_CCR_DELAY | \
647  ADC_CCR_DUAL)
648 #else
649 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
650  ADC_CCR_CKMODE | \
651  ADC_CCR_PRESC | \
652  ADC_CCR_VBATEN | \
653  ADC_CCR_TSEN | \
654  ADC_CCR_VREFEN)
655 
656 #endif /* ADC_MULTIMODE_SUPPORT */
657 
658 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
659 
666 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
667  ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
668 #endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
669 
670 
676 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
677 /* The temperature sensor measurement path (channel 17) is available on ADC1 */
678 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
679 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
680 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
681 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
682 #endif
683 
689 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
690 /* The battery voltage measurement path (channel 18) is available on ADC1 */
691 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
692 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
693 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
694 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3))
695 #endif
696 
702 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */
703 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
704 
710 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
711 
717 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
718 
719 
726 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
727 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
728  (((__CHANNEL__) == ADC_CHANNEL_1) || \
729  ((__CHANNEL__) == ADC_CHANNEL_2) || \
730  ((__CHANNEL__) == ADC_CHANNEL_3) || \
731  ((__CHANNEL__) == ADC_CHANNEL_4) || \
732  ((__CHANNEL__) == ADC_CHANNEL_5) || \
733  ((__CHANNEL__) == ADC_CHANNEL_6) || \
734  ((__CHANNEL__) == ADC_CHANNEL_7) || \
735  ((__CHANNEL__) == ADC_CHANNEL_8) || \
736  ((__CHANNEL__) == ADC_CHANNEL_9) || \
737  ((__CHANNEL__) == ADC_CHANNEL_10) || \
738  ((__CHANNEL__) == ADC_CHANNEL_11) || \
739  ((__CHANNEL__) == ADC_CHANNEL_12) || \
740  ((__CHANNEL__) == ADC_CHANNEL_13) || \
741  ((__CHANNEL__) == ADC_CHANNEL_14) || \
742  ((__CHANNEL__) == ADC_CHANNEL_15) || \
743  ((__CHANNEL__) == ADC_CHANNEL_16) || \
744  ((__CHANNEL__) == ADC_CHANNEL_17) || \
745  ((__CHANNEL__) == ADC_CHANNEL_18) || \
746  ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
747  ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
748  ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
749  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \
750  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2)))
751 #elif defined (STM32L412xx) || defined (STM32L422xx)
752 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
753  (((__CHANNEL__) == ADC_CHANNEL_1) || \
754  ((__CHANNEL__) == ADC_CHANNEL_2) || \
755  ((__CHANNEL__) == ADC_CHANNEL_3) || \
756  ((__CHANNEL__) == ADC_CHANNEL_4) || \
757  ((__CHANNEL__) == ADC_CHANNEL_5) || \
758  ((__CHANNEL__) == ADC_CHANNEL_6) || \
759  ((__CHANNEL__) == ADC_CHANNEL_7) || \
760  ((__CHANNEL__) == ADC_CHANNEL_8) || \
761  ((__CHANNEL__) == ADC_CHANNEL_9) || \
762  ((__CHANNEL__) == ADC_CHANNEL_10) || \
763  ((__CHANNEL__) == ADC_CHANNEL_11) || \
764  ((__CHANNEL__) == ADC_CHANNEL_12) || \
765  ((__CHANNEL__) == ADC_CHANNEL_13) || \
766  ((__CHANNEL__) == ADC_CHANNEL_14) || \
767  ((__CHANNEL__) == ADC_CHANNEL_15) || \
768  ((__CHANNEL__) == ADC_CHANNEL_16) || \
769  ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
770  ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
771  ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
772  ((((__HANDLE__)->Instance) == ADC2) && \
773  (((__CHANNEL__) == ADC_CHANNEL_1) || \
774  ((__CHANNEL__) == ADC_CHANNEL_2) || \
775  ((__CHANNEL__) == ADC_CHANNEL_3) || \
776  ((__CHANNEL__) == ADC_CHANNEL_4) || \
777  ((__CHANNEL__) == ADC_CHANNEL_7) || \
778  ((__CHANNEL__) == ADC_CHANNEL_8) || \
779  ((__CHANNEL__) == ADC_CHANNEL_9) || \
780  ((__CHANNEL__) == ADC_CHANNEL_10) || \
781  ((__CHANNEL__) == ADC_CHANNEL_11) || \
782  ((__CHANNEL__) == ADC_CHANNEL_12) || \
783  ((__CHANNEL__) == ADC_CHANNEL_13) || \
784  ((__CHANNEL__) == ADC_CHANNEL_14) || \
785  ((__CHANNEL__) == ADC_CHANNEL_15) || \
786  ((__CHANNEL__) == ADC_CHANNEL_16) )))
787 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
788 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
789  (((__CHANNEL__) == ADC_CHANNEL_1) || \
790  ((__CHANNEL__) == ADC_CHANNEL_2) || \
791  ((__CHANNEL__) == ADC_CHANNEL_3) || \
792  ((__CHANNEL__) == ADC_CHANNEL_4) || \
793  ((__CHANNEL__) == ADC_CHANNEL_5) || \
794  ((__CHANNEL__) == ADC_CHANNEL_6) || \
795  ((__CHANNEL__) == ADC_CHANNEL_7) || \
796  ((__CHANNEL__) == ADC_CHANNEL_8) || \
797  ((__CHANNEL__) == ADC_CHANNEL_9) || \
798  ((__CHANNEL__) == ADC_CHANNEL_10) || \
799  ((__CHANNEL__) == ADC_CHANNEL_11) || \
800  ((__CHANNEL__) == ADC_CHANNEL_12) || \
801  ((__CHANNEL__) == ADC_CHANNEL_13) || \
802  ((__CHANNEL__) == ADC_CHANNEL_14) || \
803  ((__CHANNEL__) == ADC_CHANNEL_15) || \
804  ((__CHANNEL__) == ADC_CHANNEL_16) || \
805  ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
806  ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
807  ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
808  ((((__HANDLE__)->Instance) == ADC2) && \
809  (((__CHANNEL__) == ADC_CHANNEL_1) || \
810  ((__CHANNEL__) == ADC_CHANNEL_2) || \
811  ((__CHANNEL__) == ADC_CHANNEL_3) || \
812  ((__CHANNEL__) == ADC_CHANNEL_4) || \
813  ((__CHANNEL__) == ADC_CHANNEL_5) || \
814  ((__CHANNEL__) == ADC_CHANNEL_6) || \
815  ((__CHANNEL__) == ADC_CHANNEL_7) || \
816  ((__CHANNEL__) == ADC_CHANNEL_8) || \
817  ((__CHANNEL__) == ADC_CHANNEL_9) || \
818  ((__CHANNEL__) == ADC_CHANNEL_10) || \
819  ((__CHANNEL__) == ADC_CHANNEL_11) || \
820  ((__CHANNEL__) == ADC_CHANNEL_12) || \
821  ((__CHANNEL__) == ADC_CHANNEL_13) || \
822  ((__CHANNEL__) == ADC_CHANNEL_14) || \
823  ((__CHANNEL__) == ADC_CHANNEL_15) || \
824  ((__CHANNEL__) == ADC_CHANNEL_16) || \
825  ((__CHANNEL__) == ADC_CHANNEL_17) || \
826  ((__CHANNEL__) == ADC_CHANNEL_18) || \
827  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \
828  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \
829  ((((__HANDLE__)->Instance) == ADC3) && \
830  (((__CHANNEL__) == ADC_CHANNEL_1) || \
831  ((__CHANNEL__) == ADC_CHANNEL_2) || \
832  ((__CHANNEL__) == ADC_CHANNEL_3) || \
833  ((__CHANNEL__) == ADC_CHANNEL_4) || \
834  ((__CHANNEL__) == ADC_CHANNEL_6) || \
835  ((__CHANNEL__) == ADC_CHANNEL_7) || \
836  ((__CHANNEL__) == ADC_CHANNEL_8) || \
837  ((__CHANNEL__) == ADC_CHANNEL_9) || \
838  ((__CHANNEL__) == ADC_CHANNEL_10) || \
839  ((__CHANNEL__) == ADC_CHANNEL_11) || \
840  ((__CHANNEL__) == ADC_CHANNEL_12) || \
841  ((__CHANNEL__) == ADC_CHANNEL_13) || \
842  ((__CHANNEL__) == ADC_CHANNEL_14) || \
843  ((__CHANNEL__) == ADC_CHANNEL_15) || \
844  ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
845  ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
846  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \
847  ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) )))
848 #endif
849 
856 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
857 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
858  ((__CHANNEL__) == ADC_CHANNEL_2) || \
859  ((__CHANNEL__) == ADC_CHANNEL_3) || \
860  ((__CHANNEL__) == ADC_CHANNEL_4) || \
861  ((__CHANNEL__) == ADC_CHANNEL_5) || \
862  ((__CHANNEL__) == ADC_CHANNEL_6) || \
863  ((__CHANNEL__) == ADC_CHANNEL_7) || \
864  ((__CHANNEL__) == ADC_CHANNEL_8) || \
865  ((__CHANNEL__) == ADC_CHANNEL_9) || \
866  ((__CHANNEL__) == ADC_CHANNEL_10) || \
867  ((__CHANNEL__) == ADC_CHANNEL_11) || \
868  ((__CHANNEL__) == ADC_CHANNEL_12) || \
869  ((__CHANNEL__) == ADC_CHANNEL_13) || \
870  ((__CHANNEL__) == ADC_CHANNEL_14) || \
871  ((__CHANNEL__) == ADC_CHANNEL_15) )
872 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
873  /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
874  channels 0, 16 to 18 can be only used in single-ended mode.
875  For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
876  channels 4, 5 and 13 to 18 can only be used in single-ended mode. */
877 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \
878  (((__HANDLE__)->Instance) == ADC2)) && \
879  (((__CHANNEL__) == ADC_CHANNEL_1) || \
880  ((__CHANNEL__) == ADC_CHANNEL_2) || \
881  ((__CHANNEL__) == ADC_CHANNEL_3) || \
882  ((__CHANNEL__) == ADC_CHANNEL_4) || \
883  ((__CHANNEL__) == ADC_CHANNEL_5) || \
884  ((__CHANNEL__) == ADC_CHANNEL_6) || \
885  ((__CHANNEL__) == ADC_CHANNEL_7) || \
886  ((__CHANNEL__) == ADC_CHANNEL_8) || \
887  ((__CHANNEL__) == ADC_CHANNEL_9) || \
888  ((__CHANNEL__) == ADC_CHANNEL_10) || \
889  ((__CHANNEL__) == ADC_CHANNEL_11) || \
890  ((__CHANNEL__) == ADC_CHANNEL_12) || \
891  ((__CHANNEL__) == ADC_CHANNEL_13) || \
892  ((__CHANNEL__) == ADC_CHANNEL_14) || \
893  ((__CHANNEL__) == ADC_CHANNEL_15))) || \
894  ((((__HANDLE__)->Instance) == ADC3) && \
895  (((__CHANNEL__) == ADC_CHANNEL_1) || \
896  ((__CHANNEL__) == ADC_CHANNEL_2) || \
897  ((__CHANNEL__) == ADC_CHANNEL_3) || \
898  ((__CHANNEL__) == ADC_CHANNEL_6) || \
899  ((__CHANNEL__) == ADC_CHANNEL_7) || \
900  ((__CHANNEL__) == ADC_CHANNEL_8) || \
901  ((__CHANNEL__) == ADC_CHANNEL_9) || \
902  ((__CHANNEL__) == ADC_CHANNEL_10) || \
903  ((__CHANNEL__) == ADC_CHANNEL_11) || \
904  ((__CHANNEL__) == ADC_CHANNEL_12) )))
905 #endif
906 
912 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
913  ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
914 
920 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
921  ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
922  ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
923  ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
924  ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
925 
931 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
932  ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
933  ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
934  ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
935 
942 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
943  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
944  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
945  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
946  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
947  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
948  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
949  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
950  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
951  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
952  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
953  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
954  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
955  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
956  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
957  ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
958  ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
959 
965 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
966  ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
967  ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
968  ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
969 
970 #if defined(ADC_MULTIMODE_SUPPORT)
971 
976 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
977  ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
978  ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
979  ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
980  ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
981  ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
982  ((__MODE__) == ADC_DUALMODE_INTERL) || \
983  ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
984 
990 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
991  ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
992  ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
993 
999 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
1000  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
1001  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
1002  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
1003  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
1004  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
1005  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
1006  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
1007  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
1008  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
1009  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
1010  ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
1011 #endif /* ADC_MULTIMODE_SUPPORT */
1012 
1018 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
1019  ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
1020  ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
1021 
1027 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
1028  ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
1029  ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
1030  ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
1031  ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
1032  ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
1033  ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
1034 
1040 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
1041  ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
1042  ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
1043 
1049 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
1050  ((__EVENT__) == ADC_AWD_EVENT) || \
1051  ((__EVENT__) == ADC_AWD2_EVENT) || \
1052  ((__EVENT__) == ADC_AWD3_EVENT) || \
1053  ((__EVENT__) == ADC_OVR_EVENT) || \
1054  ((__EVENT__) == ADC_JQOVF_EVENT) )
1055 
1061 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
1062  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
1063  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
1064  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
1065  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
1066  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
1067  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
1068  ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
1069 
1075 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
1076  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
1077  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
1078  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
1079  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
1080  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
1081  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
1082  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
1083  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
1084 
1090 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
1091  ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
1092 
1098 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
1099  ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
1100 
1109 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
1110 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \
1111  ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
1112 #else
1113 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
1114 #endif
1115 
1124 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
1125 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
1126 #else
1127 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
1128 #endif
1129 
1135 /* Exported functions --------------------------------------------------------*/
1143 /* IO operation functions *****************************************************/
1144 
1145 /* ADC calibration */
1146 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
1147 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
1148 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
1149  uint32_t CalibrationFactor);
1150 
1151 /* Blocking mode: Polling */
1152 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
1153 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
1154 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
1155 
1156 /* Non-blocking mode: Interruption */
1157 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
1158 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
1159 
1160 #if defined(ADC_MULTIMODE_SUPPORT)
1161 /* ADC multimode */
1162 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
1163 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
1164 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
1165 #endif /* ADC_MULTIMODE_SUPPORT */
1166 
1167 /* ADC retrieve conversion value intended to be used with polling or interruption */
1168 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
1169 
1170 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
1171 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
1172 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
1173 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
1174 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
1175 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
1176 
1177 /* ADC group regular conversions stop */
1178 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
1179 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
1180 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
1181 #if defined(ADC_MULTIMODE_SUPPORT)
1182 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
1183 #endif /* ADC_MULTIMODE_SUPPORT */
1184 
1192 /* Peripheral Control functions ***********************************************/
1193 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
1194 #if defined(ADC_MULTIMODE_SUPPORT)
1195 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
1196 #endif /* ADC_MULTIMODE_SUPPORT */
1197 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
1198 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
1199 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
1200 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
1201 
1218 #ifdef __cplusplus
1219 }
1220 #endif
1221 
1222 #endif /* STM32L4xx_HAL_ADC_EX_H */
1223 
1224 
1225 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_ADCEx_DisableInjectedQueue
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
Disable Injected Queue.
Definition: stm32l4xx_hal_adc_ex.c:2224
HAL_ADCEx_Calibration_SetValue
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conve...
Definition: stm32l4xx_hal_adc_ex.c:223
HAL_ADCEx_InjectedPollForConversion
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
Definition: stm32l4xx_hal_adc_ex.c:483
HAL_ADCEx_InjectedStop_IT
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion. Disable ADC peripher...
Definition: stm32l4xx_hal_adc_ex.c:793
HAL_ADCEx_LevelOutOfWindow2Callback
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
Analog watchdog 2 callback in non-blocking mode.
Definition: stm32l4xx_hal_adc_ex.c:1204
ADC_InjectionConfTypeDef::InjectedRank
uint32_t InjectedRank
Definition: stm32l4xx_hal_adc_ex.h:78
ADC_MultiModeTypeDef::TwoSamplingDelay
uint32_t TwoSamplingDelay
Definition: stm32l4xx_hal_adc_ex.h:189
ADC_InjectionConfTypeDef::InjectedOffset
uint32_t InjectedOffset
Definition: stm32l4xx_hal_adc_ex.h:110
HAL_ADCEx_Calibration_GetValue
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Get the calibration factor.
Definition: stm32l4xx_hal_adc_ex.c:203
HAL_ADCEx_RegularStop_DMA
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode)...
Definition: stm32l4xx_hal_adc_ex.c:1370
HAL_ADCEx_InjectedGetValue
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
Definition: stm32l4xx_hal_adc_ex.c:1135
HAL_ADCEx_InjectedStop
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
Stop conversion of injected channels. Disable ADC peripheral if no regular conversion is on going...
Definition: stm32l4xx_hal_adc_ex.c:428
HAL_ADCEx_InjectedConvCpltCallback
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non-blocking mode.
Definition: stm32l4xx_hal_adc_ex.c:1170
ADC_InjectionConfTypeDef::InjectedChannel
uint32_t InjectedChannel
Definition: stm32l4xx_hal_adc_ex.h:74
HAL_ADCEx_Calibration_Start
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute thi...
Definition: stm32l4xx_hal_adc_ex.c:129
HAL_ADCEx_InjectedStart
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group.
Definition: stm32l4xx_hal_adc_ex.c:279
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_ADCEx_EnableInjectedQueue
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
Enable Injected Queue.
Definition: stm32l4xx_hal_adc_ex.c:2183
ADC_InjectionConfTypeDef::ExternalTrigInjecConvEdge
uint32_t ExternalTrigInjecConvEdge
Definition: stm32l4xx_hal_adc_ex.h:159
ADC_MultiModeTypeDef::Mode
uint32_t Mode
Definition: stm32l4xx_hal_adc_ex.h:182
HAL_ADCEx_MultiModeStart_DMA
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start MultiMode conversion and transfer regular results through DMA.
Definition: stm32l4xx_hal_adc_ex.c:860
HAL_ADCEx_InjectedQueueOverflowCallback
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
Injected context queue overflow callback.
Definition: stm32l4xx_hal_adc_ex.c:1189
ADC_InjectionConfTypeDef::InjectedSamplingTime
uint32_t InjectedSamplingTime
Definition: stm32l4xx_hal_adc_ex.h:83
ADC_InjOversamplingTypeDef::Ratio
uint32_t Ratio
Definition: stm32l4xx_hal_adc_ex.h:49
ADC_InjectionConfTypeDef::InjectedSingleDiff
uint32_t InjectedSingleDiff
Definition: stm32l4xx_hal_adc_ex.h:94
ADC_InjectionConfTypeDef::InjectedOffsetNumber
uint32_t InjectedOffsetNumber
Definition: stm32l4xx_hal_adc_ex.h:106
HAL_ADCEx_InjectedStart_IT
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of injected group with interruption.
Definition: stm32l4xx_hal_adc_ex.c:620
HAL_ADCEx_RegularMultiModeStop_DMA
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injec...
Definition: stm32l4xx_hal_adc_ex.c:1457
ADC_MultiModeTypeDef::DMAAccessMode
uint32_t DMAAccessMode
Definition: stm32l4xx_hal_adc_ex.h:185
ADC_HandleTypeDef
struct __ADC_HandleTypeDef else typedef struct endif ADC_HandleTypeDef
ADC handle Structure definition.
ADC_InjOversamplingTypeDef
ADC Injected Conversion Oversampling structure definition.
Definition: stm32l4xx_hal_adc_ex.h:47
ADC_InjectionConfTypeDef::AutoInjectedConv
FunctionalState AutoInjectedConv
Definition: stm32l4xx_hal_adc_ex.h:133
HAL_ADCEx_EnterADCDeepPowerDownMode
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
Enter ADC deep-power-down mode.
Definition: stm32l4xx_hal_adc_ex.c:2298
ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode
FunctionalState InjectedDiscontinuousConvMode
Definition: stm32l4xx_hal_adc_ex.h:123
ADC_InjectionConfTypeDef::InjectedNbrOfConversion
uint32_t InjectedNbrOfConversion
Definition: stm32l4xx_hal_adc_ex.h:117
HAL_ADCEx_EndOfSamplingCallback
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
End Of Sampling callback in non-blocking mode.
Definition: stm32l4xx_hal_adc_ex.c:1235
ADC_InjOversamplingTypeDef::RightBitShift
uint32_t RightBitShift
Definition: stm32l4xx_hal_adc_ex.h:52
HAL_ADCEx_InjectedConfigChannel
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configure a channel to be assigned to ADC group injected.
Definition: stm32l4xx_hal_adc_ex.c:1631
ADC_InjectionConfTypeDef::InjecOversampling
ADC_InjOversamplingTypeDef InjecOversampling
Definition: stm32l4xx_hal_adc_ex.h:169
HAL_ADCEx_MultiModeConfigChannel
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.
Definition: stm32l4xx_hal_adc_ex.c:2070
ADC_InjectionConfTypeDef::QueueInjectedContext
FunctionalState QueueInjectedContext
Definition: stm32l4xx_hal_adc_ex.h:142
HAL_ADCEx_LevelOutOfWindow3Callback
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
Analog watchdog 3 callback in non-blocking mode.
Definition: stm32l4xx_hal_adc_ex.c:1219
ADC_MultiModeTypeDef
Structure definition of ADC multimode.
Definition: stm32l4xx_hal_adc_ex.h:180
ADC_InjectionConfTypeDef::InjecOversamplingMode
FunctionalState InjecOversamplingMode
Definition: stm32l4xx_hal_adc_ex.h:165
HAL_ADCEx_DisableVoltageRegulator
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
Disable ADC voltage regulator.
Definition: stm32l4xx_hal_adc_ex.c:2261
HAL_ADCEx_RegularStop_IT
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
Stop ADC conversion of ADC groups regular and injected, disable interrution of end-of-conversion, disable ADC peripheral if no conversion is on going on injected group.
Definition: stm32l4xx_hal_adc_ex.c:1310
HAL_ADCEx_RegularStop
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode)...
Definition: stm32l4xx_hal_adc_ex.c:1252
HAL_ADCEx_MultiModeGetValue
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
Return the last ADC Master and Slave regular conversions results when in multimode configuration...
Definition: stm32l4xx_hal_adc_ex.c:1088
HAL_ADCEx_MultiModeStop_DMA
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
Definition: stm32l4xx_hal_adc_ex.c:975
ADC_InjectionConfTypeDef
Structure definition of ADC group injected and ADC channel affected to ADC group injected.
Definition: stm32l4xx_hal_adc_ex.h:72
ADC_InjectionConfTypeDef::ExternalTrigInjecConv
uint32_t ExternalTrigInjecConv
Definition: stm32l4xx_hal_adc_ex.h:153