STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_flash.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L4xx_HAL_FLASH_H
22 #define __STM32L4xx_HAL_FLASH_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t TypeErase;
51  uint32_t Banks;
54  uint32_t Page;
57  uint32_t NbPages;
59 } FLASH_EraseInitTypeDef;
60 
64 typedef struct
65 {
66  uint32_t OptionType;
68  uint32_t WRPArea;
71  uint32_t WRPStartOffset;
74  uint32_t WRPEndOffset;
76  uint32_t RDPLevel;
78  uint32_t USERType;
80  uint32_t USERConfig;
88  uint32_t PCROPConfig;
91  uint32_t PCROPStartAddr;
94  uint32_t PCROPEndAddr;
96 } FLASH_OBProgramInitTypeDef;
97 
101 typedef enum
102 {
103  FLASH_PROC_NONE = 0,
104  FLASH_PROC_PAGE_ERASE,
105  FLASH_PROC_MASS_ERASE,
106  FLASH_PROC_PROGRAM,
107  FLASH_PROC_PROGRAM_LAST
108 } FLASH_ProcedureTypeDef;
109 
113 typedef enum
114 {
115  FLASH_CACHE_DISABLED = 0,
116  FLASH_CACHE_ICACHE_ENABLED,
117  FLASH_CACHE_DCACHE_ENABLED,
118  FLASH_CACHE_ICACHE_DCACHE_ENABLED
119 } FLASH_CacheTypeDef;
120 
124 typedef struct
125 {
126  HAL_LockTypeDef Lock; /* FLASH locking object */
127  __IO uint32_t ErrorCode; /* FLASH error code */
128  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
129  __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
130  __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
131  __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
132  __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
133  __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
134 }FLASH_ProcessTypeDef;
135 
140 /* Exported constants --------------------------------------------------------*/
148 #define HAL_FLASH_ERROR_NONE 0x00000000U
149 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
150 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
151 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
152 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
153 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
154 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
155 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
156 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
157 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
158 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
159 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
160 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
161  defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
162  defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \
163  defined (STM32L4S7xx) || defined (STM32L4S9xx)
164 #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY
165 #endif
166 
173 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00)
174 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)
182 #define FLASH_BANK_1 ((uint32_t)0x01)
183 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
184  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
185  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
186 #define FLASH_BANK_2 ((uint32_t)0x02)
187 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2))
188 #else
189 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1))
190 #endif
191 
199 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00)
200 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01)
202 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)
211 #define OPTIONBYTE_WRP ((uint32_t)0x01)
212 #define OPTIONBYTE_RDP ((uint32_t)0x02)
213 #define OPTIONBYTE_USER ((uint32_t)0x04)
214 #define OPTIONBYTE_PCROP ((uint32_t)0x08)
222 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00)
223 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01)
224 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
225  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
226  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
227 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02)
228 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04)
229 #endif
230 
237 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
238 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
239 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC)
248 #define OB_USER_BOR_LEV ((uint32_t)0x0001)
249 #define OB_USER_nRST_STOP ((uint32_t)0x0002)
250 #define OB_USER_nRST_STDBY ((uint32_t)0x0004)
251 #define OB_USER_IWDG_SW ((uint32_t)0x0008)
252 #define OB_USER_IWDG_STOP ((uint32_t)0x0010)
253 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020)
254 #define OB_USER_WWDG_SW ((uint32_t)0x0040)
255 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
256  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
257  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
258 #define OB_USER_BFB2 ((uint32_t)0x0080)
259 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
260 #define OB_USER_DUALBANK ((uint32_t)0x0100)
261 #else
262 #define OB_USER_DUALBANK ((uint32_t)0x0100)
263 #endif
264 #endif
265 #define OB_USER_nBOOT1 ((uint32_t)0x0200)
266 #define OB_USER_SRAM2_PE ((uint32_t)0x0400)
267 #define OB_USER_SRAM2_RST ((uint32_t)0x0800)
268 #define OB_USER_nRST_SHDW ((uint32_t)0x1000)
269 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \
270  defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
271  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
272  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
273 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000)
274 #define OB_USER_nBOOT0 ((uint32_t)0x4000)
275 #endif
276 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
277 #define OB_USER_DBANK ((uint32_t)0x8000)
278 #endif
279 
286 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0)
287 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1)
288 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2)
289 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3)
290 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4)
298 #define OB_STOP_RST ((uint32_t)0x0000)
299 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP)
307 #define OB_STANDBY_RST ((uint32_t)0x0000)
308 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY)
316 #define OB_SHUTDOWN_RST ((uint32_t)0x0000)
317 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW)
325 #define OB_IWDG_HW ((uint32_t)0x00000)
326 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW)
334 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000)
335 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP)
343 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000)
344 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY)
352 #define OB_WWDG_HW ((uint32_t)0x00000)
353 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW)
358 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
359  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
360  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
361 
364 #define OB_BFB2_DISABLE ((uint32_t)0x000000)
365 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2)
369 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
370 
373 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000)
374 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M)
378 #else
379 
382 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000)
383 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK)
387 #endif
388 #endif
389 
390 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
391 
394 #define OB_DBANK_128_BITS ((uint32_t)0x000000)
395 #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK)
396 #endif
397 
403 #define OB_BOOT1_SRAM ((uint32_t)0x000000)
404 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1)
412 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000)
413 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE)
421 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000)
422 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST)
427 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \
428  defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
429  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
430  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
431 
434 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000)
435 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0)
443 #define OB_BOOT0_RESET ((uint32_t)0x0000000)
444 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0)
448 #endif
449 
453 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000)
455 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP)
464 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
465 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
466 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
467 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
468 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
469 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
470 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
471 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
472 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
473 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
474 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
475 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
476 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
477 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
478 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
479 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
480 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
481 #endif
482 
489 #define FLASH_KEY1 0x45670123U
490 #define FLASH_KEY2 0xCDEF89ABU
493 #define FLASH_PDKEY1 0x04152637U
494 #define FLASH_PDKEY2 0xFAFBFCFDU
497 #define FLASH_OPTKEY1 0x08192A3BU
498 #define FLASH_OPTKEY2 0x4C5D6E7FU
507 #define FLASH_FLAG_EOP FLASH_SR_EOP
508 #define FLASH_FLAG_OPERR FLASH_SR_OPERR
509 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR
510 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR
511 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR
512 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR
513 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR
514 #define FLASH_FLAG_MISERR FLASH_SR_MISERR
515 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR
516 #define FLASH_FLAG_RDERR FLASH_SR_RDERR
517 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR
518 #define FLASH_FLAG_BSY FLASH_SR_BSY
519 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
520  defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
521  defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || \
522  defined (STM32L4S7xx) || defined (STM32L4S9xx)
523 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY
524 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
525  FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
526  FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
527  FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY)
528 #else
529 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
530  FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
531  FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
532  FLASH_FLAG_OPTVERR)
533 #endif
534 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC
535 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD
537 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
538  FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
539  FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
540  FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
541 
549 #define FLASH_IT_EOP FLASH_CR_EOPIE
550 #define FLASH_IT_OPERR FLASH_CR_ERRIE
551 #define FLASH_IT_RDERR FLASH_CR_RDERRIE
552 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24)
557 /* Exported macros -----------------------------------------------------------*/
558 
574 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
575 
586 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
587 
592 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
593 
598 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
599 
604 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
605 
610 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
611 
616 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
617 
622 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
623 
629 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
630  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
631  } while (0)
632 
638 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
639  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
640  } while (0)
641 
647 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
648  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
649  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
650  } while (0)
651 
657 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
658  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
659  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
660  } while (0)
661 
666 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
667 
672 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
673 
693 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
694  if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
695  } while(0)
696 
707 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
708  if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
709  } while(0)
710 
732 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
733  (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
734  (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
735 
756 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
757  if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
758  } while(0)
759 
763 /* Include FLASH HAL Extended module */
764 #include "stm32l4xx_hal_flash_ex.h"
765 #include "stm32l4xx_hal_flash_ramfunc.h"
766 
767 /* Exported functions --------------------------------------------------------*/
772 /* Program operation functions ***********************************************/
776 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
777 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
778 /* FLASH IRQ handler method */
779 void HAL_FLASH_IRQHandler(void);
780 /* Callbacks in non blocking modes */
781 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
782 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
787 /* Peripheral Control functions **********************************************/
791 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
792 HAL_StatusTypeDef HAL_FLASH_Lock(void);
793 /* Option bytes control */
794 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
795 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
796 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
801 /* Peripheral State functions ************************************************/
805 uint32_t HAL_FLASH_GetError(void);
814 /* Private variables ---------------------------------------------------------*/
818 extern FLASH_ProcessTypeDef pFlash;
823 /* Private function ----------------------------------------------------------*/
827 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
832 /* Private constants --------------------------------------------------------*/
836 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
837 
838 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
839 #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \
840  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
841 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
842 #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x200U << 10U) : \
843  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
844 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
845 #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
846  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
847 #elif defined (STM32L412xx) || defined (STM32L422xx)
848 #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) : \
849  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
850 #else
851 #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \
852  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
853 #endif
854 
855 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
856  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
857  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
858 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U)
859 #else
860 #define FLASH_BANK_SIZE (FLASH_SIZE)
861 #endif
862 
863 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
864 #define FLASH_PAGE_SIZE ((uint32_t)0x1000)
865 #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000)
866 #else
867 #define FLASH_PAGE_SIZE ((uint32_t)0x800)
868 #endif
869 
870 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
871 
875 /* Private macros ------------------------------------------------------------*/
880 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
881  ((VALUE) == FLASH_TYPEERASE_MASSERASE))
882 
883 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
884  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
885  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
886 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
887  ((BANK) == FLASH_BANK_2) || \
888  ((BANK) == FLASH_BANK_BOTH))
889 
890 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
891  ((BANK) == FLASH_BANK_2))
892 #else
893 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
894 
895 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
896 #endif
897 
898 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
899  ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
900  ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
901 
902 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
903 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU)))
904 #else
905 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \
906  ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \
907  ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \
908  ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \
909  ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)))))))
910 #endif
911 
912 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
913 
914 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))
915 
916 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
917 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U)
918 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
919 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \
920  ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \
921  ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \
922  ((PAGE) < 256U)))))
923 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
924 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \
925  ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \
926  ((PAGE) < 256U))))
927 #else
928 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \
929  ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \
930  ((PAGE) < 128U))))
931 #endif
932 
933 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
934 
935 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
936  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
937  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
938 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
939  ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
940 #else
941 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
942 #endif
943 
944 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
945  ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
946  ((LEVEL) == OB_RDP_LEVEL_2)*/)
947 
948 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
949 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U))
950 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
951 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U))
952 #else
953 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U))
954 #endif
955 
956 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
957  ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
958  ((LEVEL) == OB_BOR_LEVEL_4))
959 
960 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
961 
962 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
963 
964 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
965 
966 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
967 
968 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
969 
970 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
971 
972 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
973 
974 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
975  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
976  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
977 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
978 
979 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
980 #endif
981 
982 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
983 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
984 #endif
985 
986 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
987 
988 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
989 
990 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
991 
992 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \
993  defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
994  defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || \
995  defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
996 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
997 
998 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
999 #endif
1000 
1001 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
1002 
1003 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1004 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
1005  ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
1006  ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
1007  ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
1008  ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
1009  ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
1010  ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
1011  ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
1012 #else
1013 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
1014  ((LATENCY) == FLASH_LATENCY_1) || \
1015  ((LATENCY) == FLASH_LATENCY_2) || \
1016  ((LATENCY) == FLASH_LATENCY_3) || \
1017  ((LATENCY) == FLASH_LATENCY_4))
1018 #endif
1019 
1035 #ifdef __cplusplus
1036 }
1037 #endif
1038 
1039 #endif /* __STM32L4xx_HAL_FLASH_H */
1040 
1041 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_FLASH_Program_IT
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address with interrupt enabled...
Definition: stm32l4xx_hal_flash.c:253
FLASH_OBProgramInitTypeDef::RDPLevel
uint32_t RDPLevel
Definition: stm32l4xx_hal_flash.h:76
HAL_FLASH_OperationErrorCallback
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
FLASH operation error interrupt callback.
Definition: stm32l4xx_hal_flash.c:474
FLASH_ProcessTypeDef::Address
__IO uint32_t Address
Definition: stm32l4xx_hal_flash.h:129
FLASH_ProcessTypeDef::ProcedureOnGoing
__IO FLASH_ProcedureTypeDef ProcedureOnGoing
Definition: stm32l4xx_hal_flash.h:128
HAL_FLASH_EndOfOperationCallback
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
FLASH end of operation interrupt callback.
Definition: stm32l4xx_hal_flash.c:456
FLASH_ProcessTypeDef::NbPagesToErase
__IO uint32_t NbPagesToErase
Definition: stm32l4xx_hal_flash.h:132
HAL_FLASH_OB_Lock
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
Lock the FLASH Option Bytes Registers access.
Definition: stm32l4xx_hal_flash.c:563
FLASH_CacheTypeDef
FLASH_CacheTypeDef
FLASH Cache structure definition.
Definition: stm32l4xx_hal_flash.h:113
FLASH_OBProgramInitTypeDef::USERType
uint32_t USERType
Definition: stm32l4xx_hal_flash.h:78
FLASH_PROC_NONE
Definition: stm32l4xx_hal_flash.h:103
FLASH_ProcessTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32l4xx_hal_flash.h:126
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_FLASH_Lock
HAL_StatusTypeDef HAL_FLASH_Lock(void)
Lock the FLASH control register access.
Definition: stm32l4xx_hal_flash.c:531
FLASH_PROC_MASS_ERASE
Definition: stm32l4xx_hal_flash.h:105
HAL_FLASH_OB_Launch
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
Launch the option byte loading.
Definition: stm32l4xx_hal_flash.c:575
FLASH_ProcedureTypeDef
FLASH_ProcedureTypeDef
FLASH Procedure structure definition.
Definition: stm32l4xx_hal_flash.h:101
HAL_FLASH_Unlock
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
Unlock the FLASH control register access.
Definition: stm32l4xx_hal_flash.c:507
FLASH_OBProgramInitTypeDef::PCROPEndAddr
uint32_t PCROPEndAddr
Definition: stm32l4xx_hal_flash.h:94
FLASH_CACHE_ICACHE_DCACHE_ENABLED
Definition: stm32l4xx_hal_flash.h:118
FLASH_PROC_PAGE_ERASE
Definition: stm32l4xx_hal_flash.h:104
HAL_FLASH_Program
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program double word or fast program of a row at a specified address.
Definition: stm32l4xx_hal_flash.c:171
FLASH_PROC_PROGRAM
Definition: stm32l4xx_hal_flash.h:106
FLASH_CACHE_DISABLED
Definition: stm32l4xx_hal_flash.h:115
FLASH_OBProgramInitTypeDef::WRPStartOffset
uint32_t WRPStartOffset
Definition: stm32l4xx_hal_flash.h:71
FLASH_ProcessTypeDef::Bank
__IO uint32_t Bank
Definition: stm32l4xx_hal_flash.h:130
HAL_FLASH_OB_Unlock
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
Unlock the FLASH Option Bytes Registers access.
Definition: stm32l4xx_hal_flash.c:543
FLASH_OBProgramInitTypeDef::PCROPStartAddr
uint32_t PCROPStartAddr
Definition: stm32l4xx_hal_flash.h:91
FLASH_CACHE_DCACHE_ENABLED
Definition: stm32l4xx_hal_flash.h:117
FLASH_WaitForLastOperation
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
Wait for a FLASH operation to complete.
Definition: stm32l4xx_hal_flash.c:649
FLASH_OBProgramInitTypeDef::USERConfig
uint32_t USERConfig
Definition: stm32l4xx_hal_flash.h:80
stm32l4xx_hal_flash_ramfunc.h
Header file of FLASH RAMFUNC driver.
FLASH_OBProgramInitTypeDef::WRPEndOffset
uint32_t WRPEndOffset
Definition: stm32l4xx_hal_flash.h:74
FLASH_OBProgramInitTypeDef::PCROPConfig
uint32_t PCROPConfig
Definition: stm32l4xx_hal_flash.h:88
FLASH_OBProgramInitTypeDef::WRPArea
uint32_t WRPArea
Definition: stm32l4xx_hal_flash.h:68
FLASH_ProcessTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32l4xx_hal_flash.h:127
FLASH_OBProgramInitTypeDef::OptionType
uint32_t OptionType
Definition: stm32l4xx_hal_flash.h:66
HAL_FLASH_IRQHandler
void HAL_FLASH_IRQHandler(void)
Handle FLASH interrupt request.
Definition: stm32l4xx_hal_flash.c:313
FLASH_ProcessTypeDef
FLASH handle Structure definition.
Definition: stm32l4xx_hal_flash.h:124
pFlash
FLASH_ProcessTypeDef pFlash
Variable used for Program/Erase sectors under interruption.
Definition: stm32l4xx_hal_flash.c:118
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32l4xx_hal_def.h:50
FLASH_ProcessTypeDef::Page
__IO uint32_t Page
Definition: stm32l4xx_hal_flash.h:131
FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition.
Definition: stm32l4xx_hal_flash.h:64
HAL_FLASH_GetError
uint32_t HAL_FLASH_GetError(void)
Get the specific FLASH error flag.
Definition: stm32l4xx_hal_flash.c:625
FLASH_PROC_PROGRAM_LAST
Definition: stm32l4xx_hal_flash.h:107
FLASH_ProcessTypeDef::CacheToReactivate
__IO FLASH_CacheTypeDef CacheToReactivate
Definition: stm32l4xx_hal_flash.h:133
FLASH_CACHE_ICACHE_ENABLED
Definition: stm32l4xx_hal_flash.h:116
stm32l4xx_hal_flash_ex.h
Header file of FLASH HAL Extended module.