STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_rcc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L4xx_HAL_RCC_H
22 #define __STM32L4xx_HAL_RCC_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t PLLState;
52  uint32_t PLLSource;
55  uint32_t PLLM;
59  uint32_t PLLN;
62 #if defined(RCC_PLLP_SUPPORT)
63  uint32_t PLLP;
65 #endif /* RCC_PLLP_SUPPORT */
66 
67  uint32_t PLLQ;
70  uint32_t PLLR;
75 }RCC_PLLInitTypeDef;
76 
80 typedef struct
81 {
82  uint32_t OscillatorType;
85  uint32_t HSEState;
88  uint32_t LSEState;
91  uint32_t HSIState;
94  uint32_t HSICalibrationValue;
98  uint32_t LSIState;
100 #if defined(RCC_CSR_LSIPREDIV)
101 
102  uint32_t LSIDiv;
104 #endif /* RCC_CSR_LSIPREDIV */
105 
106  uint32_t MSIState;
109  uint32_t MSICalibrationValue;
112  uint32_t MSIClockRange;
115  uint32_t HSI48State;
118  RCC_PLLInitTypeDef PLL;
120 }RCC_OscInitTypeDef;
121 
125 typedef struct
126 {
127  uint32_t ClockType;
130  uint32_t SYSCLKSource;
133  uint32_t AHBCLKDivider;
136  uint32_t APB1CLKDivider;
139  uint32_t APB2CLKDivider;
142 }RCC_ClkInitTypeDef;
143 
148 /* Exported constants --------------------------------------------------------*/
156 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
157 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
158 
165 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
166 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
167 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
168 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
169 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
170 #define RCC_OSCILLATORTYPE_MSI 0x00000010U
171 #if defined(RCC_HSI48_SUPPORT)
172 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U
173 #endif /* RCC_HSI48_SUPPORT */
174 
181 #define RCC_HSE_OFF 0x00000000U
182 #define RCC_HSE_ON RCC_CR_HSEON
183 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON)
191 #define RCC_LSE_OFF 0x00000000U
192 #define RCC_LSE_ON RCC_BDCR_LSEON
193 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)
194 #if defined(RCC_BDCR_LSESYSDIS)
195 #define RCC_LSE_ON_RTC_ONLY (RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON)
196 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSDIS | RCC_BDCR_LSEON)
197 #endif /* RCC_BDCR_LSESYSDIS */
198 
205 #define RCC_HSI_OFF 0x00000000U
206 #define RCC_HSI_ON RCC_CR_HSION
208 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
209  defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
210 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
211 #else
212 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
213 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
214  /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
222 #define RCC_LSI_OFF 0x00000000U
223 #define RCC_LSI_ON RCC_CSR_LSION
227 #if defined(RCC_CSR_LSIPREDIV)
228 
232 #define RCC_LSI_DIV1 0x00000000U
233 #define RCC_LSI_DIV128 RCC_CSR_LSIPREDIV
237 #endif /* RCC_CSR_LSIPREDIV */
238 
242 #define RCC_MSI_OFF 0x00000000U
243 #define RCC_MSI_ON RCC_CR_MSION
245 #define RCC_MSICALIBRATION_DEFAULT 0U
250 #if defined(RCC_HSI48_SUPPORT)
251 
254 #define RCC_HSI48_OFF 0x00000000U
255 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON
259 #else
260 
263 #define RCC_HSI48_OFF 0x00000000U
267 #endif /* RCC_HSI48_SUPPORT */
268 
272 #define RCC_PLL_NONE 0x00000000U
273 #define RCC_PLL_OFF 0x00000001U
274 #define RCC_PLL_ON 0x00000002U
279 #if defined(RCC_PLLP_SUPPORT)
280 
283 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
284 #define RCC_PLLP_DIV2 0x00000002U
285 #define RCC_PLLP_DIV3 0x00000003U
286 #define RCC_PLLP_DIV4 0x00000004U
287 #define RCC_PLLP_DIV5 0x00000005U
288 #define RCC_PLLP_DIV6 0x00000006U
289 #define RCC_PLLP_DIV7 0x00000007U
290 #define RCC_PLLP_DIV8 0x00000008U
291 #define RCC_PLLP_DIV9 0x00000009U
292 #define RCC_PLLP_DIV10 0x0000000AU
293 #define RCC_PLLP_DIV11 0x0000000BU
294 #define RCC_PLLP_DIV12 0x0000000CU
295 #define RCC_PLLP_DIV13 0x0000000DU
296 #define RCC_PLLP_DIV14 0x0000000EU
297 #define RCC_PLLP_DIV15 0x0000000FU
298 #define RCC_PLLP_DIV16 0x00000010U
299 #define RCC_PLLP_DIV17 0x00000011U
300 #define RCC_PLLP_DIV18 0x00000012U
301 #define RCC_PLLP_DIV19 0x00000013U
302 #define RCC_PLLP_DIV20 0x00000014U
303 #define RCC_PLLP_DIV21 0x00000015U
304 #define RCC_PLLP_DIV22 0x00000016U
305 #define RCC_PLLP_DIV23 0x00000017U
306 #define RCC_PLLP_DIV24 0x00000018U
307 #define RCC_PLLP_DIV25 0x00000019U
308 #define RCC_PLLP_DIV26 0x0000001AU
309 #define RCC_PLLP_DIV27 0x0000001BU
310 #define RCC_PLLP_DIV28 0x0000001CU
311 #define RCC_PLLP_DIV29 0x0000001DU
312 #define RCC_PLLP_DIV30 0x0000001EU
313 #define RCC_PLLP_DIV31 0x0000001FU
314 #else
315 #define RCC_PLLP_DIV7 0x00000007U
316 #define RCC_PLLP_DIV17 0x00000011U
317 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
318 
321 #endif /* RCC_PLLP_SUPPORT */
322 
326 #define RCC_PLLQ_DIV2 0x00000002U
327 #define RCC_PLLQ_DIV4 0x00000004U
328 #define RCC_PLLQ_DIV6 0x00000006U
329 #define RCC_PLLQ_DIV8 0x00000008U
337 #define RCC_PLLR_DIV2 0x00000002U
338 #define RCC_PLLR_DIV4 0x00000004U
339 #define RCC_PLLR_DIV6 0x00000006U
340 #define RCC_PLLR_DIV8 0x00000008U
348 #define RCC_PLLSOURCE_NONE 0x00000000U
349 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
350 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
351 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
359 #if defined(RCC_PLLSAI2_SUPPORT)
360 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN
361 #elif defined(RCC_PLLSAI1_SUPPORT)
362 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN
363 #endif /* RCC_PLLSAI2_SUPPORT */
364 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN
365 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN
369 #if defined(RCC_PLLSAI1_SUPPORT)
370 
374 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN
375 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN
376 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN
380 #endif /* RCC_PLLSAI1_SUPPORT */
381 
382 #if defined(RCC_PLLSAI2_SUPPORT)
383 
387 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN
388 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
389 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN
390 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
391 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
392 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN
393 #else
394 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN
395 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
396 
400 #endif /* RCC_PLLSAI2_SUPPORT */
401 
405 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
406 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
407 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
408 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
409 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
410 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
411 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
412 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
413 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
414 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
415 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
416 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11
424 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
425 #define RCC_CLOCKTYPE_HCLK 0x00000002U
426 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
427 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
435 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
436 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
437 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
438 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
446 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
447 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
448 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
449 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
457 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
458 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
459 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
460 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
461 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
462 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
463 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
464 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
465 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
473 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
474 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
475 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
476 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
477 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
485 #define RCC_RTCCLKSOURCE_NONE 0x00000000U
486 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0
487 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1
488 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
496 #define RCC_MCO1 0x00000000U
497 #define RCC_MCO RCC_MCO1
505 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U
506 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
507 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
508 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
509 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
510 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
511 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
512 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
513 #if defined(RCC_HSI48_SUPPORT)
514 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3
515 #endif /* RCC_HSI48_SUPPORT */
516 
523 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1
524 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2
525 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4
526 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8
527 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16
535 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
536 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF
537 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
538 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
539 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF
540 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
541 #if defined(RCC_PLLSAI1_SUPPORT)
542 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF
543 #endif /* RCC_PLLSAI1_SUPPORT */
544 #if defined(RCC_PLLSAI2_SUPPORT)
545 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF
546 #endif /* RCC_PLLSAI2_SUPPORT */
547 #define RCC_IT_CSS RCC_CIFR_CSSF
548 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF
549 #if defined(RCC_HSI48_SUPPORT)
550 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
551 #endif /* RCC_HSI48_SUPPORT */
552 
566 /* Flags in the CR register */
567 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)
568 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
569 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
570 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
571 #if defined(RCC_PLLSAI1_SUPPORT)
572 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)
573 #endif /* RCC_PLLSAI1_SUPPORT */
574 #if defined(RCC_PLLSAI2_SUPPORT)
575 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)
576 #endif /* RCC_PLLSAI2_SUPPORT */
577 
578 /* Flags in the BDCR register */
579 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
580 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
582 /* Flags in the CSR register */
583 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)
584 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)
585 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
586 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
587 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)
588 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
589 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
590 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
591 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)
593 #if defined(RCC_HSI48_SUPPORT)
594 /* Flags in the CRRCR register */
595 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)
596 #endif /* RCC_HSI48_SUPPORT */
597 
604 #define RCC_LSEDRIVE_LOW 0x00000000U
605 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
606 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
607 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
615 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U
616 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
625 /* Exported macros -----------------------------------------------------------*/
626 
639 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
640  __IO uint32_t tmpreg; \
641  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
642  /* Delay after an RCC peripheral clock enabling */ \
643  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
644  UNUSED(tmpreg); \
645  } while(0)
646 
647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
648  __IO uint32_t tmpreg; \
649  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
650  /* Delay after an RCC peripheral clock enabling */ \
651  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
652  UNUSED(tmpreg); \
653  } while(0)
654 
655 #if defined(DMAMUX1)
656 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
657  __IO uint32_t tmpreg; \
658  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
659  /* Delay after an RCC peripheral clock enabling */ \
660  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
661  UNUSED(tmpreg); \
662  } while(0)
663 #endif /* DMAMUX1 */
664 
665 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
666  __IO uint32_t tmpreg; \
667  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
668  /* Delay after an RCC peripheral clock enabling */ \
669  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
670  UNUSED(tmpreg); \
671  } while(0)
672 
673 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
674  __IO uint32_t tmpreg; \
675  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
676  /* Delay after an RCC peripheral clock enabling */ \
677  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
678  UNUSED(tmpreg); \
679  } while(0)
680 
681 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
682  __IO uint32_t tmpreg; \
683  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
684  /* Delay after an RCC peripheral clock enabling */ \
685  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
686  UNUSED(tmpreg); \
687  } while(0)
688 
689 #if defined(DMA2D)
690 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
691  __IO uint32_t tmpreg; \
692  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
693  /* Delay after an RCC peripheral clock enabling */ \
694  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
695  UNUSED(tmpreg); \
696  } while(0)
697 #endif /* DMA2D */
698 
699 #if defined(GFXMMU)
700 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
701  __IO uint32_t tmpreg; \
702  SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
703  /* Delay after an RCC peripheral clock enabling */ \
704  tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
705  UNUSED(tmpreg); \
706  } while(0)
707 #endif /* GFXMMU */
708 
709 
710 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
711 
712 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
713 
714 #if defined(DMAMUX1)
715 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
716 #endif /* DMAMUX1 */
717 
718 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
719 
720 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
721 
722 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
723 
724 #if defined(DMA2D)
725 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
726 #endif /* DMA2D */
727 
728 #if defined(GFXMMU)
729 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN)
730 #endif /* GFXMMU */
731 
744 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
745  __IO uint32_t tmpreg; \
746  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
747  /* Delay after an RCC peripheral clock enabling */ \
748  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
749  UNUSED(tmpreg); \
750  } while(0)
751 
752 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
753  __IO uint32_t tmpreg; \
754  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
755  /* Delay after an RCC peripheral clock enabling */ \
756  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
757  UNUSED(tmpreg); \
758  } while(0)
759 
760 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
761  __IO uint32_t tmpreg; \
762  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
763  /* Delay after an RCC peripheral clock enabling */ \
764  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
765  UNUSED(tmpreg); \
766  } while(0)
767 
768 #if defined(GPIOD)
769 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
770  __IO uint32_t tmpreg; \
771  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
772  /* Delay after an RCC peripheral clock enabling */ \
773  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
774  UNUSED(tmpreg); \
775  } while(0)
776 #endif /* GPIOD */
777 
778 #if defined(GPIOE)
779 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
780  __IO uint32_t tmpreg; \
781  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
782  /* Delay after an RCC peripheral clock enabling */ \
783  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
784  UNUSED(tmpreg); \
785  } while(0)
786 #endif /* GPIOE */
787 
788 #if defined(GPIOF)
789 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
790  __IO uint32_t tmpreg; \
791  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
792  /* Delay after an RCC peripheral clock enabling */ \
793  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
794  UNUSED(tmpreg); \
795  } while(0)
796 #endif /* GPIOF */
797 
798 #if defined(GPIOG)
799 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
800  __IO uint32_t tmpreg; \
801  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
802  /* Delay after an RCC peripheral clock enabling */ \
803  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
804  UNUSED(tmpreg); \
805  } while(0)
806 #endif /* GPIOG */
807 
808 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
809  __IO uint32_t tmpreg; \
810  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
811  /* Delay after an RCC peripheral clock enabling */ \
812  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
813  UNUSED(tmpreg); \
814  } while(0)
815 
816 #if defined(GPIOI)
817 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
818  __IO uint32_t tmpreg; \
819  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
820  /* Delay after an RCC peripheral clock enabling */ \
821  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
822  UNUSED(tmpreg); \
823  } while(0)
824 #endif /* GPIOI */
825 
826 #if defined(USB_OTG_FS)
827 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
828  __IO uint32_t tmpreg; \
829  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
830  /* Delay after an RCC peripheral clock enabling */ \
831  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
832  UNUSED(tmpreg); \
833  } while(0)
834 #endif /* USB_OTG_FS */
835 
836 #define __HAL_RCC_ADC_CLK_ENABLE() do { \
837  __IO uint32_t tmpreg; \
838  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
839  /* Delay after an RCC peripheral clock enabling */ \
840  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
841  UNUSED(tmpreg); \
842  } while(0)
843 
844 #if defined(DCMI)
845 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
846  __IO uint32_t tmpreg; \
847  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
848  /* Delay after an RCC peripheral clock enabling */ \
849  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
850  UNUSED(tmpreg); \
851  } while(0)
852 #endif /* DCMI */
853 
854 #if defined(AES)
855 #define __HAL_RCC_AES_CLK_ENABLE() do { \
856  __IO uint32_t tmpreg; \
857  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
858  /* Delay after an RCC peripheral clock enabling */ \
859  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
860  UNUSED(tmpreg); \
861  } while(0)
862 #endif /* AES */
863 
864 #if defined(HASH)
865 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
866  __IO uint32_t tmpreg; \
867  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
868  /* Delay after an RCC peripheral clock enabling */ \
869  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
870  UNUSED(tmpreg); \
871  } while(0)
872 #endif /* HASH */
873 
874 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
875  __IO uint32_t tmpreg; \
876  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
877  /* Delay after an RCC peripheral clock enabling */ \
878  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
879  UNUSED(tmpreg); \
880  } while(0)
881 
882 #if defined(OCTOSPIM)
883 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \
884  __IO uint32_t tmpreg; \
885  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
886  /* Delay after an RCC peripheral clock enabling */ \
887  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \
888  UNUSED(tmpreg); \
889  } while(0)
890 #endif /* OCTOSPIM */
891 
892 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
893 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
894  __IO uint32_t tmpreg; \
895  SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
896  /* Delay after an RCC peripheral clock enabling */ \
897  tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
898  UNUSED(tmpreg); \
899  } while(0)
900 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
901 
902 
903 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
904 
905 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
906 
907 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
908 
909 #if defined(GPIOD)
910 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
911 #endif /* GPIOD */
912 
913 #if defined(GPIOE)
914 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
915 #endif /* GPIOE */
916 
917 #if defined(GPIOF)
918 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
919 #endif /* GPIOF */
920 
921 #if defined(GPIOG)
922 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
923 #endif /* GPIOG */
924 
925 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
926 
927 #if defined(GPIOI)
928 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
929 #endif /* GPIOI */
930 
931 #if defined(USB_OTG_FS)
932 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
933 #endif /* USB_OTG_FS */
934 
935 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
936 
937 #if defined(DCMI)
938 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
939 #endif /* DCMI */
940 
941 #if defined(AES)
942 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
943 #endif /* AES */
944 
945 #if defined(HASH)
946 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
947 #endif /* HASH */
948 
949 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
950 
951 #if defined(OCTOSPIM)
952 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN)
953 #endif /* OCTOSPIM */
954 
955 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
956 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN)
957 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
958 
971 #if defined(FMC_BANK1)
972 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
973  __IO uint32_t tmpreg; \
974  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
975  /* Delay after an RCC peripheral clock enabling */ \
976  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
977  UNUSED(tmpreg); \
978  } while(0)
979 #endif /* FMC_BANK1 */
980 
981 #if defined(QUADSPI)
982 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
983  __IO uint32_t tmpreg; \
984  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
985  /* Delay after an RCC peripheral clock enabling */ \
986  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
987  UNUSED(tmpreg); \
988  } while(0)
989 #endif /* QUADSPI */
990 
991 #if defined(OCTOSPI1)
992 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
993  __IO uint32_t tmpreg; \
994  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
995  /* Delay after an RCC peripheral clock enabling */ \
996  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
997  UNUSED(tmpreg); \
998  } while(0)
999 #endif /* OCTOSPI1 */
1000 
1001 #if defined(OCTOSPI2)
1002 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
1003  __IO uint32_t tmpreg; \
1004  SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
1005  /* Delay after an RCC peripheral clock enabling */ \
1006  tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \
1007  UNUSED(tmpreg); \
1008  } while(0)
1009 #endif /* OCTOSPI2 */
1010 
1011 #if defined(FMC_BANK1)
1012 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
1013 #endif /* FMC_BANK1 */
1014 
1015 #if defined(QUADSPI)
1016 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
1017 #endif /* QUADSPI */
1018 
1019 #if defined(OCTOSPI1)
1020 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN)
1021 #endif /* OCTOSPI1 */
1022 
1023 #if defined(OCTOSPI2)
1024 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN)
1025 #endif /* OCTOSPI2 */
1026 
1039 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1040  __IO uint32_t tmpreg; \
1041  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
1042  /* Delay after an RCC peripheral clock enabling */ \
1043  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
1044  UNUSED(tmpreg); \
1045  } while(0)
1046 
1047 #if defined(TIM3)
1048 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1049  __IO uint32_t tmpreg; \
1050  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
1051  /* Delay after an RCC peripheral clock enabling */ \
1052  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
1053  UNUSED(tmpreg); \
1054  } while(0)
1055 #endif /* TIM3 */
1056 
1057 #if defined(TIM4)
1058 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1059  __IO uint32_t tmpreg; \
1060  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
1061  /* Delay after an RCC peripheral clock enabling */ \
1062  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
1063  UNUSED(tmpreg); \
1064  } while(0)
1065 #endif /* TIM4 */
1066 
1067 #if defined(TIM5)
1068 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
1069  __IO uint32_t tmpreg; \
1070  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1071  /* Delay after an RCC peripheral clock enabling */ \
1072  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
1073  UNUSED(tmpreg); \
1074  } while(0)
1075 #endif /* TIM5 */
1076 
1077 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1078  __IO uint32_t tmpreg; \
1079  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
1080  /* Delay after an RCC peripheral clock enabling */ \
1081  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
1082  UNUSED(tmpreg); \
1083  } while(0)
1084 
1085 #if defined(TIM7)
1086 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1087  __IO uint32_t tmpreg; \
1088  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
1089  /* Delay after an RCC peripheral clock enabling */ \
1090  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
1091  UNUSED(tmpreg); \
1092  } while(0)
1093 #endif /* TIM7 */
1094 
1095 #if defined(LCD)
1096 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
1097  __IO uint32_t tmpreg; \
1098  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
1099  /* Delay after an RCC peripheral clock enabling */ \
1100  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
1101  UNUSED(tmpreg); \
1102  } while(0)
1103 #endif /* LCD */
1104 
1105 #if defined(RCC_APB1ENR1_RTCAPBEN)
1106 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
1107  __IO uint32_t tmpreg; \
1108  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
1109  /* Delay after an RCC peripheral clock enabling */ \
1110  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
1111  UNUSED(tmpreg); \
1112  } while(0)
1113 #endif /* RCC_APB1ENR1_RTCAPBEN */
1114 
1115 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
1116  __IO uint32_t tmpreg; \
1117  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
1118  /* Delay after an RCC peripheral clock enabling */ \
1119  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
1120  UNUSED(tmpreg); \
1121  } while(0)
1122 
1123 #if defined(SPI2)
1124 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
1125  __IO uint32_t tmpreg; \
1126  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
1127  /* Delay after an RCC peripheral clock enabling */ \
1128  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
1129  UNUSED(tmpreg); \
1130  } while(0)
1131 #endif /* SPI2 */
1132 
1133 #if defined(SPI3)
1134 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1135  __IO uint32_t tmpreg; \
1136  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
1137  /* Delay after an RCC peripheral clock enabling */ \
1138  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
1139  UNUSED(tmpreg); \
1140  } while(0)
1141 #endif /* SPI3 */
1142 
1143 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
1144  __IO uint32_t tmpreg; \
1145  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
1146  /* Delay after an RCC peripheral clock enabling */ \
1147  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
1148  UNUSED(tmpreg); \
1149  } while(0)
1150 
1151 #if defined(USART3)
1152 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
1153  __IO uint32_t tmpreg; \
1154  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
1155  /* Delay after an RCC peripheral clock enabling */ \
1156  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
1157  UNUSED(tmpreg); \
1158  } while(0)
1159 #endif /* USART3 */
1160 
1161 #if defined(UART4)
1162 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1163  __IO uint32_t tmpreg; \
1164  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
1165  /* Delay after an RCC peripheral clock enabling */ \
1166  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
1167  UNUSED(tmpreg); \
1168  } while(0)
1169 #endif /* UART4 */
1170 
1171 #if defined(UART5)
1172 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1173  __IO uint32_t tmpreg; \
1174  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
1175  /* Delay after an RCC peripheral clock enabling */ \
1176  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
1177  UNUSED(tmpreg); \
1178  } while(0)
1179 #endif /* UART5 */
1180 
1181 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
1182  __IO uint32_t tmpreg; \
1183  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
1184  /* Delay after an RCC peripheral clock enabling */ \
1185  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
1186  UNUSED(tmpreg); \
1187  } while(0)
1188 
1189 #if defined(I2C2)
1190 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
1191  __IO uint32_t tmpreg; \
1192  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
1193  /* Delay after an RCC peripheral clock enabling */ \
1194  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
1195  UNUSED(tmpreg); \
1196  } while(0)
1197 #endif /* I2C2 */
1198 
1199 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1200  __IO uint32_t tmpreg; \
1201  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
1202  /* Delay after an RCC peripheral clock enabling */ \
1203  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
1204  UNUSED(tmpreg); \
1205  } while(0)
1206 
1207 #if defined(I2C4)
1208 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
1209  __IO uint32_t tmpreg; \
1210  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1211  /* Delay after an RCC peripheral clock enabling */ \
1212  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1213  UNUSED(tmpreg); \
1214  } while(0)
1215 #endif /* I2C4 */
1216 
1217 #if defined(CRS)
1218 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
1219  __IO uint32_t tmpreg; \
1220  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
1221  /* Delay after an RCC peripheral clock enabling */ \
1222  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
1223  UNUSED(tmpreg); \
1224  } while(0)
1225 #endif /* CRS */
1226 
1227 #if defined(CAN1)
1228 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
1229  __IO uint32_t tmpreg; \
1230  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
1231  /* Delay after an RCC peripheral clock enabling */ \
1232  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
1233  UNUSED(tmpreg); \
1234  } while(0)
1235 #endif /* CAN1 */
1236 
1237 #if defined(CAN2)
1238 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1239  __IO uint32_t tmpreg; \
1240  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
1241  /* Delay after an RCC peripheral clock enabling */ \
1242  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
1243  UNUSED(tmpreg); \
1244  } while(0)
1245 #endif /* CAN2 */
1246 
1247 #if defined(USB)
1248 #define __HAL_RCC_USB_CLK_ENABLE() do { \
1249  __IO uint32_t tmpreg; \
1250  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
1251  /* Delay after an RCC peripheral clock enabling */ \
1252  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
1253  UNUSED(tmpreg); \
1254  } while(0)
1255 #endif /* USB */
1256 
1257 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
1258  __IO uint32_t tmpreg; \
1259  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
1260  /* Delay after an RCC peripheral clock enabling */ \
1261  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
1262  UNUSED(tmpreg); \
1263  } while(0)
1264 
1265 #if defined(DAC1)
1266 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
1267  __IO uint32_t tmpreg; \
1268  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
1269  /* Delay after an RCC peripheral clock enabling */ \
1270  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
1271  UNUSED(tmpreg); \
1272  } while(0)
1273 #endif /* DAC1 */
1274 
1275 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
1276  __IO uint32_t tmpreg; \
1277  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
1278  /* Delay after an RCC peripheral clock enabling */ \
1279  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
1280  UNUSED(tmpreg); \
1281  } while(0)
1282 
1283 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
1284  __IO uint32_t tmpreg; \
1285  SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
1286  /* Delay after an RCC peripheral clock enabling */ \
1287  tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
1288  UNUSED(tmpreg); \
1289  } while(0)
1290 
1291 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
1292  __IO uint32_t tmpreg; \
1293  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1294  /* Delay after an RCC peripheral clock enabling */ \
1295  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
1296  UNUSED(tmpreg); \
1297  } while(0)
1298 
1299 #if defined(SWPMI1)
1300 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
1301  __IO uint32_t tmpreg; \
1302  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
1303  /* Delay after an RCC peripheral clock enabling */ \
1304  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
1305  UNUSED(tmpreg); \
1306  } while(0)
1307 #endif /* SWPMI1 */
1308 
1309 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
1310  __IO uint32_t tmpreg; \
1311  SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1312  /* Delay after an RCC peripheral clock enabling */ \
1313  tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
1314  UNUSED(tmpreg); \
1315  } while(0)
1316 
1317 
1318 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
1319 
1320 #if defined(TIM3)
1321 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
1322 #endif /* TIM3 */
1323 
1324 #if defined(TIM4)
1325 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
1326 #endif /* TIM4 */
1327 
1328 #if defined(TIM5)
1329 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1330 #endif /* TIM5 */
1331 
1332 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
1333 
1334 #if defined(TIM7)
1335 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
1336 #endif /* TIM7 */
1337 
1338 #if defined(LCD)
1339 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
1340 #endif /* LCD */
1341 
1342 #if defined(RCC_APB1ENR1_RTCAPBEN)
1343 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
1344 #endif /* RCC_APB1ENR1_RTCAPBEN */
1345 
1346 #if defined(SPI2)
1347 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
1348 #endif /* SPI2 */
1349 
1350 #if defined(SPI3)
1351 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
1352 #endif /* SPI3 */
1353 
1354 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
1355 
1356 #if defined(USART3)
1357 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
1358 #endif /* USART3 */
1359 
1360 #if defined(UART4)
1361 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
1362 #endif /* UART4 */
1363 
1364 #if defined(UART5)
1365 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
1366 #endif /* UART5 */
1367 
1368 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
1369 
1370 #if defined(I2C2)
1371 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
1372 #endif /* I2C2 */
1373 
1374 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
1375 
1376 #if defined(I2C4)
1377 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
1378 #endif /* I2C4 */
1379 
1380 #if defined(CRS)
1381 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
1382 #endif /* CRS */
1383 
1384 #if defined(CAN1)
1385 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
1386 #endif /* CAN1 */
1387 
1388 #if defined(CAN2)
1389 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
1390 #endif /* CAN2 */
1391 
1392 #if defined(USB)
1393 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
1394 #endif /* USB */
1395 
1396 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
1397 
1398 #if defined(DAC1)
1399 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
1400 #endif /* DAC1 */
1401 
1402 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
1403 
1404 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
1405 
1406 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
1407 
1408 #if defined(SWPMI1)
1409 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
1410 #endif /* SWPMI1 */
1411 
1412 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
1413 
1426 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
1427  __IO uint32_t tmpreg; \
1428  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
1429  /* Delay after an RCC peripheral clock enabling */ \
1430  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
1431  UNUSED(tmpreg); \
1432  } while(0)
1433 
1434 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
1435  __IO uint32_t tmpreg; \
1436  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
1437  /* Delay after an RCC peripheral clock enabling */ \
1438  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
1439  UNUSED(tmpreg); \
1440  } while(0)
1441 
1442 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
1443 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
1444  __IO uint32_t tmpreg; \
1445  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
1446  /* Delay after an RCC peripheral clock enabling */ \
1447  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
1448  UNUSED(tmpreg); \
1449  } while(0)
1450 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
1451 
1452 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
1453  __IO uint32_t tmpreg; \
1454  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1455  /* Delay after an RCC peripheral clock enabling */ \
1456  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1457  UNUSED(tmpreg); \
1458  } while(0)
1459 
1460 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
1461  __IO uint32_t tmpreg; \
1462  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1463  /* Delay after an RCC peripheral clock enabling */ \
1464  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1465  UNUSED(tmpreg); \
1466  } while(0)
1467 
1468 #if defined(TIM8)
1469 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1470  __IO uint32_t tmpreg; \
1471  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
1472  /* Delay after an RCC peripheral clock enabling */ \
1473  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
1474  UNUSED(tmpreg); \
1475  } while(0)
1476 #endif /* TIM8 */
1477 
1478 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
1479  __IO uint32_t tmpreg; \
1480  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1481  /* Delay after an RCC peripheral clock enabling */ \
1482  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1483  UNUSED(tmpreg); \
1484  } while(0)
1485 
1486 
1487 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
1488  __IO uint32_t tmpreg; \
1489  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
1490  /* Delay after an RCC peripheral clock enabling */ \
1491  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
1492  UNUSED(tmpreg); \
1493  } while(0)
1494 
1495 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
1496  __IO uint32_t tmpreg; \
1497  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
1498  /* Delay after an RCC peripheral clock enabling */ \
1499  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
1500  UNUSED(tmpreg); \
1501  } while(0)
1502 
1503 #if defined(TIM17)
1504 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
1505  __IO uint32_t tmpreg; \
1506  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
1507  /* Delay after an RCC peripheral clock enabling */ \
1508  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
1509  UNUSED(tmpreg); \
1510  } while(0)
1511 #endif /* TIM17 */
1512 
1513 #if defined(SAI1)
1514 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1515  __IO uint32_t tmpreg; \
1516  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
1517  /* Delay after an RCC peripheral clock enabling */ \
1518  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
1519  UNUSED(tmpreg); \
1520  } while(0)
1521 #endif /* SAI1 */
1522 
1523 #if defined(SAI2)
1524 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
1525  __IO uint32_t tmpreg; \
1526  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
1527  /* Delay after an RCC peripheral clock enabling */ \
1528  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
1529  UNUSED(tmpreg); \
1530  } while(0)
1531 #endif /* SAI2 */
1532 
1533 #if defined(DFSDM1_Filter0)
1534 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
1535  __IO uint32_t tmpreg; \
1536  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
1537  /* Delay after an RCC peripheral clock enabling */ \
1538  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
1539  UNUSED(tmpreg); \
1540  } while(0)
1541 #endif /* DFSDM1_Filter0 */
1542 
1543 #if defined(LTDC)
1544 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1545  __IO uint32_t tmpreg; \
1546  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
1547  /* Delay after an RCC peripheral clock enabling */ \
1548  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \
1549  UNUSED(tmpreg); \
1550  } while(0)
1551 #endif /* LTDC */
1552 
1553 #if defined(DSI)
1554 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
1555  __IO uint32_t tmpreg; \
1556  SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
1557  /* Delay after an RCC peripheral clock enabling */ \
1558  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \
1559  UNUSED(tmpreg); \
1560  } while(0)
1561 #endif /* DSI */
1562 
1563 
1564 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
1565 
1566 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
1567 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
1568 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
1569 
1570 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
1571 
1572 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
1573 
1574 #if defined(TIM8)
1575 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
1576 #endif /* TIM8 */
1577 
1578 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
1579 
1580 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
1581 
1582 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
1583 
1584 #if defined(TIM17)
1585 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
1586 #endif /* TIM17 */
1587 
1588 #if defined(SAI1)
1589 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
1590 #endif /* SAI1 */
1591 
1592 #if defined(SAI2)
1593 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
1594 #endif /* SAI2 */
1595 
1596 #if defined(DFSDM1_Filter0)
1597 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
1598 #endif /* DFSDM1_Filter0 */
1599 
1600 #if defined(LTDC)
1601 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN)
1602 #endif /* LTDC */
1603 
1604 #if defined(DSI)
1605 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN)
1606 #endif /* DSI */
1607 
1620 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
1621 
1622 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
1623 
1624 #if defined(DMAMUX1)
1625 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
1626 #endif /* DMAMUX1 */
1627 
1628 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
1629 
1630 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
1631 
1632 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U)
1633 
1634 #if defined(DMA2D)
1635 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U)
1636 #endif /* DMA2D */
1637 
1638 #if defined(GFXMMU)
1639 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U)
1640 #endif /* GFXMMU */
1641 
1642 
1643 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
1644 
1645 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
1646 
1647 #if defined(DMAMUX1)
1648 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
1649 #endif /* DMAMUX1 */
1650 
1651 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
1652 
1653 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
1654 
1655 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U)
1656 
1657 #if defined(DMA2D)
1658 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U)
1659 #endif /* DMA2D */
1660 
1661 #if defined(GFXMMU)
1662 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U)
1663 #endif /* GFXMMU */
1664 
1677 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
1678 
1679 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
1680 
1681 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
1682 
1683 #if defined(GPIOD)
1684 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
1685 #endif /* GPIOD */
1686 
1687 #if defined(GPIOE)
1688 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
1689 #endif /* GPIOE */
1690 
1691 #if defined(GPIOF)
1692 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
1693 #endif /* GPIOF */
1694 
1695 #if defined(GPIOG)
1696 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
1697 #endif /* GPIOG */
1698 
1699 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)
1700 
1701 #if defined(GPIOI)
1702 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)
1703 #endif /* GPIOI */
1704 
1705 #if defined(USB_OTG_FS)
1706 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != 0U)
1707 #endif /* USB_OTG_FS */
1708 
1709 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)
1710 
1711 #if defined(DCMI)
1712 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != 0U)
1713 #endif /* DCMI */
1714 
1715 #if defined(AES)
1716 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
1717 #endif /* AES */
1718 
1719 #if defined(HASH)
1720 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)
1721 #endif /* HASH */
1722 
1723 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
1724 
1725 
1726 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
1727 
1728 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
1729 
1730 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
1731 
1732 #if defined(GPIOD)
1733 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
1734 #endif /* GPIOD */
1735 
1736 #if defined(GPIOE)
1737 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
1738 #endif /* GPIOE */
1739 
1740 #if defined(GPIOF)
1741 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
1742 #endif /* GPIOF */
1743 
1744 #if defined(GPIOG)
1745 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
1746 #endif /* GPIOG */
1747 
1748 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)
1749 
1750 #if defined(GPIOI)
1751 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)
1752 #endif /* GPIOI */
1753 
1754 #if defined(USB_OTG_FS)
1755 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == 0U)
1756 #endif /* USB_OTG_FS */
1757 
1758 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)
1759 
1760 #if defined(DCMI)
1761 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == 0U)
1762 #endif /* DCMI */
1763 
1764 #if defined(AES)
1765 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
1766 #endif /* AES */
1767 
1768 #if defined(HASH)
1769 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)
1770 #endif /* HASH */
1771 
1772 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
1773 
1786 #if defined(FMC_BANK1)
1787 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1788 #endif /* FMC_BANK1 */
1789 
1790 #if defined(QUADSPI)
1791 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
1792 #endif /* QUADSPI */
1793 
1794 #if defined(FMC_BANK1)
1795 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
1796 #endif /* FMC_BANK1 */
1797 
1798 #if defined(QUADSPI)
1799 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
1800 #endif /* QUADSPI */
1801 
1814 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
1815 
1816 #if defined(TIM3)
1817 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
1818 #endif /* TIM3 */
1819 
1820 #if defined(TIM4)
1821 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
1822 #endif /* TIM4 */
1823 
1824 #if defined(TIM5)
1825 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
1826 #endif /* TIM5 */
1827 
1828 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
1829 
1830 #if defined(TIM7)
1831 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
1832 #endif /* TIM7 */
1833 
1834 #if defined(LCD)
1835 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != 0U)
1836 #endif /* LCD */
1837 
1838 #if defined(RCC_APB1ENR1_RTCAPBEN)
1839 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
1840 #endif /* RCC_APB1ENR1_RTCAPBEN */
1841 
1842 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
1843 
1844 #if defined(SPI2)
1845 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
1846 #endif /* SPI2 */
1847 
1848 #if defined(SPI3)
1849 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
1850 #endif /* SPI3 */
1851 
1852 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
1853 
1854 #if defined(USART3)
1855 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
1856 #endif /* USART3 */
1857 
1858 #if defined(UART4)
1859 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
1860 #endif /* UART4 */
1861 
1862 #if defined(UART5)
1863 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
1864 #endif /* UART5 */
1865 
1866 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
1867 
1868 #if defined(I2C2)
1869 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
1870 #endif /* I2C2 */
1871 
1872 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
1873 
1874 #if defined(I2C4)
1875 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
1876 #endif /* I2C4 */
1877 
1878 #if defined(CRS)
1879 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
1880 #endif /* CRS */
1881 
1882 #if defined(CAN1)
1883 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)
1884 #endif /* CAN1 */
1885 
1886 #if defined(CAN2)
1887 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != 0U)
1888 #endif /* CAN2 */
1889 
1890 #if defined(USB)
1891 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)
1892 #endif /* USB */
1893 
1894 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
1895 
1896 #if defined(DAC1)
1897 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U)
1898 #endif /* DAC1 */
1899 
1900 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U)
1901 
1902 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
1903 
1904 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
1905 
1906 #if defined(SWPMI1)
1907 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != 0U)
1908 #endif /* SWPMI1 */
1909 
1910 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U)
1911 
1912 
1913 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
1914 
1915 #if defined(TIM3)
1916 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
1917 #endif /* TIM3 */
1918 
1919 #if defined(TIM4)
1920 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
1921 #endif /* TIM4 */
1922 
1923 #if defined(TIM5)
1924 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
1925 #endif /* TIM5 */
1926 
1927 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
1928 
1929 #if defined(TIM7)
1930 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
1931 #endif /* TIM7 */
1932 
1933 #if defined(LCD)
1934 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == 0U)
1935 #endif /* LCD */
1936 
1937 #if defined(RCC_APB1ENR1_RTCAPBEN)
1938 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
1939 #endif /* RCC_APB1ENR1_RTCAPBEN */
1940 
1941 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
1942 
1943 #if defined(SPI2)
1944 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
1945 #endif /* SPI2 */
1946 
1947 #if defined(SPI3)
1948 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
1949 #endif /* SPI3 */
1950 
1951 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
1952 
1953 #if defined(USART3)
1954 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
1955 #endif /* USART3 */
1956 
1957 #if defined(UART4)
1958 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
1959 #endif /* UART4 */
1960 
1961 #if defined(UART5)
1962 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
1963 #endif /* UART5 */
1964 
1965 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
1966 
1967 #if defined(I2C2)
1968 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
1969 #endif /* I2C2 */
1970 
1971 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
1972 
1973 #if defined(I2C4)
1974 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
1975 #endif /* I2C4 */
1976 
1977 #if defined(CRS)
1978 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
1979 #endif /* CRS */
1980 
1981 #if defined(CAN1)
1982 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)
1983 #endif /* CAN1 */
1984 
1985 #if defined(CAN2)
1986 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == 0U)
1987 #endif /* CAN2 */
1988 
1989 #if defined(USB)
1990 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)
1991 #endif /* USB */
1992 
1993 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
1994 
1995 #if defined(DAC1)
1996 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U)
1997 #endif /* DAC1 */
1998 
1999 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U)
2000 
2001 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
2002 
2003 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
2004 
2005 #if defined(SWPMI1)
2006 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == 0U)
2007 #endif /* SWPMI1 */
2008 
2009 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U)
2010 
2023 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
2024 
2025 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U)
2026 
2027 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
2028 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != 0U)
2029 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
2030 
2031 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
2032 
2033 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
2034 
2035 #if defined(TIM8)
2036 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
2037 #endif /* TIM8 */
2038 
2039 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
2040 
2041 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
2042 
2043 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
2044 
2045 #if defined(TIM17)
2046 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
2047 #endif /* TIM17 */
2048 
2049 #if defined(SAI1)
2050 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
2051 #endif /* SAI1 */
2052 
2053 #if defined(SAI2)
2054 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
2055 #endif /* SAI2 */
2056 
2057 #if defined(DFSDM1_Filter0)
2058 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U)
2059 #endif /* DFSDM1_Filter0 */
2060 
2061 #if defined(LTDC)
2062 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U)
2063 #endif /* LTDC */
2064 
2065 #if defined(DSI)
2066 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != 0U)
2067 #endif /* DSI */
2068 
2069 
2070 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
2071 
2072 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
2073 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == 0U)
2074 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
2075 
2076 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
2077 
2078 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
2079 
2080 #if defined(TIM8)
2081 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
2082 #endif /* TIM8 */
2083 
2084 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
2085 
2086 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
2087 
2088 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
2089 
2090 #if defined(TIM17)
2091 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
2092 #endif /* TIM17 */
2093 
2094 #if defined(SAI1)
2095 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
2096 #endif /* SAI1 */
2097 
2098 #if defined(SAI2)
2099 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)
2100 #endif /* SAI2 */
2101 
2102 #if defined(DFSDM1_Filter0)
2103 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U)
2104 #endif /* DFSDM1_Filter0 */
2105 
2106 #if defined(LTDC)
2107 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U)
2108 #endif /* LTDC */
2109 
2110 #if defined(DSI)
2111 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == 0U)
2112 #endif /* DSI */
2113 
2122 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
2123 
2124 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
2125 
2126 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
2127 
2128 #if defined(DMAMUX1)
2129 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
2130 #endif /* DMAMUX1 */
2131 
2132 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
2133 
2134 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
2135 
2136 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
2137 
2138 #if defined(DMA2D)
2139 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
2140 #endif /* DMA2D */
2141 
2142 #if defined(GFXMMU)
2143 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
2144 #endif /* GFXMMU */
2145 
2146 
2147 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
2148 
2149 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
2150 
2151 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
2152 
2153 #if defined(DMAMUX1)
2154 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
2155 #endif /* DMAMUX1 */
2156 
2157 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
2158 
2159 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
2160 
2161 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
2162 
2163 #if defined(DMA2D)
2164 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
2165 #endif /* DMA2D */
2166 
2167 #if defined(GFXMMU)
2168 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST)
2169 #endif /* GFXMMU */
2170 
2179 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
2180 
2181 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
2182 
2183 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
2184 
2185 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
2186 
2187 #if defined(GPIOD)
2188 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
2189 #endif /* GPIOD */
2190 
2191 #if defined(GPIOE)
2192 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
2193 #endif /* GPIOE */
2194 
2195 #if defined(GPIOF)
2196 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
2197 #endif /* GPIOF */
2198 
2199 #if defined(GPIOG)
2200 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
2201 #endif /* GPIOG */
2202 
2203 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
2204 
2205 #if defined(GPIOI)
2206 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
2207 #endif /* GPIOI */
2208 
2209 #if defined(USB_OTG_FS)
2210 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
2211 #endif /* USB_OTG_FS */
2212 
2213 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
2214 
2215 #if defined(DCMI)
2216 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
2217 #endif /* DCMI */
2218 
2219 #if defined(AES)
2220 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
2221 #endif /* AES */
2222 
2223 #if defined(HASH)
2224 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
2225 #endif /* HASH */
2226 
2227 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
2228 
2229 #if defined(OCTOSPIM)
2230 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
2231 #endif /* OCTOSPIM */
2232 
2233 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
2234 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
2235 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
2236 
2237 
2238 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
2239 
2240 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
2241 
2242 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
2243 
2244 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
2245 
2246 #if defined(GPIOD)
2247 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
2248 #endif /* GPIOD */
2249 
2250 #if defined(GPIOE)
2251 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
2252 #endif /* GPIOE */
2253 
2254 #if defined(GPIOF)
2255 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
2256 #endif /* GPIOF */
2257 
2258 #if defined(GPIOG)
2259 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
2260 #endif /* GPIOG */
2261 
2262 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
2263 
2264 #if defined(GPIOI)
2265 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
2266 #endif /* GPIOI */
2267 
2268 #if defined(USB_OTG_FS)
2269 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
2270 #endif /* USB_OTG_FS */
2271 
2272 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
2273 
2274 #if defined(DCMI)
2275 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
2276 #endif /* DCMI */
2277 
2278 #if defined(AES)
2279 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
2280 #endif /* AES */
2281 
2282 #if defined(HASH)
2283 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
2284 #endif /* HASH */
2285 
2286 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
2287 
2288 #if defined(OCTOSPIM)
2289 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST)
2290 #endif /* OCTOSPIM */
2291 
2292 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST)
2293 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
2294 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */
2295 
2304 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
2305 
2306 #if defined(FMC_BANK1)
2307 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
2308 #endif /* FMC_BANK1 */
2309 
2310 #if defined(QUADSPI)
2311 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
2312 #endif /* QUADSPI */
2313 
2314 #if defined(OCTOSPI1)
2315 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
2316 #endif /* OCTOSPI1 */
2317 
2318 #if defined(OCTOSPI2)
2319 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
2320 #endif /* OCTOSPI2 */
2321 
2322 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
2323 
2324 #if defined(FMC_BANK1)
2325 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
2326 #endif /* FMC_BANK1 */
2327 
2328 #if defined(QUADSPI)
2329 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
2330 #endif /* QUADSPI */
2331 
2332 #if defined(OCTOSPI1)
2333 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
2334 #endif /* OCTOSPI1 */
2335 
2336 #if defined(OCTOSPI2)
2337 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST)
2338 #endif /* OCTOSPI2 */
2339 
2348 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
2349 
2350 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2351 
2352 #if defined(TIM3)
2353 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2354 #endif /* TIM3 */
2355 
2356 #if defined(TIM4)
2357 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2358 #endif /* TIM4 */
2359 
2360 #if defined(TIM5)
2361 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2362 #endif /* TIM5 */
2363 
2364 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
2365 
2366 #if defined(TIM7)
2367 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
2368 #endif /* TIM7 */
2369 
2370 #if defined(LCD)
2371 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
2372 #endif /* LCD */
2373 
2374 #if defined(SPI2)
2375 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
2376 #endif /* SPI2 */
2377 
2378 #if defined(SPI3)
2379 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
2380 #endif /* SPI3 */
2381 
2382 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
2383 
2384 #if defined(USART3)
2385 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
2386 #endif /* USART3 */
2387 
2388 #if defined(UART4)
2389 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
2390 #endif /* UART4 */
2391 
2392 #if defined(UART5)
2393 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
2394 #endif /* UART5 */
2395 
2396 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
2397 
2398 #if defined(I2C2)
2399 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
2400 #endif /* I2C2 */
2401 
2402 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
2403 
2404 #if defined(I2C4)
2405 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
2406 #endif /* I2C4 */
2407 
2408 #if defined(CRS)
2409 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
2410 #endif /* CRS */
2411 
2412 #if defined(CAN1)
2413 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
2414 #endif /* CAN1 */
2415 
2416 #if defined(CAN2)
2417 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
2418 #endif /* CAN2 */
2419 
2420 #if defined(USB)
2421 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
2422 #endif /* USB */
2423 
2424 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
2425 
2426 #if defined(DAC1)
2427 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
2428 #endif /* DAC1 */
2429 
2430 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
2431 
2432 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
2433 
2434 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
2435 
2436 #if defined(SWPMI1)
2437 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
2438 #endif /* SWPMI1 */
2439 
2440 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
2441 
2442 
2443 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
2444 
2445 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2446 
2447 #if defined(TIM3)
2448 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2449 #endif /* TIM3 */
2450 
2451 #if defined(TIM4)
2452 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2453 #endif /* TIM4 */
2454 
2455 #if defined(TIM5)
2456 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2457 #endif /* TIM5 */
2458 
2459 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
2460 
2461 #if defined(TIM7)
2462 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
2463 #endif /* TIM7 */
2464 
2465 #if defined(LCD)
2466 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
2467 #endif /* LCD */
2468 
2469 #if defined(SPI2)
2470 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
2471 #endif /* SPI2 */
2472 
2473 #if defined(SPI3)
2474 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
2475 #endif /* SPI3 */
2476 
2477 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
2478 
2479 #if defined(USART3)
2480 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
2481 #endif /* USART3 */
2482 
2483 #if defined(UART4)
2484 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
2485 #endif /* UART4 */
2486 
2487 #if defined(UART5)
2488 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
2489 #endif /* UART5 */
2490 
2491 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
2492 
2493 #if defined(I2C2)
2494 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
2495 #endif /* I2C2 */
2496 
2497 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
2498 
2499 #if defined(I2C4)
2500 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
2501 #endif /* I2C4 */
2502 
2503 #if defined(CRS)
2504 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
2505 #endif /* CRS */
2506 
2507 #if defined(CAN1)
2508 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
2509 #endif /* CAN1 */
2510 
2511 #if defined(CAN2)
2512 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
2513 #endif /* CAN2 */
2514 
2515 #if defined(USB)
2516 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
2517 #endif /* USB */
2518 
2519 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
2520 
2521 #if defined(DAC1)
2522 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
2523 #endif /* DAC1 */
2524 
2525 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
2526 
2527 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
2528 
2529 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
2530 
2531 #if defined(SWPMI1)
2532 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
2533 #endif /* SWPMI1 */
2534 
2535 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
2536 
2545 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
2546 
2547 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
2548 
2549 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
2550 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
2551 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
2552 
2553 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
2554 
2555 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
2556 
2557 #if defined(TIM8)
2558 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
2559 #endif /* TIM8 */
2560 
2561 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
2562 
2563 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
2564 
2565 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
2566 
2567 #if defined(TIM17)
2568 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
2569 #endif /* TIM17 */
2570 
2571 #if defined(SAI1)
2572 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
2573 #endif /* SAI1 */
2574 
2575 #if defined(SAI2)
2576 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
2577 #endif /* SAI2 */
2578 
2579 #if defined(DFSDM1_Filter0)
2580 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
2581 #endif /* DFSDM1_Filter0 */
2582 
2583 #if defined(LTDC)
2584 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
2585 #endif /* LTDC */
2586 
2587 #if defined(DSI)
2588 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
2589 #endif /* DSI */
2590 
2591 
2592 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
2593 
2594 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
2595 
2596 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST)
2597 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
2598 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */
2599 
2600 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
2601 
2602 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
2603 
2604 #if defined(TIM8)
2605 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
2606 #endif /* TIM8 */
2607 
2608 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
2609 
2610 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
2611 
2612 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
2613 
2614 #if defined(TIM17)
2615 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
2616 #endif /* TIM17 */
2617 
2618 #if defined(SAI1)
2619 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
2620 #endif /* SAI1 */
2621 
2622 #if defined(SAI2)
2623 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
2624 #endif /* SAI2 */
2625 
2626 #if defined(DFSDM1_Filter0)
2627 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
2628 #endif /* DFSDM1_Filter0 */
2629 
2630 #if defined(LTDC)
2631 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST)
2632 #endif /* LTDC */
2633 
2634 #if defined(DSI)
2635 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST)
2636 #endif /* DSI */
2637 
2651 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
2652 
2653 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
2654 
2655 #if defined(DMAMUX1)
2656 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
2657 #endif /* DMAMUX1 */
2658 
2659 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
2660 
2661 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
2662 
2663 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
2664 
2665 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
2666 
2667 #if defined(DMA2D)
2668 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
2669 #endif /* DMA2D */
2670 
2671 #if defined(GFXMMU)
2672 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
2673 #endif /* GFXMMU */
2674 
2675 
2676 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
2677 
2678 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
2679 
2680 #if defined(DMAMUX1)
2681 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
2682 #endif /* DMAMUX1 */
2683 
2684 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
2685 
2686 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
2687 
2688 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
2689 
2690 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
2691 
2692 #if defined(DMA2D)
2693 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
2694 #endif /* DMA2D */
2695 
2696 #if defined(GFXMMU)
2697 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN)
2698 #endif /* GFXMMU */
2699 
2713 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
2714 
2715 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
2716 
2717 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
2718 
2719 #if defined(GPIOD)
2720 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
2721 #endif /* GPIOD */
2722 
2723 #if defined(GPIOE)
2724 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
2725 #endif /* GPIOE */
2726 
2727 #if defined(GPIOF)
2728 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
2729 #endif /* GPIOF */
2730 
2731 #if defined(GPIOG)
2732 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
2733 #endif /* GPIOG */
2734 
2735 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
2736 
2737 #if defined(GPIOI)
2738 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
2739 #endif /* GPIOI */
2740 
2741 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
2742 
2743 #if defined(SRAM3)
2744 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
2745 #endif /* SRAM3 */
2746 
2747 #if defined(USB_OTG_FS)
2748 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
2749 #endif /* USB_OTG_FS */
2750 
2751 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
2752 
2753 #if defined(DCMI)
2754 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
2755 #endif /* DCMI */
2756 
2757 #if defined(AES)
2758 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
2759 #endif /* AES */
2760 
2761 #if defined(HASH)
2762 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
2763 #endif /* HASH */
2764 
2765 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
2766 
2767 #if defined(OCTOSPIM)
2768 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
2769 #endif /* OCTOSPIM */
2770 
2771 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
2772 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
2773 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
2774 
2775 
2776 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
2777 
2778 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
2779 
2780 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
2781 
2782 #if defined(GPIOD)
2783 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
2784 #endif /* GPIOD */
2785 
2786 #if defined(GPIOE)
2787 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
2788 #endif /* GPIOE */
2789 
2790 #if defined(GPIOF)
2791 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
2792 #endif /* GPIOF */
2793 
2794 #if defined(GPIOG)
2795 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
2796 #endif /* GPIOG */
2797 
2798 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
2799 
2800 #if defined(GPIOI)
2801 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
2802 #endif /* GPIOI */
2803 
2804 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
2805 
2806 #if defined(SRAM3)
2807 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN)
2808 #endif /* SRAM3 */
2809 
2810 #if defined(USB_OTG_FS)
2811 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
2812 #endif /* USB_OTG_FS */
2813 
2814 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
2815 
2816 #if defined(DCMI)
2817 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
2818 #endif /* DCMI */
2819 
2820 #if defined(AES)
2821 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
2822 #endif /* AES */
2823 
2824 #if defined(HASH)
2825 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
2826 #endif /* HASH */
2827 
2828 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
2829 
2830 #if defined(OCTOSPIM)
2831 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN)
2832 #endif /* OCTOSPIM */
2833 
2834 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
2835 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN)
2836 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
2837 
2851 #if defined(QUADSPI)
2852 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
2853 #endif /* QUADSPI */
2854 
2855 #if defined(OCTOSPI1)
2856 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
2857 #endif /* OCTOSPI1 */
2858 
2859 #if defined(OCTOSPI2)
2860 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
2861 #endif /* OCTOSPI2 */
2862 
2863 #if defined(FMC_BANK1)
2864 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
2865 #endif /* FMC_BANK1 */
2866 
2867 #if defined(QUADSPI)
2868 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
2869 #endif /* QUADSPI */
2870 
2871 #if defined(OCTOSPI1)
2872 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN)
2873 #endif /* OCTOSPI1 */
2874 
2875 #if defined(OCTOSPI2)
2876 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN)
2877 #endif /* OCTOSPI2 */
2878 
2879 #if defined(FMC_BANK1)
2880 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
2881 #endif /* FMC_BANK1 */
2882 
2896 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
2897 
2898 #if defined(TIM3)
2899 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
2900 #endif /* TIM3 */
2901 
2902 #if defined(TIM4)
2903 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2904 #endif /* TIM4 */
2905 
2906 #if defined(TIM5)
2907 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
2908 #endif /* TIM5 */
2909 
2910 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
2911 
2912 #if defined(TIM7)
2913 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
2914 #endif /* TIM7 */
2915 
2916 #if defined(LCD)
2917 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
2918 #endif /* LCD */
2919 
2920 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
2921 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
2922 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
2923 
2924 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
2925 
2926 #if defined(SPI2)
2927 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
2928 #endif /* SPI2 */
2929 
2930 #if defined(SPI3)
2931 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
2932 #endif /* SPI3 */
2933 
2934 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
2935 
2936 #if defined(USART3)
2937 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
2938 #endif /* USART3 */
2939 
2940 #if defined(UART4)
2941 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
2942 #endif /* UART4 */
2943 
2944 #if defined(UART5)
2945 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
2946 #endif /* UART5 */
2947 
2948 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
2949 
2950 #if defined(I2C2)
2951 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
2952 #endif /* I2C2 */
2953 
2954 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
2955 
2956 #if defined(I2C4)
2957 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
2958 #endif /* I2C4 */
2959 
2960 #if defined(CRS)
2961 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
2962 #endif /* CRS */
2963 
2964 #if defined(CAN1)
2965 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
2966 #endif /* CAN1 */
2967 
2968 #if defined(CAN2)
2969 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
2970 #endif /* CAN2 */
2971 
2972 #if defined(USB)
2973 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
2974 #endif /* USB */
2975 
2976 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
2977 
2978 #if defined(DAC1)
2979 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
2980 #endif /* DAC1 */
2981 
2982 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
2983 
2984 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
2985 
2986 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
2987 
2988 #if defined(SWPMI1)
2989 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
2990 #endif /* SWPMI1 */
2991 
2992 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
2993 
2994 
2995 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
2996 
2997 #if defined(TIM3)
2998 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
2999 #endif /* TIM3 */
3000 
3001 #if defined(TIM4)
3002 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
3003 #endif /* TIM4 */
3004 
3005 #if defined(TIM5)
3006 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
3007 #endif /* TIM5 */
3008 
3009 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
3010 
3011 #if defined(TIM7)
3012 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
3013 #endif /* TIM7 */
3014 
3015 #if defined(LCD)
3016 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
3017 #endif /* LCD */
3018 
3019 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
3020 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
3021 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
3022 
3023 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
3024 
3025 #if defined(SPI2)
3026 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
3027 #endif /* SPI2 */
3028 
3029 #if defined(SPI3)
3030 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
3031 #endif /* SPI3 */
3032 
3033 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
3034 
3035 #if defined(USART3)
3036 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
3037 #endif /* USART3 */
3038 
3039 #if defined(UART4)
3040 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
3041 #endif /* UART4 */
3042 
3043 #if defined(UART5)
3044 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
3045 #endif /* UART5 */
3046 
3047 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
3048 
3049 #if defined(I2C2)
3050 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
3051 #endif /* I2C2 */
3052 
3053 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
3054 
3055 #if defined(I2C4)
3056 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
3057 #endif /* I2C4 */
3058 
3059 #if defined(CRS)
3060 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
3061 #endif /* CRS */
3062 
3063 #if defined(CAN1)
3064 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
3065 #endif /* CAN1 */
3066 
3067 #if defined(CAN2)
3068 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
3069 #endif /* CAN2 */
3070 
3071 #if defined(USB)
3072 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
3073 #endif /* USB */
3074 
3075 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
3076 
3077 #if defined(DAC1)
3078 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
3079 #endif /* DAC1 */
3080 
3081 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
3082 
3083 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
3084 
3085 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
3086 
3087 #if defined(SWPMI1)
3088 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
3089 #endif /* SWPMI1 */
3090 
3091 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
3092 
3106 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
3107 
3108 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
3109 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
3110 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
3111 
3112 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
3113 
3114 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
3115 
3116 #if defined(TIM8)
3117 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
3118 #endif /* TIM8 */
3119 
3120 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
3121 
3122 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
3123 
3124 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
3125 
3126 #if defined(TIM17)
3127 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
3128 #endif /* TIM17 */
3129 
3130 #if defined(SAI1)
3131 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
3132 #endif /* SAI1 */
3133 
3134 #if defined(SAI2)
3135 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
3136 #endif /* SAI2 */
3137 
3138 #if defined(DFSDM1_Filter0)
3139 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
3140 #endif /* DFSDM1_Filter0 */
3141 
3142 #if defined(LTDC)
3143 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
3144 #endif /* LTDC */
3145 
3146 #if defined(DSI)
3147 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
3148 #endif /* DSI */
3149 
3150 
3151 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
3152 
3153 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
3154 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
3155 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
3156 
3157 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
3158 
3159 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
3160 
3161 #if defined(TIM8)
3162 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
3163 #endif /* TIM8 */
3164 
3165 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
3166 
3167 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
3168 
3169 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
3170 
3171 #if defined(TIM17)
3172 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
3173 #endif /* TIM17 */
3174 
3175 #if defined(SAI1)
3176 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
3177 #endif /* SAI1 */
3178 
3179 #if defined(SAI2)
3180 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
3181 #endif /* SAI2 */
3182 
3183 #if defined(DFSDM1_Filter0)
3184 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
3185 #endif /* DFSDM1_Filter0 */
3186 
3187 #if defined(LTDC)
3188 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN)
3189 #endif /* LTDC */
3190 
3191 #if defined(DSI)
3192 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN)
3193 #endif /* DSI */
3194 
3208 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
3209 
3210 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
3211 
3212 #if defined(DMAMUX1)
3213 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
3214 #endif /* DMAMUX1 */
3215 
3216 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
3217 
3218 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
3219 
3220 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
3221 
3222 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U)
3223 
3224 #if defined(DMA2D)
3225 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != 0U)
3226 #endif /* DMA2D */
3227 
3228 #if defined(GFXMMU)
3229 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != 0U)
3230 #endif /* GFXMMU */
3231 
3232 
3233 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
3234 
3235 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
3236 
3237 #if defined(DMAMUX1)
3238 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
3239 #endif /* DMAMUX1 */
3240 
3241 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
3242 
3243 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
3244 
3245 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
3246 
3247 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U)
3248 
3249 #if defined(DMA2D)
3250 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == 0U)
3251 #endif /* DMA2D */
3252 
3253 #if defined(GFXMMU)
3254 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == 0U)
3255 #endif /* GFXMMU */
3256 
3270 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
3271 
3272 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
3273 
3274 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
3275 
3276 #if defined(GPIOD)
3277 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
3278 #endif /* GPIOD */
3279 
3280 #if defined(GPIOE)
3281 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
3282 #endif /* GPIOE */
3283 
3284 #if defined(GPIOF)
3285 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
3286 #endif /* GPIOF */
3287 
3288 #if defined(GPIOG)
3289 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
3290 #endif /* GPIOG */
3291 
3292 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U)
3293 
3294 #if defined(GPIOI)
3295 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != 0U)
3296 #endif /* GPIOI */
3297 
3298 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
3299 
3300 #if defined(SRAM3)
3301 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != 0U)
3302 #endif /* SRAM3 */
3303 
3304 #if defined(USB_OTG_FS)
3305 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != 0U)
3306 #endif /* USB_OTG_FS */
3307 
3308 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U)
3309 
3310 #if defined(DCMI)
3311 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != 0U)
3312 #endif /* DCMI */
3313 
3314 #if defined(AES)
3315 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
3316 #endif /* AES */
3317 
3318 #if defined(HASH)
3319 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U)
3320 #endif /* HASH */
3321 
3322 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
3323 
3324 #if defined(OCTOSPIM)
3325 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != 0U)
3326 #endif /* OCTOSPIM */
3327 
3328 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
3329 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U)
3330 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
3331 
3332 
3333 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
3334 
3335 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
3336 
3337 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
3338 
3339 #if defined(GPIOD)
3340 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
3341 #endif /* GPIOD */
3342 
3343 #if defined(GPIOE)
3344 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
3345 #endif /* GPIOE */
3346 
3347 #if defined(GPIOF)
3348 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
3349 #endif /* GPIOF */
3350 
3351 #if defined(GPIOG)
3352 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
3353 #endif /* GPIOG */
3354 
3355 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U)
3356 
3357 #if defined(GPIOI)
3358 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == 0U)
3359 #endif /* GPIOI */
3360 
3361 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
3362 
3363 #if defined(SRAM3)
3364 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == 0U)
3365 #endif /* SRAM3 */
3366 
3367 #if defined(USB_OTG_FS)
3368 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == 0U)
3369 #endif /* USB_OTG_FS */
3370 
3371 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U)
3372 
3373 #if defined(DCMI)
3374 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == 0U)
3375 #endif /* DCMI */
3376 
3377 #if defined(AES)
3378 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
3379 #endif /* AES */
3380 
3381 #if defined(HASH)
3382 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U)
3383 #endif /* HASH */
3384 
3385 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
3386 
3387 #if defined(OCTOSPIM)
3388 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == 0U)
3389 #endif /* OCTOSPIM */
3390 
3391 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN)
3392 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U)
3393 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */
3394 
3408 #if defined(QUADSPI)
3409 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
3410 #endif /* QUADSPI */
3411 
3412 #if defined(OCTOSPI1)
3413 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != 0U)
3414 #endif /* OCTOSPI1 */
3415 
3416 #if defined(OCTOSPI2)
3417 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != 0U)
3418 #endif /* OCTOSPI2 */
3419 
3420 #if defined(FMC_BANK1)
3421 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
3422 #endif /* FMC_BANK1 */
3423 
3424 
3425 #if defined(QUADSPI)
3426 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
3427 #endif /* QUADSPI */
3428 
3429 #if defined(OCTOSPI1)
3430 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == 0U)
3431 #endif /* OCTOSPI1 */
3432 
3433 #if defined(OCTOSPI2)
3434 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == 0U)
3435 #endif /* OCTOSPI2 */
3436 
3437 #if defined(FMC_BANK1)
3438 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
3439 #endif /* FMC_BANK1 */
3440 
3454 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
3455 
3456 #if defined(TIM3)
3457 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
3458 #endif /* TIM3 */
3459 
3460 #if defined(TIM4)
3461 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
3462 #endif /* TIM4 */
3463 
3464 #if defined(TIM5)
3465 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
3466 #endif /* TIM5 */
3467 
3468 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
3469 
3470 #if defined(TIM7)
3471 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
3472 #endif /* TIM7 */
3473 
3474 #if defined(LCD)
3475 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != 0U)
3476 #endif /* LCD */
3477 
3478 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
3479 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
3480 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
3481 
3482 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
3483 
3484 #if defined(SPI2)
3485 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
3486 #endif /* SPI2 */
3487 
3488 #if defined(SPI3)
3489 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
3490 #endif /* SPI3 */
3491 
3492 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
3493 
3494 #if defined(USART3)
3495 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
3496 #endif /* USART3 */
3497 
3498 #if defined(UART4)
3499 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
3500 #endif /* UART4 */
3501 
3502 #if defined(UART5)
3503 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
3504 #endif /* UART5 */
3505 
3506 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
3507 
3508 #if defined(I2C2)
3509 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
3510 #endif /* I2C2 */
3511 
3512 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
3513 
3514 #if defined(I2C4)
3515 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
3516 #endif /* I2C4 */
3517 
3518 #if defined(CRS)
3519 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
3520 #endif /* CRS */
3521 
3522 #if defined(CAN1)
3523 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)
3524 #endif /* CAN1 */
3525 
3526 #if defined(CAN2)
3527 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != 0U)
3528 #endif /* CAN2 */
3529 
3530 #if defined(USB)
3531 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)
3532 #endif /* USB */
3533 
3534 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
3535 
3536 #if defined(DAC1)
3537 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U)
3538 #endif /* DAC1 */
3539 
3540 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U)
3541 
3542 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
3543 
3544 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
3545 
3546 #if defined(SWPMI1)
3547 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != 0U)
3548 #endif /* SWPMI1 */
3549 
3550 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U)
3551 
3552 
3553 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
3554 
3555 #if defined(TIM3)
3556 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
3557 #endif /* TIM3 */
3558 
3559 #if defined(TIM4)
3560 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
3561 #endif /* TIM4 */
3562 
3563 #if defined(TIM5)
3564 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
3565 #endif /* TIM5 */
3566 
3567 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
3568 
3569 #if defined(TIM7)
3570 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
3571 #endif /* TIM7 */
3572 
3573 #if defined(LCD)
3574 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == 0U)
3575 #endif /* LCD */
3576 
3577 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
3578 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
3579 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
3580 
3581 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
3582 
3583 #if defined(SPI2)
3584 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
3585 #endif /* SPI2 */
3586 
3587 #if defined(SPI3)
3588 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
3589 #endif /* SPI3 */
3590 
3591 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
3592 
3593 #if defined(USART3)
3594 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
3595 #endif /* USART3 */
3596 
3597 #if defined(UART4)
3598 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
3599 #endif /* UART4 */
3600 
3601 #if defined(UART5)
3602 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
3603 #endif /* UART5 */
3604 
3605 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
3606 
3607 #if defined(I2C2)
3608 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
3609 #endif /* I2C2 */
3610 
3611 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
3612 
3613 #if defined(I2C4)
3614 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
3615 #endif /* I2C4 */
3616 
3617 #if defined(CRS)
3618 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
3619 #endif /* CRS */
3620 
3621 #if defined(CAN1)
3622 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)
3623 #endif /* CAN1 */
3624 
3625 #if defined(CAN2)
3626 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == 0U)
3627 #endif /* CAN2 */
3628 
3629 #if defined(USB)
3630 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)
3631 #endif /* USB */
3632 
3633 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
3634 
3635 #if defined(DAC1)
3636 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U)
3637 #endif /* DAC1 */
3638 
3639 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U)
3640 
3641 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
3642 
3643 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
3644 
3645 #if defined(SWPMI1)
3646 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == 0U)
3647 #endif /* SWPMI1 */
3648 
3649 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U)
3650 
3664 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
3665 
3666 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
3667 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != 0U)
3668 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
3669 
3670 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
3671 
3672 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
3673 
3674 #if defined(TIM8)
3675 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
3676 #endif /* TIM8 */
3677 
3678 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
3679 
3680 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
3681 
3682 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
3683 
3684 #if defined(TIM17)
3685 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
3686 #endif /* TIM17 */
3687 
3688 #if defined(SAI1)
3689 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
3690 #endif /* SAI1 */
3691 
3692 #if defined(SAI2)
3693 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U)
3694 #endif /* SAI2 */
3695 
3696 #if defined(DFSDM1_Filter0)
3697 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U)
3698 #endif /* DFSDM1_Filter0 */
3699 
3700 #if defined(LTDC)
3701 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != 0U)
3702 #endif /* LTDC */
3703 
3704 #if defined(DSI)
3705 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != 0U)
3706 #endif /* DSI */
3707 
3708 
3709 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
3710 
3711 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN)
3712 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == 0U)
3713 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */
3714 
3715 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
3716 
3717 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
3718 
3719 #if defined(TIM8)
3720 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
3721 #endif /* TIM8 */
3722 
3723 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
3724 
3725 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
3726 
3727 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
3728 
3729 #if defined(TIM17)
3730 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
3731 #endif /* TIM17 */
3732 
3733 #if defined(SAI1)
3734 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
3735 #endif /* SAI1 */
3736 
3737 #if defined(SAI2)
3738 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U)
3739 #endif /* SAI2 */
3740 
3741 #if defined(DFSDM1_Filter0)
3742 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U)
3743 #endif /* DFSDM1_Filter0 */
3744 
3745 #if defined(LTDC)
3746 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == 0U)
3747 #endif /* LTDC */
3748 
3749 #if defined(DSI)
3750 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == 0U)
3751 #endif /* DSI */
3752 
3767 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
3768 
3769 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
3770 
3787 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
3788 
3789 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
3790 
3811 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
3812 
3813 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
3814 
3823 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
3824  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
3825 
3833 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
3834 
3835 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
3836 
3846 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
3847 
3848 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
3849 
3867 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
3868 
3869 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
3870 
3881 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
3882  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
3883 
3910 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
3911  do { \
3912  SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
3913  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
3914  } while(0)
3915 
3927 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
3928  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
3929 
3946 #define __HAL_RCC_GET_MSI_RANGE() \
3947  ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \
3948  READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \
3949  (READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U))
3950 
3960 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
3961 
3962 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
3963 
3987 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
3988  do { \
3989  if((__STATE__) == RCC_HSE_ON) \
3990  { \
3991  SET_BIT(RCC->CR, RCC_CR_HSEON); \
3992  } \
3993  else if((__STATE__) == RCC_HSE_BYPASS) \
3994  { \
3995  SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
3996  SET_BIT(RCC->CR, RCC_CR_HSEON); \
3997  } \
3998  else \
3999  { \
4000  CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
4001  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
4002  } \
4003  } while(0)
4004 
4025 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
4026  do { \
4027  if((__STATE__) == RCC_LSE_ON) \
4028  { \
4029  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4030  } \
4031  else if((__STATE__) == RCC_LSE_BYPASS) \
4032  { \
4033  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
4034  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4035  } \
4036  else \
4037  { \
4038  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4039  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
4040  } \
4041  } while(0)
4042 
4043 #if defined(RCC_HSI48_SUPPORT)
4044 
4052 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
4053 
4054 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
4055 
4056 #endif /* RCC_HSI48_SUPPORT */
4057 
4082 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
4083  MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
4084 
4085 
4093 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
4094 
4103 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
4104 
4105 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
4106 
4119 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
4120  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
4121 
4133 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
4134  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
4135 
4175 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
4176 
4177 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
4178  MODIFY_REG(RCC->PLLCFGR, \
4179  (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
4180  RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPDIV), \
4181  ((__PLLSOURCE__) | \
4182  (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
4183  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
4184  ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
4185  ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
4186  ((uint32_t)(__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
4187 
4188 #elif defined(RCC_PLLP_SUPPORT)
4189 
4190 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
4191  MODIFY_REG(RCC->PLLCFGR, \
4192  (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
4193  RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLP), \
4194  ((__PLLSOURCE__) | \
4195  (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
4196  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
4197  ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
4198  ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
4199  (((__PLLP__) >> 4U) << RCC_PLLCFGR_PLLP_Pos)))
4200 
4201 #else
4202 
4203 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLQ__,__PLLR__ ) \
4204  MODIFY_REG(RCC->PLLCFGR, \
4205  (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
4206  RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \
4207  ((__PLLSOURCE__) | \
4208  (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
4209  ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
4210  ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
4211  ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
4212 
4213 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
4214 
4223 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
4224 
4239 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
4240 
4241 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
4242 
4254 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
4255 
4266 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
4267  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
4268 
4277 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
4278 
4293 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
4294  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
4295 
4304 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
4305  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
4306 
4307 
4333 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
4334  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
4335 
4361 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
4362 
4383 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
4384 
4406 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
4407 
4429 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
4430 
4436 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
4437 
4466 #if defined(RCC_HSI48_SUPPORT)
4467 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
4468  ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
4469  ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
4470  ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
4471  (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
4472 #else
4473 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
4474  ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
4475  ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
4476  (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U)
4477 #endif /* RCC_HSI48_SUPPORT */
4478 
4487 /* Private constants ---------------------------------------------------------*/
4491 /* Defines used for Flags */
4492 #define CR_REG_INDEX 1U
4493 #define BDCR_REG_INDEX 2U
4494 #define CSR_REG_INDEX 3U
4495 #if defined(RCC_HSI48_SUPPORT)
4496 #define CRRCR_REG_INDEX 4U
4497 #endif /* RCC_HSI48_SUPPORT */
4498 
4499 #define RCC_FLAG_MASK 0x1FU
4500 
4504 /* Private macros ------------------------------------------------------------*/
4509 #if defined(RCC_HSI48_SUPPORT)
4510 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
4511  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
4512  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
4513  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
4514  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
4515  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
4516  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
4517 #else
4518 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
4519  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
4520  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
4521  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
4522  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
4523  (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
4524 #endif /* RCC_HSI48_SUPPORT */
4525 
4526 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
4527  ((__HSE__) == RCC_HSE_BYPASS))
4528 
4529 #if defined(RCC_BDCR_LSESYSDIS)
4530 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \
4531  ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS))
4532 #else
4533 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
4534  ((__LSE__) == RCC_LSE_BYPASS))
4535 #endif /* RCC_BDCR_LSESYSDIS */
4536 
4537 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
4538 
4539 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
4540 
4541 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
4542 
4543 #if defined(RCC_CSR_LSIPREDIV)
4544 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
4545 #endif /* RCC_CSR_LSIPREDIV */
4546 
4547 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
4548 
4549 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
4550 
4551 #if defined(RCC_HSI48_SUPPORT)
4552 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
4553 #endif /* RCC_HSI48_SUPPORT */
4554 
4555 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
4556  ((__PLL__) == RCC_PLL_ON))
4557 
4558 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
4559  ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
4560  ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
4561  ((__SOURCE__) == RCC_PLLSOURCE_HSE))
4562 
4563 #if defined(RCC_PLLM_DIV_1_16_SUPPORT)
4564 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
4565 #else
4566 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
4567 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */
4568 
4569 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
4570 
4571 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
4572 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
4573 #else
4574 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
4575 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
4576 
4577 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
4578  ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
4579 
4580 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
4581  ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
4582 
4583 #if defined(RCC_PLLSAI1_SUPPORT)
4584 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
4585  (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
4586  (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
4587  (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
4588 #endif /* RCC_PLLSAI1_SUPPORT */
4589 
4590 #if defined(RCC_PLLSAI2_SUPPORT)
4591 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
4592 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
4593  (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
4594  (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
4595 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
4596 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
4597  (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \
4598  (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \
4599  (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U))
4600 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
4601 #endif /* RCC_PLLSAI2_SUPPORT */
4602 
4603 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
4604  ((__RANGE__) == RCC_MSIRANGE_1) || \
4605  ((__RANGE__) == RCC_MSIRANGE_2) || \
4606  ((__RANGE__) == RCC_MSIRANGE_3) || \
4607  ((__RANGE__) == RCC_MSIRANGE_4) || \
4608  ((__RANGE__) == RCC_MSIRANGE_5) || \
4609  ((__RANGE__) == RCC_MSIRANGE_6) || \
4610  ((__RANGE__) == RCC_MSIRANGE_7) || \
4611  ((__RANGE__) == RCC_MSIRANGE_8) || \
4612  ((__RANGE__) == RCC_MSIRANGE_9) || \
4613  ((__RANGE__) == RCC_MSIRANGE_10) || \
4614  ((__RANGE__) == RCC_MSIRANGE_11))
4615 
4616 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
4617  ((__RANGE__) == RCC_MSIRANGE_5) || \
4618  ((__RANGE__) == RCC_MSIRANGE_6) || \
4619  ((__RANGE__) == RCC_MSIRANGE_7))
4620 
4621 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
4622 
4623 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
4624  ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
4625  ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
4626  ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
4627 
4628 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
4629  ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
4630  ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
4631  ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
4632  ((__HCLK__) == RCC_SYSCLK_DIV512))
4633 
4634 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
4635  ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
4636  ((__PCLK__) == RCC_HCLK_DIV16))
4637 
4638 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
4639  ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
4640  ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
4641  ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
4642 
4643 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
4644 
4645 #if defined(RCC_HSI48_SUPPORT)
4646 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
4647  ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
4648  ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
4649  ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
4650  ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
4651  ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
4652  ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
4653  ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
4654  ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
4655 #else
4656 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
4657  ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
4658  ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
4659  ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
4660  ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
4661  ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
4662  ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
4663  ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
4664 #endif /* RCC_HSI48_SUPPORT */
4665 
4666 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
4667  ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
4668  ((__DIV__) == RCC_MCODIV_16))
4669 
4670 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
4671  ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
4672  ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
4673  ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
4674 
4675 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
4676  ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
4677 
4681 /* Include RCC HAL Extended module */
4682 #include "stm32l4xx_hal_rcc_ex.h"
4683 
4684 /* Exported functions --------------------------------------------------------*/
4694 /* Initialization and de-initialization functions ******************************/
4695 HAL_StatusTypeDef HAL_RCC_DeInit(void);
4696 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
4697 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
4698 
4707 /* Peripheral Control functions ************************************************/
4708 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
4709 void HAL_RCC_EnableCSS(void);
4710 uint32_t HAL_RCC_GetSysClockFreq(void);
4711 uint32_t HAL_RCC_GetHCLKFreq(void);
4712 uint32_t HAL_RCC_GetPCLK1Freq(void);
4713 uint32_t HAL_RCC_GetPCLK2Freq(void);
4714 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
4715 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
4716 /* CSS NMI IRQ handler */
4717 void HAL_RCC_NMI_IRQHandler(void);
4718 /* User Callbacks in non blocking mode (IT mode) */
4719 void HAL_RCC_CSSCallback(void);
4720 
4737 #ifdef __cplusplus
4738 }
4739 #endif
4740 
4741 #endif /* __STM32L4xx_HAL_RCC_H */
4742 
4743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32l4xx_hal_rcc.h:85
stm32l4xx_hal_rcc_ex.h
Header file of RCC HAL Extended module.
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
Configure the RCC_OscInitStruct according to the internal RCC configuration registers.
Definition: stm32l4xx_hal_rcc.c:1470
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32l4xx_hal_rcc.h:98
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
Handle the RCC Clock Security System interrupt request.
Definition: stm32l4xx_hal_rcc.c:1674
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
Reset the RCC clock configuration to the default reset state.
Definition: stm32l4xx_hal_rcc.c:264
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition...
Definition: stm32l4xx_hal_rcc.h:80
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
Return the PCLK2 frequency.
Definition: stm32l4xx_hal_rcc.c:1457
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Configure the RCC_ClkInitStruct according to the internal RCC configuration registers.
Definition: stm32l4xx_hal_rcc.c:1629
RCC_OscInitTypeDef::MSIClockRange
uint32_t MSIClockRange
Definition: stm32l4xx_hal_rcc.h:112
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32l4xx_hal_rcc.h:118
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
Definition: stm32l4xx_hal_rcc.c:401
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
RCC Clock Security System interrupt callback.
Definition: stm32l4xx_hal_rcc.c:1691
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32l4xx_hal_rcc.h:91
RCC_OscInitTypeDef::MSICalibrationValue
uint32_t MSICalibrationValue
Definition: stm32l4xx_hal_rcc.h:109
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32l4xx_hal_rcc.h:82
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkIni...
Definition: stm32l4xx_hal_rcc.c:1055
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32l4xx_hal_rcc.h:130
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Select the clock source to output on MCO pin(PA8).
Definition: stm32l4xx_hal_rcc.c:1287
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32l4xx_hal_rcc.h:139
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
Return the HCLK frequency.
Definition: stm32l4xx_hal_rcc.c:1434
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32l4xx_hal_rcc.h:125
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32l4xx_hal_rcc.h:136
RCC_OscInitTypeDef::LSIDiv
uint32_t LSIDiv
Definition: stm32l4xx_hal_rcc.h:102
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
Return the SYSCLK frequency.
Definition: stm32l4xx_hal_rcc.c:1346
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)
Enable the Clock Security System.
Definition: stm32l4xx_hal_rcc.c:1664
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32l4xx_hal_rcc.h:94
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32l4xx_hal_rcc.h:133
RCC_OscInitTypeDef::HSI48State
uint32_t HSI48State
Definition: stm32l4xx_hal_rcc.h:115
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32l4xx_hal_rcc.h:88
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
Return the PCLK1 frequency.
Definition: stm32l4xx_hal_rcc.c:1445
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32l4xx_hal_rcc.h:127
RCC_OscInitTypeDef::MSIState
uint32_t MSIState
Definition: stm32l4xx_hal_rcc.h:106