21 #ifndef STM32L4xx_HAL_TSC_H 22 #define STM32L4xx_HAL_TSC_H 117 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 133 #if defined(TSC_IOCCR_G5_IO1) 136 #if defined(TSC_IOCCR_G6_IO1) 139 #if defined(TSC_IOCCR_G7_IO1) 142 #if defined(TSC_IOCCR_G8_IO1) 148 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 182 #define HAL_TSC_ERROR_NONE 0x00000000UL 183 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 184 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL 193 #define TSC_CTPH_1CYCLE 0x00000000UL 194 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 195 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 196 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 197 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 198 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 199 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 200 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 201 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 202 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 203 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 204 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 205 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 206 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 207 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 208 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 216 #define TSC_CTPL_1CYCLE 0x00000000UL 217 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 218 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 219 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 220 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 221 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 222 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 223 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 224 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 225 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 226 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 227 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 228 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 229 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 230 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 231 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 239 #define TSC_SS_PRESC_DIV1 0x00000000UL 240 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC 248 #define TSC_PG_PRESC_DIV1 0x00000000UL 249 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 250 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 251 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) 252 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 253 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) 254 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) 255 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) 263 #define TSC_MCV_255 0x00000000UL 264 #define TSC_MCV_511 TSC_CR_MCV_0 265 #define TSC_MCV_1023 TSC_CR_MCV_1 266 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) 267 #define TSC_MCV_4095 TSC_CR_MCV_2 268 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) 269 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) 277 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL 278 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF 286 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL 287 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL 295 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 296 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 304 #define TSC_IT_EOA TSC_IER_EOAIE 305 #define TSC_IT_MCE TSC_IER_MCEIE 313 #define TSC_FLAG_EOA TSC_ISR_EOAF 314 #define TSC_FLAG_MCE TSC_ISR_MCEF 322 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 323 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 324 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 325 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 326 #if defined(TSC_IOCCR_G5_IO1) 327 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 329 #if defined(TSC_IOCCR_G6_IO1) 330 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 332 #if defined(TSC_IOCCR_G7_IO1) 333 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 335 #if defined(TSC_IOCCR_G8_IO1) 336 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 339 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL 341 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 342 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 343 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 344 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 346 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 347 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 348 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 349 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 351 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 352 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 353 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 354 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 356 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 357 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 358 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 359 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 360 #if defined(TSC_IOCCR_G5_IO1) 362 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 363 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 364 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 365 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 368 #define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) 369 #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 370 #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 371 #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 373 #if defined(TSC_IOCCR_G6_IO1) 375 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 376 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 377 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 378 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 381 #define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) 382 #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 383 #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 384 #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 386 #if defined(TSC_IOCCR_G7_IO1) 388 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 389 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 390 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 391 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 394 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) 395 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 396 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 397 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 399 #if defined(TSC_IOCCR_G8_IO1) 401 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 402 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 403 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 404 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 407 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) 408 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 409 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 410 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 430 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 431 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 432 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 433 (__HANDLE__)->MspInitCallback = NULL; \ 434 (__HANDLE__)->MspDeInitCallback = NULL; \ 437 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 445 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 452 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 459 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 466 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 473 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 480 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 487 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 494 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 502 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 510 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 517 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 525 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 533 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 541 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 549 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__))) 557 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__))) 565 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 573 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 581 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__))) 589 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 597 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 605 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 613 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 620 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 621 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 633 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 634 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 635 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 636 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 637 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 638 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 639 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 640 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 641 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 642 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 643 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 644 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 645 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 646 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 647 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 648 ((__VALUE__) == TSC_CTPH_16CYCLES)) 650 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 651 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 652 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 653 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 654 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 655 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 656 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 657 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 658 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 659 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 660 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 661 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 662 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 663 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 664 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 665 ((__VALUE__) == TSC_CTPL_16CYCLES)) 667 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) 669 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 671 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 673 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 674 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 675 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 676 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 677 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 678 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 679 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 680 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 682 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 683 ((__VALUE__) == TSC_MCV_511) || \ 684 ((__VALUE__) == TSC_MCV_1023) || \ 685 ((__VALUE__) == TSC_MCV_2047) || \ 686 ((__VALUE__) == TSC_MCV_4095) || \ 687 ((__VALUE__) == TSC_MCV_8191) || \ 688 ((__VALUE__) == TSC_MCV_16383)) 690 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 692 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 694 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 696 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) 698 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 701 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 702 ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 703 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 704 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 705 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 706 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 707 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 708 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 709 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 710 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 711 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 712 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 713 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 714 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 715 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 716 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 717 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 718 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 719 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 720 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 721 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 722 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 723 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 724 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 725 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 726 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 727 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 728 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 729 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 730 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 731 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 732 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 733 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 754 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice)
Discharge TSC IOs.
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc)
Deinitialize the TSC peripheral registers to their default reset values.
void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc)
Error callback in non-blocking mode.
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
Configure TSC IOs.
TSC IOs configuration structure definition.
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in interrupt mode.
__IO HAL_TSC_StateTypeDef State
void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc)
Initialize the TSC MSP.
This file contains HAL common defines, enumeration, macros and structures definitions.
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc)
Acquisition completed callback in non-blocking mode.
uint32_t SynchroPinPolarity
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc)
Start the acquisition.
void(* MspInitCallback)(struct __TSC_HandleTypeDef *htsc)
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc)
Return the TSC handle state.
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition status for a group.
uint32_t SpreadSpectrumDeviation
HAL_TSC_CallbackIDTypeDef
HAL TSC Callback ID enumeration definition.
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc)
Handle TSC interrupt request.
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
Get the acquisition measure for a group.
void(* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc)
FunctionalState MaxCountInterrupt
void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
DeInitialize the TSC MSP.
TSC handle Structure definition.
void(* pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc)
HAL TSC Callback pointer definition.
uint32_t CTPulseLowLength
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc)
Start acquisition and wait until completion.
uint32_t CTPulseHighLength
struct __TSC_HandleTypeDef TSC_HandleTypeDef
TSC handle Structure definition.
TSC init structure definition.
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc)
Stop the acquisition previously launched in polling mode.
HAL_LockTypeDef
HAL Lock structures definition.
FunctionalState SpreadSpectrum
HAL_TSC_StateTypeDef
TSC state structure definition.
void(* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc)
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
Register a User TSC Callback To be used instead of the weak predefined callback.
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
Initialize the TSC peripheral according to the specified parameters in the TSC_InitTypeDef structure ...
uint32_t PulseGeneratorPrescaler
HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
Unregister an TSC Callback TSC callback is redirected to the weak predefined callback.
TSC_GroupStatusTypeDef
TSC group status structure definition.
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc)
Start the acquisition in interrupt mode.
void(* ErrorCallback)(struct __TSC_HandleTypeDef *htsc)
uint32_t SpreadSpectrumPrescaler