STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_ll_dma2d.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_DMA2D_H
22 #define STM32L4xx_LL_DMA2D_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30 
35 #if defined (DMA2D)
36 
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 
53 #endif /*USE_FULL_LL_DRIVER*/
54 
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 
64 typedef struct
65 {
66  uint32_t Mode;
71  uint32_t ColorMode;
76  uint32_t OutputBlue;
86  uint32_t OutputGreen;
96  uint32_t OutputRed;
106  uint32_t OutputAlpha;
120 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
121  uint32_t OutputSwapMode;
125 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
126 
127 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
128  uint32_t LineOffsetMode;
132 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
133 
134  uint32_t LineOffset;
141  uint32_t NbrOfLines;
156  uint32_t RBSwapMode;
162 
166 typedef struct
167 {
168  uint32_t MemoryAddress;
175  uint32_t LineOffset;
182  uint32_t ColorMode;
189  uint32_t CLUTColorMode;
196  uint32_t CLUTSize;
203  uint32_t AlphaMode;
210  uint32_t Alpha;
217  uint32_t Blue;
224  uint32_t Green;
231  uint32_t Red;
238  uint32_t CLUTMemoryAddress;
252  uint32_t RBSwapMode;
261 
265 typedef struct
266 {
267  uint32_t ColorMode;
272  uint32_t OutputBlue;
282  uint32_t OutputGreen;
292  uint32_t OutputRed;
302  uint32_t OutputAlpha;
312 
316 #endif /* USE_FULL_LL_DRIVER */
317 
318 /* Exported constants --------------------------------------------------------*/
327 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF
328 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF
329 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF
330 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF
331 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF
332 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF
341 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE
342 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE
343 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE
344 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE
345 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE
346 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE
354 #define LL_DMA2D_MODE_M2M 0x00000000U
355 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0
356 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1
357 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1)
358 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
359 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2
360 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2)
361 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
362 
369 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U
370 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0
371 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1
372 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
373 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2
381 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U
382 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0
383 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1
384 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)
385 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2
386 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)
387 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
388 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)
389 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3
390 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)
391 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)
399 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U
400 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0
401 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1
407 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
408 
411 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U
412 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB
416 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
417 
421 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U
422 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS
430 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U
431 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI
437 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
438 
441 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U
442 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM
446 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
447 
451 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U
452 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM
462 /* Exported macro ------------------------------------------------------------*/
463 
478 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
479 
486 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
487 
495 /* Exported functions --------------------------------------------------------*/
510 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
511 {
512  SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
513 }
514 
521 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
522 {
523  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
524 }
525 
533 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
534 {
535  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
536 }
537 
545 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
546 {
547  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
548 }
549 
558 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
559 {
560  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
561 }
562 
570 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
571 {
572  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
573 }
574 
583 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
584 {
585  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
586 }
587 
603 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
604 {
605  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
606 }
607 
622 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
623 {
624  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
625 }
626 
639 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
640 {
641  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
642 }
643 
655 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
656 {
657  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
658 }
659 
669 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
670 {
671  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
672 }
673 
682 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
683 {
684  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
685 }
686 
696 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
697 {
698  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
699 }
700 
709 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
710 {
711  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
712 }
713 
714 
715 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
716 
725 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
726 {
727  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
728 }
729 
738 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
739 {
740  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
741 }
742 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
743 
744 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
745 
754 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
755 {
756  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
757 }
758 
767 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
768 {
769  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
770 }
771 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
772 
784 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
785 {
786  MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
787 }
788 
799 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
800 {
801  return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
802 }
803 
811 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
812 {
813  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
814 }
815 
822 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
823 {
824  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
825 }
826 
834 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
835 {
836  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
837 }
838 
845 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
846 {
847  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
848 }
849 
857 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
858 {
859  LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
860 }
861 
868 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
869 {
870  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
871 }
872 
887 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
888 {
889  MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
890  OutputColor);
891 }
892 
905 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
906 {
907  return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
908  (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
909 }
910 
918 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
919 {
920  MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
921 }
922 
929 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
930 {
931  return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
932 }
933 
941 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
942 {
943  MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
944 }
945 
952 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
953 {
954  return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
955 }
956 
963 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
964 {
965  SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
966 }
967 
974 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
975 {
976  CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
977 }
978 
985 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
986 {
987  return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
988 }
989 
1001 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1002 {
1003  LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1004 }
1005 
1012 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1013 {
1014  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1015 }
1016 
1023 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1024 {
1025  SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1026 }
1027 
1034 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1035 {
1036  return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1037 }
1038 
1057 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1058 {
1059  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1060 }
1061 
1079 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1080 {
1081  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1082 }
1083 
1094 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1095 {
1096  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1097 }
1098 
1108 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1109 {
1110  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1111 }
1112 
1120 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1121 {
1122  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1123 }
1124 
1131 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1132 {
1133  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1134 }
1135 
1145 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1146 {
1147  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1148 }
1149 
1158 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1159 {
1160  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1161 }
1162 
1172 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1173 {
1174  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1175 }
1176 
1185 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1186 {
1187  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1188 }
1189 
1197 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1198 {
1199  MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1200 }
1201 
1208 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1209 {
1210  return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1211 }
1212 
1224 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1225 {
1226  MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1227  ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1228 }
1229 
1237 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1238 {
1239  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1240 }
1241 
1248 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1249 {
1250  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1251 }
1252 
1260 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1261 {
1262  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1263 }
1264 
1271 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1272 {
1273  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1274 }
1275 
1283 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1284 {
1285  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1286 }
1287 
1294 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1295 {
1296  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1297 }
1298 
1306 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1307 {
1308  LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1309 }
1310 
1317 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1318 {
1319  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1320 }
1321 
1329 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1330 {
1331  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1332 }
1333 
1340 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1341 {
1342  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1343 }
1344 
1354 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1355 {
1356  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1357 }
1358 
1367 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1368 {
1369  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1370 }
1371 
1387 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1388 {
1389  LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1390 }
1391 
1398 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1399 {
1400  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1401 }
1402 
1409 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1410 {
1411  SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1412 }
1413 
1420 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1421 {
1422  return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1423 }
1424 
1443 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1444 {
1445  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1446 }
1447 
1465 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1466 {
1467  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1468 }
1469 
1480 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1481 {
1482  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1483 }
1484 
1494 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1495 {
1496  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1497 }
1498 
1506 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1507 {
1508  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1509 }
1510 
1517 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1518 {
1519  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1520 }
1521 
1531 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1532 {
1533  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1534 }
1535 
1544 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1545 {
1546  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1547 }
1548 
1558 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1559 {
1560  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1561 }
1562 
1571 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1572 {
1573  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1574 }
1575 
1583 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1584 {
1585  MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1586 }
1587 
1594 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1595 {
1596  return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1597 }
1598 
1610 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1611 {
1612  MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1613  ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1614 }
1615 
1623 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1624 {
1625  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1626 }
1627 
1634 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1635 {
1636  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1637 }
1638 
1646 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1647 {
1648  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1649 }
1650 
1657 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1658 {
1659  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1660 }
1661 
1669 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1670 {
1671  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1672 }
1673 
1680 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1681 {
1682  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1683 }
1684 
1692 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1693 {
1694  LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1695 }
1696 
1703 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1704 {
1705  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1706 }
1707 
1715 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1716 {
1717  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1718 }
1719 
1726 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1727 {
1728  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1729 }
1730 
1740 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1741 {
1742  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1743 }
1744 
1753 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1754 {
1755  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1756 }
1757 
1777 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1778 {
1779  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1780 }
1781 
1788 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1789 {
1790  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1791 }
1792 
1799 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1800 {
1801  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1802 }
1803 
1810 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1811 {
1812  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1813 }
1814 
1821 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1822 {
1823  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1824 }
1825 
1832 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1833 {
1834  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1835 }
1836 
1843 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1844 {
1845  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1846 }
1847 
1854 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1855 {
1856  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1857 }
1858 
1865 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1866 {
1867  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1868 }
1869 
1876 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1877 {
1878  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1879 }
1880 
1887 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1888 {
1889  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1890 }
1891 
1898 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1899 {
1900  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1901 }
1902 
1917 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1918 {
1919  SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1920 }
1921 
1928 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1929 {
1930  SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1931 }
1932 
1939 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1940 {
1941  SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1942 }
1943 
1950 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1951 {
1952  SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1953 }
1954 
1961 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1962 {
1963  SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1964 }
1965 
1972 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1973 {
1974  SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1975 }
1976 
1983 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1984 {
1985  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1986 }
1987 
1994 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1995 {
1996  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1997 }
1998 
2005 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2006 {
2007  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2008 }
2009 
2016 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2017 {
2018  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2019 }
2020 
2027 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2028 {
2029  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2030 }
2031 
2038 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2039 {
2040  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2041 }
2042 
2049 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2050 {
2051  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2052 }
2053 
2060 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2061 {
2062  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2063 }
2064 
2071 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2072 {
2073  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2074 }
2075 
2082 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2083 {
2084  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2085 }
2086 
2093 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2094 {
2095  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2096 }
2097 
2104 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2105 {
2106  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2107 }
2108 
2109 
2110 
2115 #if defined(USE_FULL_LL_DRIVER)
2116 
2120 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2121 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2122 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2123 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2125 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2126 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2127 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2128 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2129 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2130 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2131 
2135 #endif /* USE_FULL_LL_DRIVER */
2136 
2145 #endif /* defined (DMA2D) */
2146 
2151 #ifdef __cplusplus
2152 }
2153 #endif
2154 
2155 #endif /* STM32L4xx_LL_DMA2D_H */
2156 
2157 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D line offset, expressed on 14 bits ([13:0] bits). OOR LO LL_DMA2D_SetLineOffset.
__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). BGPFCCR ALPHA LL_DMA2D_BGND_SetA...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background color mode. BGPFCCR CM LL_DMA2D_BGND_GetColorMode.
void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
Configure the foreground or background according to the specified parameters in the LL_DMA2D_LayerCfg...
ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
De-initialize DMA2D registers (registers restored to their default values).
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). BGOR LO LL_DMA2D_BGND_GetLi...
__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D foreground alpha inversion mode. FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode.
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D line offset mode. CR LOM LL_DMA2D_GetLineOffsetMode.
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D dead time functionality is enabled. AMTCR EN LL_DMA2D_IsEnabledDeadTime.
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) NLR PL LL_DMA2D_GetNbrOf...
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Access Error Interrupt Flag is set or not ISR CAEIF LL_DMA2D_IsActiveFlag_CA...
__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D foreground Red Blue swap mode. FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode.
__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Error Interrupt Flag IFCR CTEIF LL_DMA2D_ClearFlag_TE.
__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
Enable CLUT Transfer Complete Interrupt CR CTCIE LL_DMA2D_EnableIT_CTC.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). FGCOLR GREEN LL_DMA2D_F...
uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Alpha color.
__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
Set DMA2D foreground alpha mode. FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode.
LL DMA2D Layer Configuration Structure Definition.
__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). OMAR MA LL_DMA2D_SetOutputMemAd...
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. CR CTCIE LL_DMA2D_IsEnabledIT_CTC.
__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). NLR PL LL_DMA2D_SetNbrOfPi...
__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
Disable Transfer Complete Interrupt CR TCIE LL_DMA2D_DisableIT_TC.
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Error interrupt source is enabled or disabled. CR TEIE LL_DMA2D_IsEnable...
void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Set each LL_DMA2D_InitTypeDef field to default value.
__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). FGOR LO LL_DMA2D_FGND_SetLineO...
__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D background Red Blue swap mode. BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground color mode. FGPFCCR CM LL_DMA2D_FGND_GetColorMode.
__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
Set DMA2D background color values, expressed on 24 bits ([23:0] bits). BGCOLR RED LL_DMA2D_BGND_SetC...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background CLUT color mode. BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode.
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Complete Interrupt Flag is set or not ISR TCIF LL_DMA2D_IsActiveFlag_TC...
__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). FGCOLR GREEN LL_DMA2D_FGND...
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not ISR CTCIF LL_DMA2D_IsActiveFl...
__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
Disable Transfer Error Interrupt CR TEIE LL_DMA2D_DisableIT_TE.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha inversion mode. FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). FGCMAR MA LL_DMA2D_FGN...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). BGPFCCR CS LL_DMA2D_BGND_GetCLUTSi...
__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). BGCMAR MA LL_DMA2D_BGN...
__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
Enable DMA2D foreground CLUT loading. FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad.
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). BGPFCCR ALPHA LL_DMA2D_BGND_G...
__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
Abort DMA2D transfer.
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D output Red Blue swap mode. OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode. ...
__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). FGPFCCR ALPHA LL_DMA2D_FGND_SetA...
__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
Set DMA2D output swap mode. OPFCCR SB LL_DMA2D_SetOutputSwapMode.
__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). FGCOLR BLUE LL_DMA2D_FGND_S...
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. CR CAEIE LL_DMA2D_IsEn...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). BGCOLR GREEN LL_DMA2D_B...
__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
Enable Configuration Error Interrupt CR CEIE LL_DMA2D_EnableIT_CE.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). FGPFCCR ALPHA LL_DMA2D_FGND_G...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). BGCOLR RED LL_DMA2D_BGND_...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background Red Blue swap mode. BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode.
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). BGMAR MA LL_DMA2D_BGND_GetM...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D background CLUT loading is enabled. BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad...
__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D mode CR MODE LL_DMA2D_GetMode.
__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
Start a DMA2D transfer. CR START LL_DMA2D_Start.
__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
Disable CLUT Transfer Complete Interrupt CR CTCIE LL_DMA2D_DisableIT_CTC.
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D output alpha inversion mode. OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). FGCOLR BLUE LL_DMA2D_FGN...
__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
Enable CLUT Access Error Interrupt CR CAEIE LL_DMA2D_EnableIT_CAE.
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D output swap mode. OPFCCR SB LL_DMA2D_GetOutputSwapMode.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground alpha mode. FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode.
__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). LWR LW LL_DMA2D_SetLineWatermark.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground CLUT color mode. FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode.
__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D background alpha inversion mode. BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode.
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
Indicate if a DMA2D transfer is ongoing. CR START LL_DMA2D_IsTransferOngoing.
__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
Enable DMA2D dead time functionality. AMTCR EN LL_DMA2D_EnableDeadTime.
__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
Set DMA2D output Red Blue swap mode. OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode.
ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Watermark Interrupt Flag is set or not ISR TWIF LL_DMA2D_IsActiveFlag_TW...
__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). LWR LW LL_DMA2D_GetLineWatermark.
void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
Initialize DMA2D output color register according to the specified parameters in DMA2D_ColorStruct.
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. CR TWIE LL_DMA2D_IsEn...
__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
Disable CLUT Access Error Interrupt CR CAEIE LL_DMA2D_DisableIT_CAE.
__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Complete Interrupt Flag IFCR CTCIF LL_DMA2D_ClearFlag_TC.
__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Transfer Watermark Interrupt Flag IFCR CTWIF LL_DMA2D_ClearFlag_TW.
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha mode. BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode.
__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
Enable Transfer Error Interrupt CR TEIE LL_DMA2D_EnableIT_TE.
__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
Disable Configuration Error Interrupt CR CEIE LL_DMA2D_DisableIT_CE.
__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
Clear DMA2D CLUT Access Error Interrupt Flag IFCR CAECIF LL_DMA2D_ClearFlag_CAE. ...
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Configuration Error interrupt source is enabled or disabled. CR CEIE LL_DMA2D_IsE...
__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). FGMAR MA LL_DMA2D_FGND_SetM...
LL DMA2D Init Structure Definition.
__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
Enable Transfer Complete Interrupt CR TCIE LL_DMA2D_EnableIT_TC.
__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
Set DMA2D background alpha mode. BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode.
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). NLR NL LL_DMA2D_GetNbrOfLines.
__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
Set DMA2D dead time, expressed on 8 bits ([7:0] bits). AMTCR DT LL_DMA2D_SetDeadTime.
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D transfer is aborted.
__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). BGCOLR GREEN LL_DMA2D_BGND...
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background alpha inversion mode. BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode.
uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Red color.
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D transfer is suspended.
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). BGCMAR MA LL_DMA2D_BGN...
__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
Set DMA2D output color, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). FGOR LO LL_DMA2D_FGND_GetLi...
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
Return DMA2D line offset, expressed on 14 bits ([13:0] bits). OOR LO LL_DMA2D_GetLineOffset.
__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). BGCOLR RED LL_DMA2D_BGND_Set...
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
Indicate if DMA2D foreground CLUT loading is enabled. FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad...
__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). FGCOLR RED LL_DMA2D_FGND_Set...
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). OMAR MA LL_DMA2D_GetOutputMemAd...
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. CR TCIE LL_DMA2D_IsEna...
__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
Disable DMA2D dead time functionality. AMTCR EN LL_DMA2D_DisableDeadTime.
void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
Configure DMA2D transfer size.
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). BGCOLR BLUE LL_DMA2D_BGN...
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Transfer Error Interrupt Flag is set or not ISR TEIF LL_DMA2D_IsActiveFlag_TE.
__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D output color mode. OPFCCR CM LL_DMA2D_SetOutputColorMode.
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
Get DMA2D output color, expressed on 32 bits ([31:0] bits).
__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
Suspend DMA2D transfer.
__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
Enable DMA2D background CLUT loading. BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). FGCOLR RED LL_DMA2D_FGND_...
__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D background color mode. BGPFCCR CM LL_DMA2D_BGND_SetColorMode.
__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). FGCOLR RED LL_DMA2D_FGND_SetC...
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)
__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). BGPFCCR CS LL_DMA2D_BGND_SetCLUTSi...
__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
Enable Transfer Watermark Interrupt CR TWIE LL_DMA2D_EnableIT_TW.
__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). BGOR LO LL_DMA2D_BGND_SetLineO...
LL DMA2D Output Color Structure Definition.
void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
Set each LL_DMA2D_LayerCfgTypeDef field to default value.
__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
Set DMA2D line offset mode. CR LOM LL_DMA2D_SetLineOffsetMode.
__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
Set DMA2D background CLUT color mode. BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode.
__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
Return DMA2D dead time, expressed on 8 bits ([7:0] bits). AMTCR DT LL_DMA2D_GetDeadTime.
__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
Clear DMA2D Configuration Error Interrupt Flag IFCR CCEIF LL_DMA2D_ClearFlag_CE. ...
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
Check if the DMA2D Configuration Error Interrupt Flag is set or not ISR CEIF LL_DMA2D_IsActiveFlag_C...
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). FGPFCCR CS LL_DMA2D_FGND_GetCLUTSi...
__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
Resume DMA2D transfer.
__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). FGCMAR MA LL_DMA2D_FGN...
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D output color mode. OPFCCR CM LL_DMA2D_GetOutputColorMode.
__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
Set DMA2D mode. CR MODE LL_DMA2D_SetMode.
uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Blue color.
__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). FGPFCCR CS LL_DMA2D_FGND_SetCLUTSi...
__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Set DMA2D foreground color mode. FGPFCCR CM LL_DMA2D_FGND_SetColorMode.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
Return DMA2D foreground Red Blue swap mode. FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode.
__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
Set DMA2D foreground CLUT color mode. FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode.
__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). BGMAR MA LL_DMA2D_BGND_SetM...
__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
Set DMA2D output alpha inversion mode. OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode. ...
__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
Clear DMA2D CLUT Transfer Complete Interrupt Flag IFCR CCTCIF LL_DMA2D_ClearFlag_CTC.
__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
Disable Transfer Watermark Interrupt CR TWIE LL_DMA2D_DisableIT_TW.
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). FGMAR MA LL_DMA2D_FGND_GetM...
__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). BGCOLR BLUE LL_DMA2D_BGND_S...
uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
Return DMA2D output Green color.
__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). NLR NL LL_DMA2D_SetNbrOfLines.