Configuration of ADC hierarchical scope: group injected

Functions
__STATIC_INLINE void	LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger source internal (SW start) or external. More...
__STATIC_INLINE void	LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Set ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger. More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger. JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge. More...
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group injected sequencer length and scan direction. More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
	Get ADC group injected sequencer length and scan direction. More...
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
	Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont. More...
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group injected sequence: channel on the selected sequence rank. More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected sequence: channel on the selected sequence rank. More...
__STATIC_INLINE void	LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
	Set ADC group injected conversion trigger: independent or from ADC group regular. More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger: independent or from ADC group regular. CFGR JAUTO LL_ADC_INJ_GetTrigAuto. More...
__STATIC_INLINE void	LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
	Set ADC group injected contexts queue mode. More...
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
	Get ADC group injected context queue mode. CFGR JQM LL_ADC_INJ_GetQueueMode CFGR JQDIS LL_ADC_INJ_GetQueueMode. More...
__STATIC_INLINE void	LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
	Set one context on ADC group injected that will be checked in contexts queue. More...

Detailed Description

Function Documentation

LL_ADC_INJ_ConfigQueueContext()

__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext	(	ADC_TypeDef *	ADCx,
		uint32_t	TriggerSource,
		uint32_t	ExternalTriggerEdge,
		uint32_t	SequencerNbRanks,
		uint32_t	Rank1_Channel,
		uint32_t	Rank2_Channel,
		uint32_t	Rank3_Channel,
		uint32_t	Rank4_Channel
	)

Set one context on ADC group injected that will be checked in contexts queue.

Note

A context is a setting of group injected sequencer:

• group injected trigger
• sequencer length
• sequencer ranks This function is intended to be used when contexts queue is enabled, because the sequence must be fully configured in one time (functions to set separately injected trigger and sequencer channels cannot be used): Refer to function LL_ADC_INJ_SetQueueMode().

In the contexts queue, only the active context can be read. The parameters of this function can be read using functions:

• LL_ADC_INJ_GetTriggerSource()
• LL_ADC_INJ_GetTriggerEdge()
• LL_ADC_INJ_GetSequencerRanks()

On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().

On STM32L4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected. JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
JSQR JL LL_ADC_INJ_ConfigQueueContext
JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext

Parameters

ADCx	ADC instance
TriggerSource	This parameter can be one of the following values: LL_ADC_INJ_TRIG_SOFTWARE LL_ADC_INJ_TRIG_EXT_TIM1_TRGO LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 LL_ADC_INJ_TRIG_EXT_TIM1_CH4 LL_ADC_INJ_TRIG_EXT_TIM2_TRGO LL_ADC_INJ_TRIG_EXT_TIM2_CH1 LL_ADC_INJ_TRIG_EXT_TIM3_TRGO LL_ADC_INJ_TRIG_EXT_TIM3_CH1 LL_ADC_INJ_TRIG_EXT_TIM3_CH3 LL_ADC_INJ_TRIG_EXT_TIM3_CH4 LL_ADC_INJ_TRIG_EXT_TIM4_TRGO LL_ADC_INJ_TRIG_EXT_TIM6_TRGO LL_ADC_INJ_TRIG_EXT_TIM8_CH4 LL_ADC_INJ_TRIG_EXT_TIM8_TRGO LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 LL_ADC_INJ_TRIG_EXT_TIM15_TRGO LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
ExternalTriggerEdge	This parameter can be one of the following values: LL_ADC_INJ_TRIG_EXT_RISING LL_ADC_INJ_TRIG_EXT_FALLING LL_ADC_INJ_TRIG_EXT_RISINGFALLING Note: This parameter is discarded in case of SW start: parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
SequencerNbRanks	This parameter can be one of the following values: LL_ADC_INJ_SEQ_SCAN_DISABLE LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Rank1_Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (7) LL_ADC_CHANNEL_2 (7) LL_ADC_CHANNEL_3 (7) LL_ADC_CHANNEL_4 (7) LL_ADC_CHANNEL_5 (7) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1 (5) LL_ADC_CHANNEL_DAC1CH2 (5) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance. (6) On STM32L4, parameter available on devices with several ADC instances. (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank2_Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (7) LL_ADC_CHANNEL_2 (7) LL_ADC_CHANNEL_3 (7) LL_ADC_CHANNEL_4 (7) LL_ADC_CHANNEL_5 (7) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1 (5) LL_ADC_CHANNEL_DAC1CH2 (5) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance. (6) On STM32L4, parameter available on devices with several ADC instances. (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank3_Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (7) LL_ADC_CHANNEL_2 (7) LL_ADC_CHANNEL_3 (7) LL_ADC_CHANNEL_4 (7) LL_ADC_CHANNEL_5 (7) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1 (5) LL_ADC_CHANNEL_DAC1CH2 (5) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance. (6) On STM32L4, parameter available on devices with several ADC instances. (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
Rank4_Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (7) LL_ADC_CHANNEL_2 (7) LL_ADC_CHANNEL_3 (7) LL_ADC_CHANNEL_4 (7) LL_ADC_CHANNEL_5 (7) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1 (5) LL_ADC_CHANNEL_DAC1CH2 (5) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance. (6) On STM32L4, parameter available on devices with several ADC instances. (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

Return values

None

Definition at line 4501 of file stm32l4xx_ll_adc.h.

{
  /* Set bits with content of parameter "Rankx_Channel" with bits position    */
  /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
  /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
  /* because containing other bits reserved for other purpose.                */
  /* If parameter "TriggerSource" is set to SW start, then parameter          */
  /* "ExternalTriggerEdge" is discarded.                                      */
  register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
  MODIFY_REG(ADCx->JSQR,
             ADC_JSQR_JEXTSEL |
             ADC_JSQR_JEXTEN  |
             ADC_JSQR_JSQ4    |
             ADC_JSQR_JSQ3    |
             ADC_JSQR_JSQ2    |
             ADC_JSQR_JSQ1    |
             ADC_JSQR_JL,
             (TriggerSource & ADC_JSQR_JEXTSEL)          |
             (ExternalTriggerEdge * (is_trigger_not_sw)) |
             (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
             SequencerNbRanks
            );
}

LL_ADC_INJ_GetQueueMode()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode

(

ADC_TypeDef *

ADCx

)

Get ADC group injected context queue mode. CFGR JQM LL_ADC_INJ_GetQueueMode
CFGR JQDIS LL_ADC_INJ_GetQueueMode.

Parameters

ADCx	ADC instance

Return values

Returned

value can be one of the following values: LL_ADC_INJ_QUEUE_DISABLE LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

Definition at line 4277 of file stm32l4xx_ll_adc.h.

{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
}

LL_ADC_INJ_GetSequencerDiscont()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont

(

ADC_TypeDef *

ADCx

)

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont.

Parameters

ADCx	ADC instance

Return values

Returned

value can be one of the following values: LL_ADC_INJ_SEQ_DISCONT_DISABLE LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 4015 of file stm32l4xx_ll_adc.h.

{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
}

LL_ADC_INJ_GetSequencerLength()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength

(

ADC_TypeDef *

ADCx

)

Get ADC group injected sequencer length and scan direction.

Note

This function retrieves:

• Sequence length: Number of ranks in the scan sequence.
• Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).

Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel. JSQR JL LL_ADC_INJ_GetSequencerLength

Parameters

ADCx	ADC instance

Return values

Returned

value can be one of the following values: LL_ADC_INJ_SEQ_SCAN_DISABLE LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 3982 of file stm32l4xx_ll_adc.h.

{
  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
}

LL_ADC_INJ_GetSequencerRanks()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks	(	ADC_TypeDef *	ADCx,
		uint32_t	Rank
	)

Get ADC group injected sequence: channel on the selected sequence rank.

Note

Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.

Usage of the returned channel number:

• To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
• To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
  JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
  JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
  JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks

Parameters

ADCx	ADC instance
Rank	This parameter can be one of the following values: LL_ADC_INJ_RANK_1 LL_ADC_INJ_RANK_2 LL_ADC_INJ_RANK_3 LL_ADC_INJ_RANK_4

Return values

Returned

value can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (7) LL_ADC_CHANNEL_2 (7) LL_ADC_CHANNEL_3 (7) LL_ADC_CHANNEL_4 (7) LL_ADC_CHANNEL_5 (7) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1 (5) LL_ADC_CHANNEL_DAC1CH2 (5) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance. (6) On STM32L4, parameter available on devices with several ADC instances. (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). (1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 4164 of file stm32l4xx_ll_adc.h.

{
  return (uint32_t)((READ_BIT(ADCx->JSQR,
                              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
                   );
}

LL_ADC_INJ_GetTrigAuto()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto

(

ADC_TypeDef *

ADCx

)

Get ADC group injected conversion trigger: independent or from ADC group regular. CFGR JAUTO LL_ADC_INJ_GetTrigAuto.

Parameters

ADCx	ADC instance

Return values

Returned

value can be one of the following values: LL_ADC_INJ_TRIG_INDEPENDENT LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 4216 of file stm32l4xx_ll_adc.h.

{
  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
}

LL_ADC_INJ_GetTriggerEdge()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge

(

ADC_TypeDef *

ADCx

)

Get ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger. JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge.

Parameters

ADCx	ADC instance

Return values

Returned

value can be one of the following values: LL_ADC_INJ_TRIG_EXT_RISING LL_ADC_INJ_TRIG_EXT_FALLING LL_ADC_INJ_TRIG_EXT_RISINGFALLING

Definition at line 3935 of file stm32l4xx_ll_adc.h.

{
  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
}

LL_ADC_INJ_GetTriggerSource()

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource

(

ADC_TypeDef *

ADCx

)

Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note

To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.

Availability of parameters of trigger sources from timer depends on timers availability on the selected device. JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
JSQR JEXTEN LL_ADC_INJ_GetTriggerSource

Parameters

ADCx	ADC instance

Return values

Returned

value can be one of the following values: LL_ADC_INJ_TRIG_SOFTWARE LL_ADC_INJ_TRIG_EXT_TIM1_TRGO LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 LL_ADC_INJ_TRIG_EXT_TIM1_CH4 LL_ADC_INJ_TRIG_EXT_TIM2_TRGO LL_ADC_INJ_TRIG_EXT_TIM2_CH1 LL_ADC_INJ_TRIG_EXT_TIM3_TRGO LL_ADC_INJ_TRIG_EXT_TIM3_CH1 LL_ADC_INJ_TRIG_EXT_TIM3_CH3 LL_ADC_INJ_TRIG_EXT_TIM3_CH4 LL_ADC_INJ_TRIG_EXT_TIM4_TRGO LL_ADC_INJ_TRIG_EXT_TIM6_TRGO LL_ADC_INJ_TRIG_EXT_TIM8_CH4 LL_ADC_INJ_TRIG_EXT_TIM8_TRGO LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 LL_ADC_INJ_TRIG_EXT_TIM15_TRGO LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

Definition at line 3873 of file stm32l4xx_ll_adc.h.

{
  register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);

  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
  register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));

  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
  /* to match with triggers literals definition.                              */
  return ((TriggerSource
           & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
          | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
         );
}

LL_ADC_INJ_IsTriggerSourceSWStart()

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart

(

ADC_TypeDef *

ADCx

)

Get ADC group injected conversion trigger source internal (SW start) or external.

Note

In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource. JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart

Parameters

ADCx	ADC instance

Return values

Value

"0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 3900 of file stm32l4xx_ll_adc.h.

{
  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
}

LL_ADC_INJ_SetQueueMode()

__STATIC_INLINE void LL_ADC_INJ_SetQueueMode	(	ADC_TypeDef *	ADCx,
		uint32_t	QueueMode
	)

Set ADC group injected contexts queue mode.

Note

A context is a setting of group injected sequencer:

• group injected trigger
• sequencer length
• sequencer ranks If contexts queue is disabled:
• only 1 sequence can be configured and is active perpetually. If contexts queue is enabled:
• up to 2 contexts can be queued and are checked in and out as a FIFO stack (first-in, first-out).
• If a new context is set when queues is full, error is triggered by interruption "Injected Queue Overflow".
• Two behaviors are possible when all contexts have been processed: the contexts queue can maintain the last context active perpetually or can be empty and injected group triggers are disabled.
• Triggers can be only external (not internal SW start)
• Caution: The sequence must be fully configured in one time (one write of register JSQR makes a check-in of a new context into the queue). Therefore functions to set separately injected trigger and sequencer channels cannot be used, register JSQR must be set using function LL_ADC_INJ_ConfigQueueContext().

This parameter can be modified only when no conversion is on going on either groups regular or injected.

A modification of the context mode (bit JQDIS) causes the contexts queue to be flushed and the register JSQR is cleared.

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected. CFGR JQM LL_ADC_INJ_SetQueueMode
CFGR JQDIS LL_ADC_INJ_SetQueueMode

Parameters

ADCx	ADC instance
QueueMode	This parameter can be one of the following values: LL_ADC_INJ_QUEUE_DISABLE LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

Return values

None

Definition at line 4262 of file stm32l4xx_ll_adc.h.

{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
}

LL_ADC_INJ_SetSequencerDiscont()

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont	(	ADC_TypeDef *	ADCx,
		uint32_t	SeqDiscont
	)

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note

It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode. CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont

Parameters

ADCx	ADC instance
SeqDiscont	This parameter can be one of the following values: LL_ADC_INJ_SEQ_DISCONT_DISABLE LL_ADC_INJ_SEQ_DISCONT_1RANK

Return values

None

Definition at line 4000 of file stm32l4xx_ll_adc.h.

{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
}

LL_ADC_INJ_SetSequencerLength()

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength	(	ADC_TypeDef *	ADCx,
		uint32_t	SequencerNbRanks
	)

Set ADC group injected sequencer length and scan direction.

Note

This function performs configuration of:

• Sequence length: Number of ranks in the scan sequence.
• Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).

Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected. JSQR JL LL_ADC_INJ_SetSequencerLength

Parameters

ADCx	ADC instance
SequencerNbRanks	This parameter can be one of the following values: LL_ADC_INJ_SEQ_SCAN_DISABLE LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Return values

None

Definition at line 3961 of file stm32l4xx_ll_adc.h.

{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
}

LL_ADC_INJ_SetSequencerRanks()

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks	(	ADC_TypeDef *	ADCx,
		uint32_t	Rank,
		uint32_t	Channel
	)

Set ADC group injected sequence: channel on the selected sequence rank.

Note

Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.

On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().

On STM32L4, some fast channels are available: fast analog inputs coming from GPIO pads (ADC_IN1..5).

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected. JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks

Parameters

ADCx	ADC instance
Rank	This parameter can be one of the following values: LL_ADC_INJ_RANK_1 LL_ADC_INJ_RANK_2 LL_ADC_INJ_RANK_3 LL_ADC_INJ_RANK_4
Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (7) LL_ADC_CHANNEL_2 (7) LL_ADC_CHANNEL_3 (7) LL_ADC_CHANNEL_4 (7) LL_ADC_CHANNEL_5 (7) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1 (5) LL_ADC_CHANNEL_DAC1CH2 (5) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, parameter available on devices with only 1 ADC instance. (6) On STM32L4, parameter available on devices with several ADC instances. (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

Return values

None

Definition at line 4085 of file stm32l4xx_ll_adc.h.

{
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register depending on parameter "Rank".                               */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  MODIFY_REG(ADCx->JSQR,
             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
}

LL_ADC_INJ_SetTrigAuto()

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto	(	ADC_TypeDef *	ADCx,
		uint32_t	TrigAuto
	)

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note

This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.

If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected. CFGR JAUTO LL_ADC_INJ_SetTrigAuto

Parameters

ADCx	ADC instance
TrigAuto	This parameter can be one of the following values: LL_ADC_INJ_TRIG_INDEPENDENT LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Return values

None

Definition at line 4202 of file stm32l4xx_ll_adc.h.

{
  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
}

LL_ADC_INJ_SetTriggerEdge()

__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge	(	ADC_TypeDef *	ADCx,
		uint32_t	ExternalTriggerEdge
	)

Set ADC group injected conversion trigger polarity. Applicable only for trigger source set to external trigger.

Note

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected. JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge

Parameters

ADCx	ADC instance
ExternalTriggerEdge	This parameter can be one of the following values: LL_ADC_INJ_TRIG_EXT_RISING LL_ADC_INJ_TRIG_EXT_FALLING LL_ADC_INJ_TRIG_EXT_RISINGFALLING

Return values

None

Definition at line 3920 of file stm32l4xx_ll_adc.h.

{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
}

LL_ADC_INJ_SetTriggerSource()

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource	(	ADC_TypeDef *	ADCx,
		uint32_t	TriggerSource
	)

Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

Note

On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_INJ_SetTriggerEdge().

Availability of parameters of trigger sources from timer depends on timers availability on the selected device.

On this STM32 serie, setting of this feature is conditioned to ADC state: ADC must not be disabled. Can be enabled with or without conversion on going on either groups regular or injected. JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
JSQR JEXTEN LL_ADC_INJ_SetTriggerSource

Parameters

ADCx

ADC instance

TriggerSource

This parameter can be one of the following values: LL_ADC_INJ_TRIG_SOFTWARE LL_ADC_INJ_TRIG_EXT_TIM1_TRGO LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 LL_ADC_INJ_TRIG_EXT_TIM1_CH4 LL_ADC_INJ_TRIG_EXT_TIM2_TRGO LL_ADC_INJ_TRIG_EXT_TIM2_CH1 LL_ADC_INJ_TRIG_EXT_TIM3_TRGO LL_ADC_INJ_TRIG_EXT_TIM3_CH1 LL_ADC_INJ_TRIG_EXT_TIM3_CH3 LL_ADC_INJ_TRIG_EXT_TIM3_CH4 LL_ADC_INJ_TRIG_EXT_TIM4_TRGO LL_ADC_INJ_TRIG_EXT_TIM6_TRGO LL_ADC_INJ_TRIG_EXT_TIM8_CH4 LL_ADC_INJ_TRIG_EXT_TIM8_TRGO LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 LL_ADC_INJ_TRIG_EXT_TIM15_TRGO LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

Return values

None

Definition at line 3834 of file stm32l4xx_ll_adc.h.

{
  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
}