STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_ll_adc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_ADC_H
22 #define STM32L4xx_LL_ADC_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30 
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36 
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 
44 /* Private constants ---------------------------------------------------------*/
49 /* Internal mask for ADC group regular sequencer: */
50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
51 /* - sequencer register offset */
52 /* - sequencer rank bits position into the selected register */
53 
54 /* Internal register offset for ADC group regular sequencer configuration */
55 /* (offset placed into a spare area of literal definition) */
56 #define ADC_SQR1_REGOFFSET (0x00000000UL)
57 #define ADC_SQR2_REGOFFSET (0x00000100UL)
58 #define ADC_SQR3_REGOFFSET (0x00000200UL)
59 #define ADC_SQR4_REGOFFSET (0x00000300UL)
60 
61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64 
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
83 
84 
85 
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90 
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97 
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
99 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
100 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
101 
102 /* Definition of ADC group injected sequencer bits information to be inserted */
103 /* into ADC group injected sequencer ranks literals definition. */
104 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
105 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
106 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
107 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
108 
109 
110 
111 /* Internal mask for ADC group regular trigger: */
112 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
113 /* - regular trigger source */
114 /* - regular trigger edge */
115 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
116 
117 /* Mask containing trigger source masks for each of possible */
118 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
119 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
120 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
121  ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
122  ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
123  ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
124 
125 /* Mask containing trigger edge masks for each of possible */
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
127 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
128 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
129  ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
130  ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
131  ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
132 
133 /* Definition of ADC group regular trigger bits information. */
134 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
135 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
136 
137 
138 
139 /* Internal mask for ADC group injected trigger: */
140 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
141 /* - injected trigger source */
142 /* - injected trigger edge */
143 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
144 
145 /* Mask containing trigger source masks for each of possible */
146 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
147 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
148 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
149  ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
150  ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
151  ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
152 
153 /* Mask containing trigger edge masks for each of possible */
154 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
155 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
156 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
157  ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
158  ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
159  ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
160 
161 /* Definition of ADC group injected trigger bits information. */
162 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
163 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
164 
165 
166 
167 
168 
169 
170 /* Internal mask for ADC channel: */
171 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
172 /* - channel identifier defined by number */
173 /* - channel identifier defined by bitfield */
174 /* - channel differentiation between external channels (connected to */
175 /* GPIO pins) and internal channels (connected to internal paths) */
176 /* - channel sampling time defined by SMPRx register offset */
177 /* and SMPx bits positions into SMPRx register */
178 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
179 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
180 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
181 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
182 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
183 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
184 
185 /* Channel differentiation between external and internal channels */
186 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
187 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
188 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
189 
190 /* Internal register offset for ADC channel sampling time configuration */
191 /* (offset placed into a spare area of literal definition) */
192 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
193 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
194 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
195 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
196 
197 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
198 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
199 
200 /* Definition of channels ID number information to be inserted into */
201 /* channels literals definition. */
202 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
203 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
204 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
205 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
206 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
207 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
208 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
209 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
210 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
211 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
212 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
213 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
214 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
215 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
217 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
219 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
221 
222 /* Definition of channels ID bitfield information to be inserted into */
223 /* channels literals definition. */
224 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
225 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
226 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
227 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
228 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
229 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
230 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
231 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
232 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
233 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
234 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
235 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
236 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
237 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
238 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
239 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
240 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
241 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
242 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
243 
244 /* Definition of channels sampling time information to be inserted into */
245 /* channels literals definition. */
246 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
247 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
248 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
249 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
250 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
251 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
252 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
253 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
254 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
255 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
256 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
257 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
258 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
259 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
260 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
261 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
262 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
263 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
264 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
265 
266 
267 /* Internal mask for ADC mode single or differential ended: */
268 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
269 /* the relevant bits for: */
270 /* (concatenation of multiple bits used in different registers) */
271 /* - ADC calibration: calibration start, calibration factor get or set */
272 /* - ADC channels: set each ADC channel ending mode */
273 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
274 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
275 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
276 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
277 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
278 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
279 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
280 
281 /* Internal mask for ADC analog watchdog: */
282 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
283 /* (concatenation of multiple bits used in different analog watchdogs, */
284 /* (feature of several watchdogs not available on all STM32 families)). */
285 /* - analog watchdog 1: monitored channel defined by number, */
286 /* selection of ADC group (ADC groups regular and-or injected). */
287 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
288 /* selection on groups. */
289 
290 /* Internal register offset for ADC analog watchdog channel configuration */
291 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
292 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
293 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
294 
295 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
296 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
297 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
298 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
299 
300 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
301 
302 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
303 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
304 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
305 
306 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
307 
308 /* Internal register offset for ADC analog watchdog threshold configuration */
309 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
310 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
311 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
312 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
313 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
314 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
315 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
316 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
317 
318 /* Internal mask for ADC offset: */
319 /* Internal register offset for ADC offset number configuration */
320 #define ADC_OFR1_REGOFFSET (0x00000000UL)
321 #define ADC_OFR2_REGOFFSET (0x00000001UL)
322 #define ADC_OFR3_REGOFFSET (0x00000002UL)
323 #define ADC_OFR4_REGOFFSET (0x00000003UL)
324 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
325 
326 
327 /* ADC registers bits positions */
328 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
329 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
330 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
331 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
332 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
333 
334 
335 /* ADC registers bits groups */
336 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
337 
338 
339 /* ADC internal channels related definitions */
340 /* Internal voltage reference VrefInt */
341 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
342 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
343 /* Temperature sensor */
344 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
345 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
346 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
347 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
348 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
349 #else
350 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
351 #endif
352 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
353 
354 
360 /* Private macros ------------------------------------------------------------*/
373 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
374  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
375 
381 /* Exported types ------------------------------------------------------------*/
382 #if defined(USE_FULL_LL_DRIVER)
383 
397 typedef struct
398 {
399  uint32_t CommonClock;
407 #if defined(ADC_MULTIMODE_SUPPORT)
408  uint32_t Multimode;
413  uint32_t MultiDMATransfer;
418  uint32_t MultiTwoSamplingDelay;
422 #endif /* ADC_MULTIMODE_SUPPORT */
423 
424 } LL_ADC_CommonInitTypeDef;
425 
446 typedef struct
447 {
448  uint32_t Resolution;
453  uint32_t DataAlignment;
458  uint32_t LowPowerMode;
463 } LL_ADC_InitTypeDef;
464 
484 typedef struct
485 {
486  uint32_t TriggerSource;
494  uint32_t SequencerLength;
499  uint32_t SequencerDiscont;
506  uint32_t ContinuousMode;
512  uint32_t DMATransfer;
517  uint32_t Overrun;
523 } LL_ADC_REG_InitTypeDef;
524 
544 typedef struct
545 {
546  uint32_t TriggerSource;
554  uint32_t SequencerLength;
559  uint32_t SequencerDiscont;
566  uint32_t TrigAuto;
572 } LL_ADC_INJ_InitTypeDef;
573 
577 #endif /* USE_FULL_LL_DRIVER */
578 
579 /* Exported constants --------------------------------------------------------*/
588 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
589 #define LL_ADC_FLAG_EOC ADC_ISR_EOC
590 #define LL_ADC_FLAG_EOS ADC_ISR_EOS
591 #define LL_ADC_FLAG_OVR ADC_ISR_OVR
592 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
593 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC
594 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS
595 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
596 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
597 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
598 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
599 #if defined(ADC_MULTIMODE_SUPPORT)
600 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
601 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
602 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
603 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
604 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
605 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
606 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
607 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
608 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
609 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
610 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
611 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
612 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
613 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
614 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
615 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
616 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
617 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
618 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
619 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
620 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
621 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
622 #endif
623 
631 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
632 #define LL_ADC_IT_EOC ADC_IER_EOCIE
633 #define LL_ADC_IT_EOS ADC_IER_EOSIE
634 #define LL_ADC_IT_OVR ADC_IER_OVRIE
635 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
636 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE
637 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE
638 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
639 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE
640 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE
641 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE
649 /* List of ADC registers intended to be used (most commonly) with */
650 /* DMA transfer. */
651 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
652 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
653 #if defined(ADC_MULTIMODE_SUPPORT)
654 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
655 #endif
656 
663 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
664 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
665 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)
666 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL)
667 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
668 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
669 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
670 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
671 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)
672 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 )
673 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
674 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
675 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)
676 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)
677 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)
685 /* Note: Other measurement paths to internal channels may be available */
686 /* (connections to other peripherals). */
687 /* If they are not listed below, they do not require any specific */
688 /* path enable. In this case, Access to measurement path is done */
689 /* only by selecting the corresponding ADC internal channel. */
690 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL)
691 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
692 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
693 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
701 #define LL_ADC_RESOLUTION_12B (0x00000000UL)
702 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
703 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
704 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)
712 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL)
713 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)
721 #define LL_ADC_LP_MODE_NONE (0x00000000UL)
722 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
730 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
731 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
732 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
733 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
741 #define LL_ADC_OFFSET_DISABLE (0x00000000UL)
742 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)
750 #define LL_ADC_GROUP_REGULAR (0x00000001UL)
751 #define LL_ADC_GROUP_INJECTED (0x00000002UL)
752 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL)
760 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD )
761 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD )
762 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD )
763 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD )
764 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD )
765 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD )
766 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD )
767 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD )
768 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD )
769 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD )
770 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD)
771 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD)
772 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD)
773 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD)
774 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD)
775 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD)
776 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD)
777 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD)
778 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD)
779 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH)
780 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
781 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
782 #if defined(ADC1) && !defined(ADC2)
783 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
784 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
785 #elif defined(ADC2)
786 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
787 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
788 #if defined(ADC3)
789 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH)
790 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)
791 #endif
792 #endif
793 
800 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL)
801 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
802 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
803 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
804 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
805 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
806 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
807 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
808 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
809 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
810 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
811 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
812 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
813 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
814 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
815 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
816 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
824 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
825 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
826 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)
834 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL)
835 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
843 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL)
844 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)
845 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)
850 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
851 
854 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL)
855 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG)
859 #endif
860 
861 #if defined(ADC_SMPR1_SMPPLUS)
862 
865 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL)
866 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS)
870 #endif
871 
875 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL)
876 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
884 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL)
885 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
886 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
887 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
888 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
889 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
890 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
891 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
892 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
893 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
894 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
895 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
896 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
897 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
898 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
899 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
907 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL)
908 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
909 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
910 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
911 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
912 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)
913 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
914 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)
915 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)
923 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
924 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
925 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
926 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
927 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
928 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
929 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
930 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
931 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
932 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
933 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
934 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
935 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
936 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
937 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
938 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
946 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL)
947 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
948 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
949 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
950 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
951 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
952 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
953 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
954 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
955 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
956 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
957 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
958 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
959 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
960 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
961 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
962 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
970 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
971 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
972 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0)
980 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL)
981 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
989 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
990 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
991 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
992 
999 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL)
1000 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
1001 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
1002 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
1010 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL)
1011 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
1019 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
1020 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
1021 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
1022 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
1030 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL)
1031 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
1032 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
1033 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1034 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
1035 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)
1036 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 )
1037 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)
1045 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
1046 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)
1047 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED)
1055 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
1056 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET)
1057 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET)
1065 #define LL_ADC_AWD_DISABLE (0x00000000UL)
1066 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN )
1067 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN )
1068 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN )
1069 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1070 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1071 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1072 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1073 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1074 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1075 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1076 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1077 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1078 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1079 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1080 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1081 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1082 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1083 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1084 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1085 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1086 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1087 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1088 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1089 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1090 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1091 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1092 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1093 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1094 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1095 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1096 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1097 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1098 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1099 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1100 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1101 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1102 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1103 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1104 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1105 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1106 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1107 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1108 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1109 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1110 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1111 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1112 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1113 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1114 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1115 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1116 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1117 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1118 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1119 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1120 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1121 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1122 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1123 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1124 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1125 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1126 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1127 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1128 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1129 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1130 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1131 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1132 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1133 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1134 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1135 #if defined(ADC1) && !defined(ADC2)
1136 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1137 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1138 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1139 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1140 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1141 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1142 #elif defined(ADC2)
1143 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1144 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1145 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1146 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1147 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1148 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1149 #if defined(ADC3)
1150 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1151 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1152 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1153 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1154 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)
1155 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
1156 #endif
1157 #endif
1158 
1165 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )
1166 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)
1167 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1)
1175 #define LL_ADC_OVS_DISABLE (0x00000000UL)
1176 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
1177 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE)
1178 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
1179 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
1187 #define LL_ADC_OVS_REG_CONT (0x00000000UL)
1188 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
1196 #define LL_ADC_OVS_RATIO_2 (0x00000000UL)
1197 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
1198 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
1199 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
1200 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
1201 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)
1202 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 )
1203 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)
1211 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL)
1212 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
1213 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
1214 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1215 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
1216 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)
1217 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 )
1218 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)
1219 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
1224 #if defined(ADC_MULTIMODE_SUPPORT)
1225 
1228 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL)
1229 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 )
1230 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
1231 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)
1232 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)
1233 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
1234 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
1235 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)
1243 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL)
1244 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 )
1245 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
1246 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 )
1247 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0)
1255 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL)
1256 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0)
1257 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 )
1258 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1259 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 )
1260 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
1261 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 )
1262 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1263 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
1264 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)
1265 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 )
1266 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1274 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
1275 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
1276 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)
1281 #endif /* ADC_MULTIMODE_SUPPORT */
1282 
1286 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
1287 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
1288 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
1289 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
1290 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
1291 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
1292 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
1293 
1294 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
1295 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
1296 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
1297 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
1298 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
1299 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
1300 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
1301 
1302 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
1303 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
1304 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
1305 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
1306 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
1307 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
1308 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
1309 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
1310 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
1311 
1325 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1326 /* not timeout values. */
1327 /* Timeout values for ADC operations are dependent to device clock */
1328 /* configuration (system clock versus ADC clock), */
1329 /* and therefore must be defined in user application. */
1330 /* Indications for estimation of ADC timeout delays, for this */
1331 /* STM32 serie: */
1332 /* - ADC calibration time: maximum delay is 112/fADC. */
1333 /* (refer to device datasheet, parameter "tCAL") */
1334 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1335 /* (refer to device datasheet, parameter "tSTAB") */
1336 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1337 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1338 /* cycles */
1339 /* - ADC conversion time: duration depending on ADC clock and ADC */
1340 /* configuration. */
1341 /* (refer to device reference manual, section "Timing") */
1342 
1343 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1344 /* Delay set to maximum value (refer to device datasheet, */
1345 /* parameter "tADCVREG_STUP"). */
1346 /* Unit: us */
1347 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)
1349 /* Delay for internal voltage reference stabilization time. */
1350 /* Delay set to maximum value (refer to device datasheet, */
1351 /* parameter "tstart_vrefint"). */
1352 /* Unit: us */
1353 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL)
1355 /* Delay for temperature sensor stabilization time. */
1356 /* Literal set to maximum value (refer to device datasheet, */
1357 /* parameter "tSTART"). */
1358 /* Unit: us */
1359 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL)
1361 /* Delay required between ADC end of calibration and ADC enable. */
1362 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
1363 /* are required between ADC end of calibration and ADC enable. */
1364 /* Wait time can be computed in user application by waiting for the */
1365 /* equivalent number of CPU cycles, by taking into account */
1366 /* ratio of CPU clock versus ADC clock prescalers. */
1367 /* Unit: ADC clock cycles. */
1368 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL)
1379 /* Exported macro ------------------------------------------------------------*/
1380 
1395 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1396 
1403 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1404 
1461 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1462  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1463  ? ( \
1464  ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1465  ) \
1466  : \
1467  ( \
1468  (uint32_t)POSITION_VAL((__CHANNEL__)) \
1469  ) \
1470  )
1471 
1521 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1522  (((__DECIMAL_NB__) <= 9UL) \
1523  ? ( \
1524  ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1525  (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1526  (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1527  ) \
1528  : \
1529  ( \
1530  ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1531  (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1532  (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1533  ) \
1534  )
1535 
1594 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1595  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1596 
1669 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1670  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1671 
1706 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
1707 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1708  (((__ADC_INSTANCE__) == ADC1) \
1709  ? ( \
1710  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1711  ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1712  ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1713  ) \
1714  : \
1715  ((__ADC_INSTANCE__) == ADC2) \
1716  ? ( \
1717  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1718  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1719  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1720  ) \
1721  : \
1722  ((__ADC_INSTANCE__) == ADC3) \
1723  ? ( \
1724  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1725  ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1726  ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1727  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \
1728  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
1729  ) \
1730  : \
1731  (0UL) \
1732  )
1733 #elif defined (ADC1) && defined (ADC2)
1734 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1735  (((__ADC_INSTANCE__) == ADC1) \
1736  ? ( \
1737  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1738  ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1739  ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1740  ) \
1741  : \
1742  ((__ADC_INSTANCE__) == ADC2) \
1743  ? ( \
1744  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1745  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1746  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1747  ) \
1748  : \
1749  (0UL) \
1750  )
1751 #elif defined (ADC1)
1752 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1753  ( \
1754  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1755  ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1756  ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1757  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \
1758  ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \
1759  )
1760 #endif
1761 
1914 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1915  (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1916  ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1917  : \
1918  ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1919  ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
1920  : \
1921  (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1922  )
1923 
1944 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1945  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1946 
1966 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1967  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1968 
1981 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1982  (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
1983 
1997 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
1998  (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
1999 
2000 #if defined(ADC_MULTIMODE_SUPPORT)
2001 
2014 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2015  (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2016 #endif
2017 
2018 #if defined(ADC_MULTIMODE_SUPPORT)
2019 
2031 #if defined(ADC2)
2032 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2033  ( ( ((__ADCx__) == ADC2) \
2034  )? \
2035  (ADC1) \
2036  : \
2037  (__ADCx__) \
2038  )
2039 #else
2040 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2041  (__ADCx__)
2042 #endif
2043 #endif
2044 
2055 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2056 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2057  (ADC123_COMMON)
2058 #elif defined(ADC1) && defined(ADC2)
2059 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2060  (ADC12_COMMON)
2061 #else
2062 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2063  (ADC1_COMMON)
2064 #endif
2065 
2083 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2084 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2085  (LL_ADC_IsEnabled(ADC1) | \
2086  LL_ADC_IsEnabled(ADC2) | \
2087  LL_ADC_IsEnabled(ADC3) )
2088 #elif defined(ADC1) && defined(ADC2)
2089 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2090  (LL_ADC_IsEnabled(ADC1) | \
2091  LL_ADC_IsEnabled(ADC2) )
2092 #else
2093 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2094  (LL_ADC_IsEnabled(ADC1))
2095 #endif
2096 
2110 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2111  (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2112 
2131 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2132  __ADC_RESOLUTION_CURRENT__,\
2133  __ADC_RESOLUTION_TARGET__) \
2134  (((__DATA__) \
2135  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2136  >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2137  )
2138 
2155 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2156  __ADC_DATA__,\
2157  __ADC_RESOLUTION__) \
2158  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2159  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2160  )
2161 
2162 /* Legacy define */
2163 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
2164 
2190 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2191  __ADC_RESOLUTION__) \
2192  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2193  / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2194  (__ADC_RESOLUTION__), \
2195  LL_ADC_RESOLUTION_12B))
2196 
2242 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2243  __TEMPSENSOR_ADC_DATA__,\
2244  __ADC_RESOLUTION__) \
2245  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2246  (__ADC_RESOLUTION__), \
2247  LL_ADC_RESOLUTION_12B) \
2248  * (__VREFANALOG_VOLTAGE__)) \
2249  / TEMPSENSOR_CAL_VREFANALOG) \
2250  - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2251  ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2252  ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2253  ) + TEMPSENSOR_CAL1_TEMP \
2254  )
2255 
2300 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2301  __TEMPSENSOR_TYP_CALX_V__,\
2302  __TEMPSENSOR_CALX_TEMP__,\
2303  __VREFANALOG_VOLTAGE__,\
2304  __TEMPSENSOR_ADC_DATA__,\
2305  __ADC_RESOLUTION__) \
2306  ((( ( \
2307  (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2308  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2309  * 1000UL) \
2310  - \
2311  (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2312  * 1000UL) \
2313  ) \
2314  ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2315  ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2316  )
2317 
2327 /* Exported functions --------------------------------------------------------*/
2335 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2336 /* configuration of ADC instance, groups and multimode (if available): */
2337 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2338 
2369 #if defined(ADC_MULTIMODE_SUPPORT)
2370 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2371 {
2372  register uint32_t data_reg_addr;
2373 
2374  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2375  {
2376  /* Retrieve address of register DR */
2377  data_reg_addr = (uint32_t) &(ADCx->DR);
2378  }
2379  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2380  {
2381  /* Retrieve address of register CDR */
2382  data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2383  }
2384 
2385  return data_reg_addr;
2386 }
2387 #else
2388 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2389 {
2390  /* Prevent unused argument(s) compilation warning */
2391  (void)(Register);
2392 
2393  /* Retrieve address of register DR */
2394  return (uint32_t) &(ADCx->DR);
2395 }
2396 #endif
2397 
2440 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2441 {
2442  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2443 }
2444 
2468 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2469 {
2470  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2471 }
2472 
2502 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2503 {
2504  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2505 }
2506 
2524 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2525 {
2526  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2527 }
2528 
2568 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2569 {
2570  MODIFY_REG(ADCx->CALFACT,
2571  SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2572  CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2573 }
2574 
2591 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2592 {
2593  /* Retrieve bits with position in register depending on parameter */
2594  /* "SingleDiff". */
2595  /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2596  /* containing other bits reserved for other purpose. */
2597  return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2598 }
2599 
2617 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2618 {
2619  MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2620 }
2621 
2634 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2635 {
2636  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2637 }
2638 
2654 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2655 {
2656  MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2657 }
2658 
2669 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2670 {
2671  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2672 }
2673 
2722 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2723 {
2724  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2725 }
2726 
2770 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2771 {
2772  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2773 }
2774 
2855 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2856 {
2857  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2858 
2859  MODIFY_REG(*preg,
2860  ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
2861  ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
2862 }
2863 
2934 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
2935 {
2936  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2937 
2938  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
2939 }
2940 
2960 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
2961 {
2962  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2963 
2964  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
2965 }
2966 
2993 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
2994 {
2995  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2996 
2997  MODIFY_REG(*preg,
2998  ADC_OFR1_OFFSET1_EN,
2999  OffsetState);
3000 }
3001 
3019 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3020 {
3021  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3022 
3023  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3024 }
3025 
3026 #if defined(ADC_SMPR1_SMPPLUS)
3027 
3041 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3042 {
3043  MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3044 }
3045 
3055 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
3056 {
3057  return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3058 }
3059 #endif /* ADC_SMPR1_SMPPLUS */
3060 
3108 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3109 {
3110  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3111 }
3112 
3147 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3148 {
3149  register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3150 
3151  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3152  /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3153  register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3154 
3155  /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3156  /* to match with triggers literals definition. */
3157  return ((TriggerSource
3158  & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3159  | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3160  );
3161 }
3162 
3174 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3175 {
3176  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3177 }
3178 
3194 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3195 {
3196  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3197 }
3198 
3209 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3210 {
3211  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3212 }
3213 
3268 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3269 {
3270  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3271 }
3272 
3322 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3323 {
3324  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3325 }
3326 
3354 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3355 {
3356  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3357 }
3358 
3377 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3378 {
3379  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3380 }
3381 
3476 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3477 {
3478  /* Set bits with content of parameter "Channel" with bits position */
3479  /* in register and register position depending on parameter "Rank". */
3480  /* Parameters "Rank" and "Channel" are used with masks because containing */
3481  /* other bits reserved for other purpose. */
3482  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3483 
3484  MODIFY_REG(*preg,
3485  ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3486  ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3487 }
3488 
3585 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3586 {
3587  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3588 
3589  return (uint32_t)((READ_BIT(*preg,
3590  ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3591  >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
3592  );
3593 }
3594 
3614 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3615 {
3616  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
3617 }
3618 
3631 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3632 {
3633  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
3634 }
3635 
3671 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3672 {
3673  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
3674 }
3675 
3706 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3707 {
3708  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
3709 }
3710 
3711 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
3712 
3729 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
3730 {
3731  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
3732 }
3733 
3742 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)
3743 {
3744  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
3745 }
3746 #endif
3747 
3768 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3769 {
3770  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
3771 }
3772 
3782 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3783 {
3784  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
3785 }
3786 
3834 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3835 {
3836  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
3837 }
3838 
3873 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
3874 {
3875  register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
3876 
3877  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3878  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
3879  register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3880 
3881  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
3882  /* to match with triggers literals definition. */
3883  return ((TriggerSource
3884  & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
3885  | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
3886  );
3887 }
3888 
3900 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3901 {
3902  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
3903 }
3904 
3920 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3921 {
3922  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
3923 }
3924 
3935 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
3936 {
3937  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
3938 }
3939 
3961 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3962 {
3963  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
3964 }
3965 
3982 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
3983 {
3984  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
3985 }
3986 
4000 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4001 {
4002  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4003 }
4004 
4015 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4016 {
4017  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4018 }
4019 
4085 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4086 {
4087  /* Set bits with content of parameter "Channel" with bits position */
4088  /* in register depending on parameter "Rank". */
4089  /* Parameters "Rank" and "Channel" are used with masks because containing */
4090  /* other bits reserved for other purpose. */
4091  MODIFY_REG(ADCx->JSQR,
4092  (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4093  ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4094 }
4095 
4164 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4165 {
4166  return (uint32_t)((READ_BIT(ADCx->JSQR,
4167  (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4168  >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4169  );
4170 }
4171 
4202 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4203 {
4204  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4205 }
4206 
4216 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4217 {
4218  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4219 }
4220 
4262 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4263 {
4264  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4265 }
4266 
4277 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4278 {
4279  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4280 }
4281 
4501 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
4502  uint32_t TriggerSource,
4503  uint32_t ExternalTriggerEdge,
4504  uint32_t SequencerNbRanks,
4505  uint32_t Rank1_Channel,
4506  uint32_t Rank2_Channel,
4507  uint32_t Rank3_Channel,
4508  uint32_t Rank4_Channel)
4509 {
4510  /* Set bits with content of parameter "Rankx_Channel" with bits position */
4511  /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4512  /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4513  /* because containing other bits reserved for other purpose. */
4514  /* If parameter "TriggerSource" is set to SW start, then parameter */
4515  /* "ExternalTriggerEdge" is discarded. */
4516  register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
4517  MODIFY_REG(ADCx->JSQR,
4518  ADC_JSQR_JEXTSEL |
4519  ADC_JSQR_JEXTEN |
4520  ADC_JSQR_JSQ4 |
4521  ADC_JSQR_JSQ3 |
4522  ADC_JSQR_JSQ2 |
4523  ADC_JSQR_JSQ1 |
4524  ADC_JSQR_JL,
4525  (TriggerSource & ADC_JSQR_JEXTSEL) |
4526  (ExternalTriggerEdge * (is_trigger_not_sw)) |
4527  (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4528  (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4529  (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4530  (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4531  SequencerNbRanks
4532  );
4533 }
4534 
4642 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4643 {
4644  /* Set bits with content of parameter "SamplingTime" with bits position */
4645  /* in register and register position depending on parameter "Channel". */
4646  /* Parameter "Channel" is used with masks because containing */
4647  /* other bits reserved for other purpose. */
4648  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4649 
4650  MODIFY_REG(*preg,
4651  ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
4652  SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
4653 }
4654 
4738 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
4739 {
4740  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4741 
4742  return (uint32_t)(READ_BIT(*preg,
4743  ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
4744  >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
4745  );
4746 }
4747 
4796 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4797 {
4798  /* Bits of channels in single or differential mode are set only for */
4799  /* differential mode (for single mode, mask of bits allowed to be set is */
4800  /* shifted out of range of bits of channels in single or differential mode. */
4801  MODIFY_REG(ADCx->DIFSEL,
4802  Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
4803  (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4804 }
4805 
4846 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
4847 {
4848  return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
4849 }
4850 
5003 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5004 {
5005  /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5006  /* in register and register position depending on parameter "AWDy". */
5007  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5008  /* containing other bits reserved for other purpose. */
5009  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5010  + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5011 
5012  MODIFY_REG(*preg,
5013  (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5014  AWDChannelGroup & AWDy);
5015 }
5016 
5139 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5140 {
5141  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5142  + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5143 
5144  register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5145 
5146  /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5147  /* (parameter value LL_ADC_AWD_DISABLE). */
5148  /* Else, the selected AWD is enabled and is monitoring a group of channels */
5149  /* or a single channel. */
5150  if (AnalogWDMonitChannels != 0UL)
5151  {
5152  if (AWDy == LL_ADC_AWD1)
5153  {
5154  if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5155  {
5156  /* AWD monitoring a group of channels */
5157  AnalogWDMonitChannels = ((AnalogWDMonitChannels
5158  | (ADC_AWD_CR23_CHANNEL_MASK)
5159  )
5160  & (~(ADC_CFGR_AWD1CH))
5161  );
5162  }
5163  else
5164  {
5165  /* AWD monitoring a single channel */
5166  AnalogWDMonitChannels = (AnalogWDMonitChannels
5167  | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5168  );
5169  }
5170  }
5171  else
5172  {
5173  if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5174  {
5175  /* AWD monitoring a group of channels */
5176  AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5177  | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5178  );
5179  }
5180  else
5181  {
5182  /* AWD monitoring a single channel */
5183  /* AWD monitoring a group of channels */
5184  AnalogWDMonitChannels = (AnalogWDMonitChannels
5185  | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5186  | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5187  );
5188  }
5189  }
5190  }
5191 
5192  return AnalogWDMonitChannels;
5193 }
5194 
5247 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
5248  uint32_t AWDThresholdLowValue)
5249 {
5250  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5251  /* position in register and register position depending on parameter */
5252  /* "AWDy". */
5253  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5254  /* containing other bits reserved for other purpose. */
5255  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5256 
5257  MODIFY_REG(*preg,
5258  ADC_TR1_HT1 | ADC_TR1_LT1,
5259  (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5260 }
5261 
5316 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5317  uint32_t AWDThresholdValue)
5318 {
5319  /* Set bits with content of parameter "AWDThresholdValue" with bits */
5320  /* position in register and register position depending on parameters */
5321  /* "AWDThresholdsHighLow" and "AWDy". */
5322  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5323  /* containing other bits reserved for other purpose. */
5324  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5325 
5326  MODIFY_REG(*preg,
5327  AWDThresholdsHighLow,
5328  AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5329 }
5330 
5359 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5360 {
5361  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5362 
5363  return (uint32_t)(READ_BIT(*preg,
5364  (AWDThresholdsHighLow | ADC_TR1_LT1))
5365  >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
5366  );
5367 }
5368 
5402 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5403 {
5404  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5405 }
5406 
5427 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
5428 {
5429  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5430 }
5431 
5454 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5455 {
5456  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5457 }
5458 
5473 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
5474 {
5475  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
5476 }
5477 
5512 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
5513 {
5514  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
5515 }
5516 
5532 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
5533 {
5534  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
5535 }
5536 
5553 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
5554 {
5555  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
5556 }
5557 
5566 #if defined(ADC_MULTIMODE_SUPPORT)
5567 
5593 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5594 {
5595  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5596 }
5597 
5617 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
5618 {
5619  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5620 }
5621 
5668 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5669 {
5670  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
5671 }
5672 
5714 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
5715 {
5716  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
5717 }
5718 
5754 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5755 {
5756  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
5757 }
5758 
5782 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
5783 {
5784  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
5785 }
5786 #endif /* ADC_MULTIMODE_SUPPORT */
5787 
5794 /* Old functions name kept for legacy purpose, to be replaced by the */
5795 /* current functions name. */
5796 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5797 {
5798  LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);
5799 }
5800 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5801 {
5802  LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);
5803 }
5804 
5826 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
5827 {
5828  /* Note: Write register with some additional bits forced to state reset */
5829  /* instead of modifying only the selected bit for this function, */
5830  /* to not interfere with bits with HW property "rs". */
5831  MODIFY_REG(ADCx->CR,
5832  ADC_CR_BITS_PROPERTY_RS,
5833  ADC_CR_DEEPPWD);
5834 }
5835 
5849 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
5850 {
5851  /* Note: Write register with some additional bits forced to state reset */
5852  /* instead of modifying only the selected bit for this function, */
5853  /* to not interfere with bits with HW property "rs". */
5854  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
5855 }
5856 
5863 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
5864 {
5865  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
5866 }
5867 
5882 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
5883 {
5884  /* Note: Write register with some additional bits forced to state reset */
5885  /* instead of modifying only the selected bit for this function, */
5886  /* to not interfere with bits with HW property "rs". */
5887  MODIFY_REG(ADCx->CR,
5888  ADC_CR_BITS_PROPERTY_RS,
5889  ADC_CR_ADVREGEN);
5890 }
5891 
5901 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
5902 {
5903  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
5904 }
5905 
5912 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
5913 {
5914  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
5915 }
5916 
5933 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
5934 {
5935  /* Note: Write register with some additional bits forced to state reset */
5936  /* instead of modifying only the selected bit for this function, */
5937  /* to not interfere with bits with HW property "rs". */
5938  MODIFY_REG(ADCx->CR,
5939  ADC_CR_BITS_PROPERTY_RS,
5940  ADC_CR_ADEN);
5941 }
5942 
5953 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
5954 {
5955  /* Note: Write register with some additional bits forced to state reset */
5956  /* instead of modifying only the selected bit for this function, */
5957  /* to not interfere with bits with HW property "rs". */
5958  MODIFY_REG(ADCx->CR,
5959  ADC_CR_BITS_PROPERTY_RS,
5960  ADC_CR_ADDIS);
5961 }
5962 
5972 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
5973 {
5974  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
5975 }
5976 
5983 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
5984 {
5985  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
5986 }
5987 
6011 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6012 {
6013  /* Note: Write register with some additional bits forced to state reset */
6014  /* instead of modifying only the selected bit for this function, */
6015  /* to not interfere with bits with HW property "rs". */
6016  MODIFY_REG(ADCx->CR,
6017  ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6018  ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6019 }
6020 
6027 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6028 {
6029  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6030 }
6031 
6058 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6059 {
6060  /* Note: Write register with some additional bits forced to state reset */
6061  /* instead of modifying only the selected bit for this function, */
6062  /* to not interfere with bits with HW property "rs". */
6063  MODIFY_REG(ADCx->CR,
6064  ADC_CR_BITS_PROPERTY_RS,
6065  ADC_CR_ADSTART);
6066 }
6067 
6078 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6079 {
6080  /* Note: Write register with some additional bits forced to state reset */
6081  /* instead of modifying only the selected bit for this function, */
6082  /* to not interfere with bits with HW property "rs". */
6083  MODIFY_REG(ADCx->CR,
6084  ADC_CR_BITS_PROPERTY_RS,
6085  ADC_CR_ADSTP);
6086 }
6087 
6094 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6095 {
6096  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6097 }
6098 
6105 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6106 {
6107  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6108 }
6109 
6119 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6120 {
6121  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6122 }
6123 
6134 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6135 {
6136  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6137 }
6138 
6149 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6150 {
6151  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6152 }
6153 
6164 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6165 {
6166  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6167 }
6168 
6179 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6180 {
6181  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6182 }
6183 
6184 #if defined(ADC_MULTIMODE_SUPPORT)
6185 
6206 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6207 {
6208  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6209  ConversionData)
6210  >> (POSITION_VAL(ConversionData) & 0x1FUL)
6211  );
6212 }
6213 #endif /* ADC_MULTIMODE_SUPPORT */
6214 
6241 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6242 {
6243  /* Note: Write register with some additional bits forced to state reset */
6244  /* instead of modifying only the selected bit for this function, */
6245  /* to not interfere with bits with HW property "rs". */
6246  MODIFY_REG(ADCx->CR,
6247  ADC_CR_BITS_PROPERTY_RS,
6248  ADC_CR_JADSTART);
6249 }
6250 
6261 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6262 {
6263  /* Note: Write register with some additional bits forced to state reset */
6264  /* instead of modifying only the selected bit for this function, */
6265  /* to not interfere with bits with HW property "rs". */
6266  MODIFY_REG(ADCx->CR,
6267  ADC_CR_BITS_PROPERTY_RS,
6268  ADC_CR_JADSTP);
6269 }
6270 
6277 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6278 {
6279  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6280 }
6281 
6288 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6289 {
6290  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6291 }
6292 
6310 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6311 {
6312  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6313 
6314  return (uint32_t)(READ_BIT(*preg,
6315  ADC_JDR1_JDATA)
6316  );
6317 }
6318 
6337 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6338 {
6339  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6340 
6341  return (uint16_t)(READ_BIT(*preg,
6342  ADC_JDR1_JDATA)
6343  );
6344 }
6345 
6364 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
6365 {
6366  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6367 
6368  return (uint16_t)(READ_BIT(*preg,
6369  ADC_JDR1_JDATA)
6370  );
6371 }
6372 
6391 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
6392 {
6393  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6394 
6395  return (uint8_t)(READ_BIT(*preg,
6396  ADC_JDR1_JDATA)
6397  );
6398 }
6399 
6418 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
6419 {
6420  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6421 
6422  return (uint8_t)(READ_BIT(*preg,
6423  ADC_JDR1_JDATA)
6424  );
6425 }
6426 
6444 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
6445 {
6446  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6447 }
6448 
6455 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
6456 {
6457  return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6458 }
6459 
6466 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
6467 {
6468  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6469 }
6470 
6477 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
6478 {
6479  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6480 }
6481 
6488 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
6489 {
6490  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
6491 }
6492 
6499 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
6500 {
6501  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
6502 }
6503 
6510 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
6511 {
6512  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
6513 }
6514 
6521 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
6522 {
6523  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
6524 }
6525 
6532 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
6533 {
6534  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
6535 }
6536 
6543 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
6544 {
6545  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
6546 }
6547 
6554 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
6555 {
6556  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
6557 }
6558 
6568 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6569 {
6570  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6571 }
6572 
6579 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6580 {
6581  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6582 }
6583 
6590 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6591 {
6592  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6593 }
6594 
6601 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6602 {
6603  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6604 }
6605 
6612 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6613 {
6614  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6615 }
6616 
6623 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6624 {
6625  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6626 }
6627 
6634 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6635 {
6636  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6637 }
6638 
6645 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
6646 {
6647  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
6648 }
6649 
6656 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6657 {
6658  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6659 }
6660 
6667 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6668 {
6669  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6670 }
6671 
6678 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6679 {
6680  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6681 }
6682 
6683 #if defined(ADC_MULTIMODE_SUPPORT)
6684 
6691 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6692 {
6693  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
6694 }
6695 
6703 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6704 {
6705  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
6706 }
6707 
6715 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6716 {
6717  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6718 }
6719 
6727 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6728 {
6729  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6730 }
6731 
6739 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6740 {
6741  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
6742 }
6743 
6751 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6752 {
6753  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
6754 }
6755 
6763 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6764 {
6765  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
6766 }
6767 
6775 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6776 {
6777  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
6778 }
6779 
6787 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6788 {
6789  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
6790 }
6791 
6799 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6800 {
6801  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
6802 }
6803 
6811 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6812 {
6813  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
6814 }
6815 
6823 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6824 {
6825  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
6826 }
6827 
6835 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6836 {
6837  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
6838 }
6839 
6847 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6848 {
6849  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
6850 }
6851 
6859 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6860 {
6861  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
6862 }
6863 
6871 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6872 {
6873  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
6874 }
6875 
6883 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6884 {
6885  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
6886 }
6887 
6895 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6896 {
6897  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
6898 }
6899 
6907 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6908 {
6909  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
6910 }
6911 
6919 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6920 {
6921  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
6922 }
6923 
6931 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6932 {
6933  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
6934 }
6935 
6943 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6944 {
6945  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
6946 }
6947 #endif /* ADC_MULTIMODE_SUPPORT */
6948 
6963 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
6964 {
6965  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
6966 }
6967 
6974 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
6975 {
6976  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
6977 }
6978 
6985 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
6986 {
6987  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
6988 }
6989 
6996 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
6997 {
6998  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
6999 }
7000 
7007 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7008 {
7009  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7010 }
7011 
7018 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7019 {
7020  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7021 }
7022 
7029 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7030 {
7031  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7032 }
7033 
7040 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7041 {
7042  SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7043 }
7044 
7051 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7052 {
7053  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7054 }
7055 
7062 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7063 {
7064  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7065 }
7066 
7073 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7074 {
7075  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7076 }
7077 
7084 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7085 {
7086  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7087 }
7088 
7095 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7096 {
7097  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7098 }
7099 
7106 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7107 {
7108  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7109 }
7110 
7117 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7118 {
7119  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7120 }
7121 
7128 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7129 {
7130  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7131 }
7132 
7139 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7140 {
7141  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7142 }
7143 
7150 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7151 {
7152  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7153 }
7154 
7161 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7162 {
7163  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7164 }
7165 
7172 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7173 {
7174  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7175 }
7176 
7183 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7184 {
7185  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7186 }
7187 
7194 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7195 {
7196  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7197 }
7198 
7206 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7207 {
7208  return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7209 }
7210 
7218 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7219 {
7220  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7221 }
7222 
7230 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7231 {
7232  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7233 }
7234 
7242 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7243 {
7244  return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7245 }
7246 
7254 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7255 {
7256  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7257 }
7258 
7266 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7267 {
7268  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7269 }
7270 
7278 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7279 {
7280  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7281 }
7282 
7290 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7291 {
7292  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7293 }
7294 
7302 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7303 {
7304  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7305 }
7306 
7314 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7315 {
7316  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7317 }
7318 
7326 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7327 {
7328  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7329 }
7330 
7335 #if defined(USE_FULL_LL_DRIVER)
7336 
7340 /* Initialization of some features of ADC common parameters and multimode */
7341 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7342 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7343 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7344 
7345 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7346 /* (availability of ADC group injected depends on STM32 families) */
7347 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7348 
7349 /* Initialization of some features of ADC instance */
7350 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
7351 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7352 
7353 /* Initialization of some features of ADC instance and ADC group regular */
7354 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7355 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7356 
7357 /* Initialization of some features of ADC instance and ADC group injected */
7358 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7359 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7360 
7364 #endif /* USE_FULL_LL_DRIVER */
7365 
7374 #endif /* ADC1 || ADC2 || ADC3 */
7375 
7380 #ifdef __cplusplus
7381 }
7382 #endif
7383 
7384 #endif /* STM32L4xx_LL_ADC_H */
7385 
7386 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
LL_ADC_IsActiveFlag_MST_EOS
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master. CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS.
Definition: stm32l4xx_ll_adc.h:6739
LL_ADC_EnableIT_AWD1
__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1. IER AWD1IE LL_ADC_EnableIT_AWD1.
Definition: stm32l4xx_ll_adc.h:7051
LL_ADC_IsActiveFlag_SLV_AWD2
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC slave. CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2...
Definition: stm32l4xx_ll_adc.h:6919
LL_ADC_DisableIT_EOSMP
__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sampling. IER EOSMPIE LL_ADC_DisableIT_EOSMP.
Definition: stm32l4xx_ll_adc.h:7128
LL_ADC_IsActiveFlag_MST_OVR
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC master. CSR OVR_MST LL_ADC_IsActiveFlag_MST_...
Definition: stm32l4xx_ll_adc.h:6763
LL_ADC_REG_SetOverrun
__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
Set ADC group regular behavior in case of overrun: data preserved or overwritten. ...
Definition: stm32l4xx_ll_adc.h:3768
LL_ADC_DisableInternalRegulator
__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
Disable ADC internal voltage regulator.
Definition: stm32l4xx_ll_adc.h:5901
LL_ADC_REG_IsTriggerSourceSWStart
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
Definition: stm32l4xx_ll_adc.h:3174
LL_ADC_ClearFlag_EOC
__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
Clear flag ADC group regular end of unitary conversion. ISR EOC LL_ADC_ClearFlag_EOC.
Definition: stm32l4xx_ll_adc.h:6579
LL_ADC_ClearFlag_AWD1
__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1. ISR AWD1 LL_ADC_ClearFlag_AWD1.
Definition: stm32l4xx_ll_adc.h:6656
LL_ADC_REG_GetContinuousMode
__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
Definition: stm32l4xx_ll_adc.h:3631
LL_ADC_REG_InitTypeDef::SequencerDiscont
uint32_t SequencerDiscont
Definition: stm32l4xx_ll_adc.h:499
LL_ADC_GetResolution
__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
Get ADC resolution. Refer to reference manual for alignments formats dependencies to ADC resolutions...
Definition: stm32l4xx_ll_adc.h:2634
LL_ADC_IsEnabledIT_JQOVF
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt dis...
Definition: stm32l4xx_ll_adc.h:7290
LL_ADC_ClearFlag_JQOVF
__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
Clear flag ADC group injected contexts queue overflow. ISR JQOVF LL_ADC_ClearFlag_JQOVF.
Definition: stm32l4xx_ll_adc.h:6645
LL_ADC_DisableDeepPowerDown
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
Disable ADC deep power down mode.
Definition: stm32l4xx_ll_adc.h:5849
LL_ADC_REG_SetTriggerEdge
__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group regular conversion trigger polarity.
Definition: stm32l4xx_ll_adc.h:3194
LL_ADC_REG_ReadMultiConversionData32
__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave conc...
Definition: stm32l4xx_ll_adc.h:6206
LL_ADC_SetDataAlignment
__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
Definition: stm32l4xx_ll_adc.h:2654
LL_ADC_IsEnabled
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
Definition: stm32l4xx_ll_adc.h:5972
LL_ADC_REG_SetSequencerRanks
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
Definition: stm32l4xx_ll_adc.h:3476
LL_ADC_IsEnabledIT_AWD1
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled)...
Definition: stm32l4xx_ll_adc.h:7302
LL_ADC_IsEnabledIT_ADRDY
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled). IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY.
Definition: stm32l4xx_ll_adc.h:7206
LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular.
Definition: stm32l4xx_ll_adc.h:484
LL_ADC_ClearFlag_EOS
__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions. ISR EOS LL_ADC_ClearFlag_EOS.
Definition: stm32l4xx_ll_adc.h:6590
LL_ADC_CommonInitTypeDef::MultiTwoSamplingDelay
uint32_t MultiTwoSamplingDelay
Definition: stm32l4xx_ll_adc.h:418
LL_ADC_ClearFlag_JEOS
__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions. ISR JEOS LL_ADC_ClearFlag_JEOS.
Definition: stm32l4xx_ll_adc.h:6634
LL_ADC_SetCalibrationFactor
__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
Set ADC calibration factor in the mode single-ended or differential (for devices with differential mo...
Definition: stm32l4xx_ll_adc.h:2568
LL_ADC_INJ_StopConversion
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
Stop ADC group injected conversion.
Definition: stm32l4xx_ll_adc.h:6261
LL_ADC_IsActiveFlag_SLV_EOC
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC slave. CSR EOC_SLV LL_ADC_...
Definition: stm32l4xx_ll_adc.h:6727
LL_ADC_GetOffsetChannel
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be a...
Definition: stm32l4xx_ll_adc.h:2934
LL_ADC_INJ_ReadConversionData32
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and ...
Definition: stm32l4xx_ll_adc.h:6310
LL_ADC_REG_ReadConversionData6
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
Definition: stm32l4xx_ll_adc.h:6179
LL_ADC_IsEnabledIT_EOS
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled...
Definition: stm32l4xx_ll_adc.h:7230
LL_ADC_IsActiveFlag_MST_AWD2
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 2 of the ADC master. CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD...
Definition: stm32l4xx_ll_adc.h:6907
LL_ADC_IsActiveFlag_SLV_EOS
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave. CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS.
Definition: stm32l4xx_ll_adc.h:6751
LL_ADC_IsDisableOngoing
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
Get the selected ADC instance disable state. CR ADDIS LL_ADC_IsDisableOngoing.
Definition: stm32l4xx_ll_adc.h:5983
LL_ADC_IsEnabledIT_OVR
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled)...
Definition: stm32l4xx_ll_adc.h:7242
LL_ADC_REG_StructInit
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
Definition: stm32l4xx_ll_adc.c:903
LL_ADC_IsActiveFlag_SLV_ADRDY
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC slave. CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY.
Definition: stm32l4xx_ll_adc.h:6703
LL_ADC_IsInternalRegulatorEnabled
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
Get the selected ADC instance internal voltage regulator state. CR ADVREGEN LL_ADC_IsInternalRegulat...
Definition: stm32l4xx_ll_adc.h:5912
LL_ADC_INJ_SetTriggerSource
__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (ti...
Definition: stm32l4xx_ll_adc.h:3834
LL_ADC_DisableIT_JQOVF
__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
Disable interruption ADC group injected context queue overflow. IER JQOVFIE LL_ADC_DisableIT_JQOVF.
Definition: stm32l4xx_ll_adc.h:7161
LL_ADC_REG_GetDMATransfer
__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode...
Definition: stm32l4xx_ll_adc.h:3706
LL_ADC_REG_SetTriggerSource
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (tim...
Definition: stm32l4xx_ll_adc.h:3108
LL_ADC_ClearFlag_OVR
__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
Clear flag ADC group regular overrun. ISR OVR LL_ADC_ClearFlag_OVR.
Definition: stm32l4xx_ll_adc.h:6601
LL_ADC_GetAnalogWDMonitChannels
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
Get ADC analog watchdog monitored channel.
Definition: stm32l4xx_ll_adc.h:5139
LL_ADC_SetChannelSingleDiff
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
Set mode single-ended or differential input of the selected ADC channel.
Definition: stm32l4xx_ll_adc.h:4796
LL_ADC_SetOverSamplingScope
__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected de...
Definition: stm32l4xx_ll_adc.h:5402
LL_ADC_INJ_InitTypeDef::SequencerDiscont
uint32_t SequencerDiscont
Definition: stm32l4xx_ll_adc.h:559
LL_ADC_IsActiveFlag_EOS
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions. ISR EOS LL_ADC_IsActiveFlag_EOS.
Definition: stm32l4xx_ll_adc.h:6466
LL_ADC_IsEnabledIT_JEOC
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled...
Definition: stm32l4xx_ll_adc.h:7266
LL_ADC_ClearFlag_ADRDY
__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
Clear flag ADC ready.
Definition: stm32l4xx_ll_adc.h:6568
LL_ADC_IsActiveFlag_AWD2
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 2. ISR AWD2 LL_ADC_IsActiveFlag_AWD2.
Definition: stm32l4xx_ll_adc.h:6543
LL_ADC_IsEnabledIT_EOSMP
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled). IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP.
Definition: stm32l4xx_ll_adc.h:7254
LL_ADC_IsActiveFlag_MST_AWD3
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC master. CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD...
Definition: stm32l4xx_ll_adc.h:6931
LL_ADC_ClearFlag_AWD3
__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 3. ISR AWD3 LL_ADC_ClearFlag_AWD3.
Definition: stm32l4xx_ll_adc.h:6678
LL_ADC_GetSamplingTimeCommonConfig
__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
Get ADC sampling time common configuration impacting settings of sampling time channel wise...
Definition: stm32l4xx_ll_adc.h:3055
LL_ADC_GetOffsetLevel
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the r...
Definition: stm32l4xx_ll_adc.h:2960
LL_ADC_REG_SetTrigSource
__STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
Definition: stm32l4xx_ll_adc.h:5796
LL_ADC_EnableInternalRegulator
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
Enable ADC instance internal voltage regulator.
Definition: stm32l4xx_ll_adc.h:5882
LL_ADC_GetMultimode
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several...
Definition: stm32l4xx_ll_adc.h:5617
LL_ADC_REG_SetSequencerLength
__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
Definition: stm32l4xx_ll_adc.h:3268
LL_ADC_IsActiveFlag_SLV_JEOS
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave. CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS.
Definition: stm32l4xx_ll_adc.h:6847
LL_ADC_DisableIT_EOS
__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions. IER EOSIE LL_ADC_DisableIT_EOS.
Definition: stm32l4xx_ll_adc.h:7106
LL_ADC_REG_InitTypeDef::SequencerLength
uint32_t SequencerLength
Definition: stm32l4xx_ll_adc.h:494
LL_ADC_ConfigOverSamplingRatioShift
__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
Set ADC oversampling (impacting both ADC groups regular and injected)
Definition: stm32l4xx_ll_adc.h:5512
LL_ADC_INJ_Init
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
Definition: stm32l4xx_ll_adc.c:949
LL_ADC_GetDataAlignment
__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
Definition: stm32l4xx_ll_adc.h:2669
LL_ADC_REG_StartConversion
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
Start ADC group regular conversion.
Definition: stm32l4xx_ll_adc.h:6058
LL_ADC_INJ_InitTypeDef::SequencerLength
uint32_t SequencerLength
Definition: stm32l4xx_ll_adc.h:554
LL_ADC_Enable
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
Enable the selected ADC instance.
Definition: stm32l4xx_ll_adc.h:5933
LL_ADC_SetLowPowerMode
__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
Set ADC low power mode.
Definition: stm32l4xx_ll_adc.h:2722
LL_ADC_DisableIT_AWD2
__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 2. IER AWD2IE LL_ADC_DisableIT_AWD2.
Definition: stm32l4xx_ll_adc.h:7183
LL_ADC_Disable
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
Disable the selected ADC instance.
Definition: stm32l4xx_ll_adc.h:5953
LL_ADC_EnableIT_AWD3
__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 3. IER AWD3IE LL_ADC_EnableIT_AWD3.
Definition: stm32l4xx_ll_adc.h:7073
LL_ADC_INJ_GetTrigAuto
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular. CFGR JAUTO LL_ADC_...
Definition: stm32l4xx_ll_adc.h:4216
LL_ADC_REG_Init
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
Definition: stm32l4xx_ll_adc.c:816
LL_ADC_DisableIT_OVR
__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
Disable interruption ADC group regular overrun. IER OVRIE LL_ADC_DisableIT_OVR.
Definition: stm32l4xx_ll_adc.h:7117
LL_ADC_REG_GetTriggerEdge
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger polarity.
Definition: stm32l4xx_ll_adc.h:3209
LL_ADC_GetLowPowerMode
__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
Get ADC low power mode:
Definition: stm32l4xx_ll_adc.h:2770
LL_ADC_IsActiveFlag_SLV_JQOVF
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC slave. CSR JQOVF_SLV LL_ADC_...
Definition: stm32l4xx_ll_adc.h:6871
LL_ADC_InitTypeDef::Resolution
uint32_t Resolution
Definition: stm32l4xx_ll_adc.h:448
LL_ADC_SetOffsetState
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without mod...
Definition: stm32l4xx_ll_adc.h:2993
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
LL_ADC_DisableIT_ADRDY
__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
Disable interruption ADC ready. IER ADRDYIE LL_ADC_DisableIT_ADRDY.
Definition: stm32l4xx_ll_adc.h:7084
LL_ADC_GetOffsetState
__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled. OFR1 OFFSET1_EN LL_ADC_GetOffsetState OFR2 OFFSET2_EN LL_ADC_GetOffsetState OFR3 OFFSET3_EN LL_ADC_GetOffsetState OFR4 OFFSET4_EN LL_ADC_GetOffsetState.
Definition: stm32l4xx_ll_adc.h:3019
LL_ADC_IsActiveFlag_EOC
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
Get flag ADC group regular end of unitary conversion. ISR EOC LL_ADC_IsActiveFlag_EOC.
Definition: stm32l4xx_ll_adc.h:6455
LL_ADC_CommonInitTypeDef::Multimode
uint32_t Multimode
Definition: stm32l4xx_ll_adc.h:408
LL_ADC_IsActiveFlag_EOSMP
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
Get flag ADC group regular end of sampling phase. ISR EOSMP LL_ADC_IsActiveFlag_EOSMP.
Definition: stm32l4xx_ll_adc.h:6488
LL_ADC_SetOverSamplingDiscont
__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
Definition: stm32l4xx_ll_adc.h:5454
LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belon...
Definition: stm32l4xx_ll_adc.h:397
LL_ADC_IsActiveFlag_OVR
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
Get flag ADC group regular overrun. ISR OVR LL_ADC_IsActiveFlag_OVR.
Definition: stm32l4xx_ll_adc.h:6477
LL_ADC_REG_StopConversion
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
Stop ADC group regular conversion.
Definition: stm32l4xx_ll_adc.h:6078
LL_ADC_INJ_GetQueueMode
__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
Get ADC group injected context queue mode. CFGR JQM LL_ADC_INJ_GetQueueMode CFGR JQDIS LL_ADC_INJ_G...
Definition: stm32l4xx_ll_adc.h:4277
LL_ADC_StructInit
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
Definition: stm32l4xx_ll_adc.c:774
LL_ADC_IsActiveFlag_MST_EOC
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of unitary conversion of the ADC master. CSR EOC_MST LL_ADC...
Definition: stm32l4xx_ll_adc.h:6715
LL_ADC_EnableIT_EOC
__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of unitary conversion. IER EOCIE LL_ADC_EnableIT_EOC.
Definition: stm32l4xx_ll_adc.h:6974
LL_ADC_SetCommonClock
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
Set parameter common to several ADC: Clock source and prescaler.
Definition: stm32l4xx_ll_adc.h:2440
LL_ADC_GetAnalogWDThresholds
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresho...
Definition: stm32l4xx_ll_adc.h:5359
LL_ADC_SetChannelSamplingTime
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
Definition: stm32l4xx_ll_adc.h:4642
LL_ADC_REG_InitTypeDef::TriggerSource
uint32_t TriggerSource
Definition: stm32l4xx_ll_adc.h:486
LL_ADC_IsEnabledIT_AWD2
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled)...
Definition: stm32l4xx_ll_adc.h:7314
LL_ADC_SetResolution
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
Set ADC resolution. Refer to reference manual for alignments formats dependencies to ADC resolutions...
Definition: stm32l4xx_ll_adc.h:2617
LL_ADC_CommonInitTypeDef::MultiDMATransfer
uint32_t MultiDMATransfer
Definition: stm32l4xx_ll_adc.h:413
LL_ADC_INJ_ConfigQueueContext
__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
Set one context on ADC group injected that will be checked in contexts queue.
Definition: stm32l4xx_ll_adc.h:4501
LL_ADC_SetMultimode
__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several...
Definition: stm32l4xx_ll_adc.h:5593
LL_ADC_INJ_StructInit
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.
Definition: stm32l4xx_ll_adc.c:1020
LL_ADC_REG_ReadConversionData8
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
Definition: stm32l4xx_ll_adc.h:6164
LL_ADC_EnableDeepPowerDown
__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
Put ADC instance in deep power down state.
Definition: stm32l4xx_ll_adc.h:5826
LL_ADC_INJ_ReadConversionData12
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
Definition: stm32l4xx_ll_adc.h:6337
LL_ADC_DisableIT_AWD3
__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 3. IER AWD3IE LL_ADC_DisableIT_AWD3.
Definition: stm32l4xx_ll_adc.h:7194
LL_ADC_REG_SetDFSDMTransfer
__STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
Set ADC group regular conversion data transfer to DFSDM.
Definition: stm32l4xx_ll_adc.h:3729
LL_ADC_INJ_ReadConversionData10
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
Definition: stm32l4xx_ll_adc.h:6364
LL_ADC_REG_SetDMATransfer
__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode...
Definition: stm32l4xx_ll_adc.h:3671
LL_ADC_INJ_IsConversionOngoing
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
Get ADC group injected conversion state. CR JADSTART LL_ADC_INJ_IsConversionOngoing.
Definition: stm32l4xx_ll_adc.h:6277
LL_ADC_IsActiveFlag_JEOC
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
Get flag ADC group injected end of unitary conversion. ISR JEOC LL_ADC_IsActiveFlag_JEOC.
Definition: stm32l4xx_ll_adc.h:6499
LL_ADC_GetChannelSingleDiff
__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
Get mode single-ended or differential input of the selected ADC channel.
Definition: stm32l4xx_ll_adc.h:4846
LL_ADC_REG_IsStopConversionOngoing
__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
Get ADC group regular command of conversion stop state CR ADSTP LL_ADC_REG_IsStopConversionOngoing.
Definition: stm32l4xx_ll_adc.h:6105
LL_ADC_Init
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
Definition: stm32l4xx_ll_adc.c:729
LL_ADC_GetCommonPathInternalCh
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
Definition: stm32l4xx_ll_adc.h:2524
LL_ADC_INJ_InitTypeDef::TriggerSource
uint32_t TriggerSource
Definition: stm32l4xx_ll_adc.h:546
LL_ADC_DisableIT_JEOC
__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion. IER JEOCIE LL_ADC_DisableIT_JEOC.
Definition: stm32l4xx_ll_adc.h:7139
LL_ADC_GetMultiDMATransfer
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
Definition: stm32l4xx_ll_adc.h:5714
LL_ADC_IsActiveFlag_SLV_JEOC
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC slave. CSR JEOC_SLV LL_AD...
Definition: stm32l4xx_ll_adc.h:6823
LL_ADC_IsActiveFlag_MST_ADRDY
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC ready of the ADC master. CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY.
Definition: stm32l4xx_ll_adc.h:6691
LL_ADC_GetOverSamplingScope
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected de...
Definition: stm32l4xx_ll_adc.h:5427
LL_ADC_EnableIT_EOS
__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions. IER EOSIE LL_ADC_EnableIT_EOS.
Definition: stm32l4xx_ll_adc.h:6985
LL_ADC_INJ_GetTriggerEdge
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger polarity. Applicable only for trigger source set to externa...
Definition: stm32l4xx_ll_adc.h:3935
LL_ADC_INJ_SetQueueMode
__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
Set ADC group injected contexts queue mode.
Definition: stm32l4xx_ll_adc.h:4262
LL_ADC_IsEnabledIT_EOC
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled...
Definition: stm32l4xx_ll_adc.h:7218
LL_ADC_IsActiveFlag_SLV_AWD3
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 3 of the ADC slave. CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3...
Definition: stm32l4xx_ll_adc.h:6943
LL_ADC_REG_InitTypeDef::ContinuousMode
uint32_t ContinuousMode
Definition: stm32l4xx_ll_adc.h:506
LL_ADC_GetOverSamplingShift
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
Get ADC oversampling shift (impacting both ADC groups regular and injected) CFGR2 OVSS LL_ADC_GetOve...
Definition: stm32l4xx_ll_adc.h:5553
LL_ADC_IsActiveFlag_JQOVF
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
Get flag ADC group injected contexts queue overflow. ISR JQOVF LL_ADC_IsActiveFlag_JQOVF.
Definition: stm32l4xx_ll_adc.h:6521
LL_ADC_REG_ReadConversionData12
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
Definition: stm32l4xx_ll_adc.h:6134
LL_ADC_SetOffset
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
Set ADC selected offset number 1, 2, 3 or 4.
Definition: stm32l4xx_ll_adc.h:2855
LL_ADC_IsActiveFlag_AWD1
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag ISR AWD1 LL_ADC_IsActiveFlag_AWD1.
Definition: stm32l4xx_ll_adc.h:6532
LL_ADC_IsCalibrationOnGoing
__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
Get ADC calibration state. CR ADCAL LL_ADC_IsCalibrationOnGoing.
Definition: stm32l4xx_ll_adc.h:6027
LL_ADC_REG_InitTypeDef::Overrun
uint32_t Overrun
Definition: stm32l4xx_ll_adc.h:517
LL_ADC_ClearFlag_AWD2
__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 2. ISR AWD2 LL_ADC_ClearFlag_AWD2.
Definition: stm32l4xx_ll_adc.h:6667
LL_ADC_IsActiveFlag_MST_EOSMP
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC master. CSR EOSMP_MST LL_ADC_IsActiv...
Definition: stm32l4xx_ll_adc.h:6787
LL_ADC_INJ_IsStopConversionOngoing
__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
Get ADC group injected command of conversion stop state CR JADSTP LL_ADC_INJ_IsStopConversionOngoing...
Definition: stm32l4xx_ll_adc.h:6288
LL_ADC_INJ_SetSequencerDiscont
__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interru...
Definition: stm32l4xx_ll_adc.h:4000
LL_ADC_CommonInit
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common...
Definition: stm32l4xx_ll_adc.c:339
LL_ADC_IsActiveFlag_ADRDY
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
Get flag ADC ready.
Definition: stm32l4xx_ll_adc.h:6444
LL_ADC_IsActiveFlag_SLV_AWD1
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave. CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1.
Definition: stm32l4xx_ll_adc.h:6895
LL_ADC_REG_GetSequencerLength
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
Definition: stm32l4xx_ll_adc.h:3322
LL_ADC_INJ_ReadConversionData8
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
Definition: stm32l4xx_ll_adc.h:6391
LL_ADC_ClearFlag_JEOC
__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
Clear flag ADC group injected end of unitary conversion. ISR JEOC LL_ADC_ClearFlag_JEOC.
Definition: stm32l4xx_ll_adc.h:6623
LL_ADC_SetMultiTwoSamplingDelay
__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
Set ADC multimode delay between 2 sampling phases.
Definition: stm32l4xx_ll_adc.h:5754
LL_ADC_EnableIT_ADRDY
__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
Enable ADC ready. IER ADRDYIE LL_ADC_EnableIT_ADRDY.
Definition: stm32l4xx_ll_adc.h:6963
LL_ADC_INJ_SetTrigSource
__STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
Definition: stm32l4xx_ll_adc.h:5800
LL_ADC_INJ_ReadConversionData6
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 6 bits.
Definition: stm32l4xx_ll_adc.h:6418
LL_ADC_GetOverSamplingRatio
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
Get ADC oversampling ratio (impacting both ADC groups regular and injected) CFGR2 OVSR LL_ADC_GetOve...
Definition: stm32l4xx_ll_adc.h:5532
LL_ADC_SetAnalogWDThresholds
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
Definition: stm32l4xx_ll_adc.h:5316
LL_ADC_EnableIT_JEOC
__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of unitary conversion. IER JEOCIE LL_ADC_EnableIT_JEOC.
Definition: stm32l4xx_ll_adc.h:7018
LL_ADC_REG_InitTypeDef::DMATransfer
uint32_t DMATransfer
Definition: stm32l4xx_ll_adc.h:512
LL_ADC_CommonStructInit
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
Definition: stm32l4xx_ll_adc.c:421
LL_ADC_DisableIT_AWD1
__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1. IER AWD1IE LL_ADC_DisableIT_AWD1.
Definition: stm32l4xx_ll_adc.h:7172
LL_ADC_INJ_IsTriggerSourceSWStart
__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external. ...
Definition: stm32l4xx_ll_adc.h:3900
LL_ADC_InitTypeDef
Structure definition of some features of ADC instance.
Definition: stm32l4xx_ll_adc.h:446
LL_ADC_IsActiveFlag_MST_AWD1
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master. CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD...
Definition: stm32l4xx_ll_adc.h:6883
LL_ADC_EnableIT_EOSMP
__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sampling. IER EOSMPIE LL_ADC_EnableIT_EOSMP.
Definition: stm32l4xx_ll_adc.h:7007
LL_ADC_IsActiveFlag_AWD3
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 3. ISR AWD3 LL_ADC_IsActiveFlag_AWD3.
Definition: stm32l4xx_ll_adc.h:6554
LL_ADC_INJ_SetSequencerRanks
__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
Definition: stm32l4xx_ll_adc.h:4085
LL_ADC_GetCalibrationFactor
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
Get ADC calibration factor in the mode single-ended or differential (for devices with differential mo...
Definition: stm32l4xx_ll_adc.h:2591
LL_ADC_IsActiveFlag_JEOS
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions. ISR JEOS LL_ADC_IsActiveFlag_JEOS.
Definition: stm32l4xx_ll_adc.h:6510
LL_ADC_IsDeepPowerDownEnabled
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
Get the selected ADC instance deep power down state. CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled.
Definition: stm32l4xx_ll_adc.h:5863
LL_ADC_INJ_GetSequencerDiscont
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interru...
Definition: stm32l4xx_ll_adc.h:4015
LL_ADC_IsEnabledIT_AWD3
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled)...
Definition: stm32l4xx_ll_adc.h:7326
LL_ADC_REG_ReadConversionData10
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
Definition: stm32l4xx_ll_adc.h:6149
LL_ADC_ConfigAnalogWDThresholds
__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
Set ADC analog watchdog thresholds value of both thresholds high and low.
Definition: stm32l4xx_ll_adc.h:5247
LL_ADC_CommonInitTypeDef::CommonClock
uint32_t CommonClock
Definition: stm32l4xx_ll_adc.h:399
LL_ADC_REG_IsConversionOngoing
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
Get ADC group regular conversion state. CR ADSTART LL_ADC_REG_IsConversionOngoing.
Definition: stm32l4xx_ll_adc.h:6094
LL_ADC_DisableIT_EOC
__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of unitary conversion. IER EOCIE LL_ADC_DisableIT_EOC.
Definition: stm32l4xx_ll_adc.h:7095
LL_ADC_GetChannelSamplingTime
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
Definition: stm32l4xx_ll_adc.h:4738
LL_ADC_REG_ReadConversionData32
__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and ...
Definition: stm32l4xx_ll_adc.h:6119
LL_ADC_DeInit
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
Definition: stm32l4xx_ll_adc.c:454
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)
LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected.
Definition: stm32l4xx_ll_adc.h:544
LL_ADC_ClearFlag_EOSMP
__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sampling phase. ISR EOSMP LL_ADC_ClearFlag_EOSMP.
Definition: stm32l4xx_ll_adc.h:6612
LL_ADC_GetMultiTwoSamplingDelay
__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode delay between 2 sampling phases. CCR DELAY LL_ADC_GetMultiTwoSamplingDelay.
Definition: stm32l4xx_ll_adc.h:5782
LL_ADC_GetOverSamplingDiscont
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
Definition: stm32l4xx_ll_adc.h:5473
LL_ADC_REG_GetDFSDMTransfer
__STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer to DFSDM. CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer.
Definition: stm32l4xx_ll_adc.h:3742
LL_ADC_INJ_GetSequencerRanks
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
Definition: stm32l4xx_ll_adc.h:4164
LL_ADC_REG_SetContinuousMode
__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
Definition: stm32l4xx_ll_adc.h:3614
LL_ADC_INJ_InitTypeDef::TrigAuto
uint32_t TrigAuto
Definition: stm32l4xx_ll_adc.h:566
LL_ADC_InitTypeDef::LowPowerMode
uint32_t LowPowerMode
Definition: stm32l4xx_ll_adc.h:458
LL_ADC_SetAnalogWDMonitChannels
__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels...
Definition: stm32l4xx_ll_adc.h:5003
LL_ADC_IsActiveFlag_MST_JQOVF
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected context queue overflow of the ADC master. CSR JQOVF_MST LL_ADC...
Definition: stm32l4xx_ll_adc.h:6859
LL_ADC_INJ_GetTriggerSource
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external peripheral (ti...
Definition: stm32l4xx_ll_adc.h:3873
LL_ADC_IsActiveFlag_MST_JEOC
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of unitary conversion of the ADC master. CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC.
Definition: stm32l4xx_ll_adc.h:6811
LL_ADC_REG_GetSequencerDiscont
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrup...
Definition: stm32l4xx_ll_adc.h:3377
LL_ADC_SetCommonPathInternalCh
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
Definition: stm32l4xx_ll_adc.h:2502
LL_ADC_SetMultiDMATransfer
__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
Definition: stm32l4xx_ll_adc.h:5668
LL_ADC_CommonDeInit
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their defau...
Definition: stm32l4xx_ll_adc.c:310
LL_ADC_IsActiveFlag_SLV_EOSMP
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sampling of the ADC slave. CSR EOSMP_SLV LL_ADC_IsActive...
Definition: stm32l4xx_ll_adc.h:6799
LL_ADC_InitTypeDef::DataAlignment
uint32_t DataAlignment
Definition: stm32l4xx_ll_adc.h:453
LL_ADC_INJ_GetSequencerLength
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
Definition: stm32l4xx_ll_adc.h:3982
LL_ADC_REG_GetOverrun
__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
Get ADC group regular behavior in case of overrun: data preserved or overwritten. CFGR OVRMOD LL_ADC...
Definition: stm32l4xx_ll_adc.h:3782
LL_ADC_SetSamplingTimeCommonConfig
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
Set ADC sampling time common configuration impacting settings of sampling time channel wise...
Definition: stm32l4xx_ll_adc.h:3041
LL_ADC_REG_GetSequencerRanks
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
Definition: stm32l4xx_ll_adc.h:3585
LL_ADC_REG_GetTriggerSource
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external peripheral (tim...
Definition: stm32l4xx_ll_adc.h:3147
LL_ADC_DMA_GetRegAddr
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC insta...
Definition: stm32l4xx_ll_adc.h:2370
LL_ADC_IsEnabledIT_JEOS
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled...
Definition: stm32l4xx_ll_adc.h:7278
LL_ADC_StartCalibration
__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode av...
Definition: stm32l4xx_ll_adc.h:6011
LL_ADC_DisableIT_JEOS
__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions. IER JEOSIE LL_ADC_DisableIT_JEO...
Definition: stm32l4xx_ll_adc.h:7150
LL_ADC_EnableIT_OVR
__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
Enable ADC group regular interruption overrun. IER OVRIE LL_ADC_EnableIT_OVR.
Definition: stm32l4xx_ll_adc.h:6996
LL_ADC_GetCommonClock
__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: Clock source and prescaler. CCR CKMODE LL_ADC_GetCommonClock C...
Definition: stm32l4xx_ll_adc.h:2468
LL_ADC_IsActiveFlag_SLV_OVR
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular overrun of the ADC slave. CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_O...
Definition: stm32l4xx_ll_adc.h:6775
LL_ADC_INJ_SetTrigAuto
__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular. ...
Definition: stm32l4xx_ll_adc.h:4202
LL_ADC_REG_SetSequencerDiscont
__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrup...
Definition: stm32l4xx_ll_adc.h:3354
LL_ADC_INJ_SetSequencerLength
__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
Definition: stm32l4xx_ll_adc.h:3961
LL_ADC_IsActiveFlag_MST_JEOS
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master. CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS.
Definition: stm32l4xx_ll_adc.h:6835
LL_ADC_EnableIT_JQOVF
__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
Enable interruption ADC group injected context queue overflow. IER JQOVFIE LL_ADC_EnableIT_JQOVF.
Definition: stm32l4xx_ll_adc.h:7040
LL_ADC_EnableIT_JEOS
__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions. IER JEOSIE LL_ADC_EnableIT_JEOS...
Definition: stm32l4xx_ll_adc.h:7029
LL_ADC_EnableIT_AWD2
__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 2. IER AWD2IE LL_ADC_EnableIT_AWD2.
Definition: stm32l4xx_ll_adc.h:7062
LL_ADC_INJ_SetTriggerEdge
__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Set ADC group injected conversion trigger polarity. Applicable only for trigger source set to externa...
Definition: stm32l4xx_ll_adc.h:3920
LL_ADC_INJ_StartConversion
__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
Start ADC group injected conversion.
Definition: stm32l4xx_ll_adc.h:6241