Set the DMA2D transfer parameters.
1942 MODIFY_REG(hdma2d->
Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
1945 WRITE_REG(hdma2d->
Instance->OMAR, DstAddress);
1948 if (hdma2d->
Init.
Mode == DMA2D_R2M)
1950 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
1951 tmp2 = pdata & DMA2D_OCOLR_RED_1;
1952 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
1953 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
1958 tmp = (tmp3 | tmp2 | tmp1| tmp4);
1962 tmp = (tmp3 | tmp2 | tmp4);
1966 tmp2 = (tmp2 >> 19U);
1967 tmp3 = (tmp3 >> 10U);
1968 tmp4 = (tmp4 >> 3U );
1969 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
1973 tmp1 = (tmp1 >> 31U);
1974 tmp2 = (tmp2 >> 19U);
1975 tmp3 = (tmp3 >> 11U);
1976 tmp4 = (tmp4 >> 3U );
1977 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
1981 tmp1 = (tmp1 >> 28U);
1982 tmp2 = (tmp2 >> 20U);
1983 tmp3 = (tmp3 >> 12U);
1984 tmp4 = (tmp4 >> 4U );
1985 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
1988 WRITE_REG(hdma2d->
Instance->OCOLR, tmp);
1993 WRITE_REG(hdma2d->
Instance->FGMAR, pdata);
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)