STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_dma2d.c
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1 
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32l4xx_hal.h"
165 
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168 
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
187 #define DMA2D_TIMEOUT_ABORT (1000U)
188 #define DMA2D_TIMEOUT_SUSPEND (1000U)
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
209 /* Private functions ---------------------------------------------------------*/
210 /* Exported functions --------------------------------------------------------*/
237 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
238 {
239  /* Check the DMA2D peripheral state */
240  if(hdma2d == NULL)
241  {
242  return HAL_ERROR;
243  }
244 
245  /* Check the parameters */
246  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
247  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
248  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
249  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
250  assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
251  assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
252 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
253  assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
254 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
255 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
256  assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
257 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
258 
259 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
260  if (hdma2d->State == HAL_DMA2D_STATE_RESET)
261  {
262  /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
263  hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
264  hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
265  if(hdma2d->MspInitCallback == NULL)
266  {
267  hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
268  }
269 
270  /* Init the low level hardware */
271  hdma2d->MspInitCallback(hdma2d);
272  }
273 #else
274  if(hdma2d->State == HAL_DMA2D_STATE_RESET)
275  {
276  /* Allocate lock resource and initialize it */
277  hdma2d->Lock = HAL_UNLOCKED;
278  /* Init the low level hardware */
279  HAL_DMA2D_MspInit(hdma2d);
280  }
281 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
282 
283  /* Change DMA2D peripheral state */
284  hdma2d->State = HAL_DMA2D_STATE_BUSY;
285 
286  /* DMA2D CR register configuration -------------------------------------------*/
287 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
288  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
289 #else
290  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
291 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
292 
293  /* DMA2D OPFCCR register configuration ---------------------------------------*/
294 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
295  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
296 #else
297  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
298 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
299 
300  /* DMA2D OOR register configuration ------------------------------------------*/
301  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
302  /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
303  MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
304 
305 
306  /* Update error code */
307  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
308 
309  /* Initialize the DMA2D state*/
310  hdma2d->State = HAL_DMA2D_STATE_READY;
311 
312  return HAL_OK;
313 }
314 
323 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
324 {
325 
326  /* Check the DMA2D peripheral state */
327  if(hdma2d == NULL)
328  {
329  return HAL_ERROR;
330  }
331 
332  /* Before aborting any DMA2D transfer or CLUT loading, check
333  first whether or not DMA2D clock is enabled */
334  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
335  {
336  /* Abort DMA2D transfer if any */
337  if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
338  {
339  if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
340  {
341  /* Issue when aborting DMA2D transfer */
342  return HAL_ERROR;
343  }
344  }
345  else
346  {
347  /* Abort background CLUT loading if any */
348  if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
349  {
350  if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
351  {
352  /* Issue when aborting background CLUT loading */
353  return HAL_ERROR;
354  }
355  }
356  else
357  {
358  /* Abort foreground CLUT loading if any */
359  if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
360  {
361  if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
362  {
363  /* Issue when aborting foreground CLUT loading */
364  return HAL_ERROR;
365  }
366  }
367  }
368  }
369  }
370 
371  /* Reset DMA2D control registers*/
372  hdma2d->Instance->CR = 0U;
373  hdma2d->Instance->IFCR = 0x3FU;
374  hdma2d->Instance->FGOR = 0U;
375  hdma2d->Instance->BGOR = 0U;
376  hdma2d->Instance->FGPFCCR = 0U;
377  hdma2d->Instance->BGPFCCR = 0U;
378  hdma2d->Instance->OPFCCR = 0U;
379 
380 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
381 
382  if(hdma2d->MspDeInitCallback == NULL)
383  {
384  hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
385  }
386 
387  /* DeInit the low level hardware */
388  hdma2d->MspDeInitCallback(hdma2d);
389 
390 #else
391  /* Carry on with de-initialization of low level hardware */
392  HAL_DMA2D_MspDeInit(hdma2d);
393 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
394 
395  /* Update error code */
396  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
397 
398  /* Initialize the DMA2D state*/
399  hdma2d->State = HAL_DMA2D_STATE_RESET;
400 
401  /* Release Lock */
402  __HAL_UNLOCK(hdma2d);
403 
404  return HAL_OK;
405 }
406 
413 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
414 {
415  /* Prevent unused argument(s) compilation warning */
416  UNUSED(hdma2d);
417 
418  /* NOTE : This function should not be modified; when the callback is needed,
419  the HAL_DMA2D_MspInit can be implemented in the user file.
420  */
421 }
422 
429 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
430 {
431  /* Prevent unused argument(s) compilation warning */
432  UNUSED(hdma2d);
433 
434  /* NOTE : This function should not be modified; when the callback is needed,
435  the HAL_DMA2D_MspDeInit can be implemented in the user file.
436  */
437 }
438 
439 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
440 
456 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
457 {
458  HAL_StatusTypeDef status = HAL_OK;
459 
460  if(pCallback == NULL)
461  {
462  /* Update the error code */
463  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
464  return HAL_ERROR;
465  }
466  /* Process locked */
467  __HAL_LOCK(hdma2d);
468 
469  if(HAL_DMA2D_STATE_READY == hdma2d->State)
470  {
471  switch (CallbackID)
472  {
473  case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
474  hdma2d->XferCpltCallback = pCallback;
475  break;
476 
477  case HAL_DMA2D_TRANSFERERROR_CB_ID :
478  hdma2d->XferErrorCallback = pCallback;
479  break;
480 
481  case HAL_DMA2D_LINEEVENT_CB_ID :
482  hdma2d->LineEventCallback = pCallback;
483  break;
484 
485  case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
486  hdma2d->CLUTLoadingCpltCallback = pCallback;
487  break;
488 
489  case HAL_DMA2D_MSPINIT_CB_ID :
490  hdma2d->MspInitCallback = pCallback;
491  break;
492 
493  case HAL_DMA2D_MSPDEINIT_CB_ID :
494  hdma2d->MspDeInitCallback = pCallback;
495  break;
496 
497  default :
498  /* Update the error code */
499  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
500  /* update return status */
501  status = HAL_ERROR;
502  break;
503  }
504  }
505  else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
506  {
507  switch (CallbackID)
508  {
509  case HAL_DMA2D_MSPINIT_CB_ID :
510  hdma2d->MspInitCallback = pCallback;
511  break;
512 
513  case HAL_DMA2D_MSPDEINIT_CB_ID :
514  hdma2d->MspDeInitCallback = pCallback;
515  break;
516 
517  default :
518  /* Update the error code */
519  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
520  /* update return status */
521  status = HAL_ERROR;
522  break;
523  }
524  }
525  else
526  {
527  /* Update the error code */
528  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
529  /* update return status */
530  status = HAL_ERROR;
531  }
532 
533  /* Release Lock */
534  __HAL_UNLOCK(hdma2d);
535  return status;
536 }
537 
553 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
554 {
555 HAL_StatusTypeDef status = HAL_OK;
556 
557  /* Process locked */
558  __HAL_LOCK(hdma2d);
559 
560  if(HAL_DMA2D_STATE_READY == hdma2d->State)
561  {
562  switch (CallbackID)
563  {
564  case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
565  hdma2d->XferCpltCallback = NULL;
566  break;
567 
568  case HAL_DMA2D_TRANSFERERROR_CB_ID :
569  hdma2d->XferErrorCallback = NULL;
570  break;
571 
572  case HAL_DMA2D_LINEEVENT_CB_ID :
573  hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
574  break;
575 
576  case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
577  hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
578  break;
579 
580  case HAL_DMA2D_MSPINIT_CB_ID :
581  hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
582  break;
583 
584  case HAL_DMA2D_MSPDEINIT_CB_ID :
585  hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
586  break;
587 
588  default :
589  /* Update the error code */
590  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
591  /* update return status */
592  status = HAL_ERROR;
593  break;
594  }
595  }
596  else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
597  {
598  switch (CallbackID)
599  {
600  case HAL_DMA2D_MSPINIT_CB_ID :
601  hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
602  break;
603 
604  case HAL_DMA2D_MSPDEINIT_CB_ID :
605  hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
606  break;
607 
608  default :
609  /* Update the error code */
610  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
611  /* update return status */
612  status = HAL_ERROR;
613  break;
614  }
615  }
616  else
617  {
618  /* Update the error code */
619  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
620  /* update return status */
621  status = HAL_ERROR;
622  }
623 
624  /* Release Lock */
625  __HAL_UNLOCK(hdma2d);
626  return status;
627 }
628 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
629 
683 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
684 {
685  /* Check the parameters */
686  assert_param(IS_DMA2D_LINE(Height));
687  assert_param(IS_DMA2D_PIXEL(Width));
688 
689  /* Process locked */
690  __HAL_LOCK(hdma2d);
691 
692  /* Change DMA2D peripheral state */
693  hdma2d->State = HAL_DMA2D_STATE_BUSY;
694 
695  /* Configure the source, destination address and the data size */
696  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
697 
698  /* Enable the Peripheral */
699  __HAL_DMA2D_ENABLE(hdma2d);
700 
701  return HAL_OK;
702 }
703 
717 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
718 {
719  /* Check the parameters */
720  assert_param(IS_DMA2D_LINE(Height));
721  assert_param(IS_DMA2D_PIXEL(Width));
722 
723  /* Process locked */
724  __HAL_LOCK(hdma2d);
725 
726  /* Change DMA2D peripheral state */
727  hdma2d->State = HAL_DMA2D_STATE_BUSY;
728 
729  /* Configure the source, destination address and the data size */
730  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
731 
732  /* Enable the transfer complete, transfer error and configuration error interrupts */
733  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
734 
735  /* Enable the Peripheral */
736  __HAL_DMA2D_ENABLE(hdma2d);
737 
738  return HAL_OK;
739 }
740 
752 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
753 {
754  /* Check the parameters */
755  assert_param(IS_DMA2D_LINE(Height));
756  assert_param(IS_DMA2D_PIXEL(Width));
757 
758  /* Process locked */
759  __HAL_LOCK(hdma2d);
760 
761  /* Change DMA2D peripheral state */
762  hdma2d->State = HAL_DMA2D_STATE_BUSY;
763 
764  /* Configure DMA2D Stream source2 address */
765  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
766 
767  /* Configure the source, destination address and the data size */
768  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
769 
770  /* Enable the Peripheral */
771  __HAL_DMA2D_ENABLE(hdma2d);
772 
773  return HAL_OK;
774 }
775 
787 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
788 {
789  /* Check the parameters */
790  assert_param(IS_DMA2D_LINE(Height));
791  assert_param(IS_DMA2D_PIXEL(Width));
792 
793  /* Process locked */
794  __HAL_LOCK(hdma2d);
795 
796  /* Change DMA2D peripheral state */
797  hdma2d->State = HAL_DMA2D_STATE_BUSY;
798 
799  /* Configure DMA2D Stream source2 address */
800  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
801 
802  /* Configure the source, destination address and the data size */
803  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
804 
805  /* Enable the transfer complete, transfer error and configuration error interrupts */
806  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
807 
808  /* Enable the Peripheral */
809  __HAL_DMA2D_ENABLE(hdma2d);
810 
811  return HAL_OK;
812 }
813 
820 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
821 {
822  uint32_t tickstart;
823 
824  /* Abort the DMA2D transfer */
825  /* START bit is reset to make sure not to set it again, in the event the HW clears it
826  between the register read and the register write by the CPU (writing 0 has no
827  effect on START bitvalue) */
828  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
829 
830  /* Get tick */
831  tickstart = HAL_GetTick();
832 
833  /* Check if the DMA2D is effectively disabled */
834  while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
835  {
836  if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
837  {
838  /* Update error code */
839  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
840 
841  /* Change the DMA2D state */
842  hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
843 
844  /* Process Unlocked */
845  __HAL_UNLOCK(hdma2d);
846 
847  return HAL_TIMEOUT;
848  }
849  }
850 
851  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
852  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
853 
854  /* Change the DMA2D state*/
855  hdma2d->State = HAL_DMA2D_STATE_READY;
856 
857  /* Process Unlocked */
858  __HAL_UNLOCK(hdma2d);
859 
860  return HAL_OK;
861 }
862 
869 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
870 {
871  uint32_t tickstart;
872 
873  /* Suspend the DMA2D transfer */
874  /* START bit is reset to make sure not to set it again, in the event the HW clears it
875  between the register read and the register write by the CPU (writing 0 has no
876  effect on START bitvalue). */
877  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
878 
879  /* Get tick */
880  tickstart = HAL_GetTick();
881 
882  /* Check if the DMA2D is effectively suspended */
883  while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
884  {
885  if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
886  {
887  /* Update error code */
888  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
889 
890  /* Change the DMA2D state */
891  hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
892 
893  return HAL_TIMEOUT;
894  }
895  }
896 
897  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
898  if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
899  {
900  hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
901  }
902  else
903  {
904  /* Make sure SUSP bit is cleared since it is meaningless
905  when no tranfer is on-going */
906  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
907  }
908 
909  return HAL_OK;
910 }
911 
918 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
919 {
920  /* Check the SUSP and START bits */
921  if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
922  {
923  /* Ongoing transfer is suspended: change the DMA2D state before resuming */
924  hdma2d->State = HAL_DMA2D_STATE_BUSY;
925  }
926 
927  /* Resume the DMA2D transfer */
928  /* START bit is reset to make sure not to set it again, in the event the HW clears it
929  between the register read and the register write by the CPU (writing 0 has no
930  effect on START bitvalue). */
931  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
932 
933  return HAL_OK;
934 }
935 
936 
946 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
947 {
948  /* Check the parameters */
949  assert_param(IS_DMA2D_LAYER(LayerIdx));
950 
951  /* Process locked */
952  __HAL_LOCK(hdma2d);
953 
954  /* Change DMA2D peripheral state */
955  hdma2d->State = HAL_DMA2D_STATE_BUSY;
956 
957  if(LayerIdx == DMA2D_BACKGROUND_LAYER)
958  {
959  /* Enable the background CLUT loading */
960  SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
961  }
962  else
963  {
964  /* Enable the foreground CLUT loading */
965  SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
966  }
967 
968  return HAL_OK;
969 }
970 
971 
984 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
985 {
986  /* Check the parameters */
987  assert_param(IS_DMA2D_LAYER(LayerIdx));
988  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
989  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
990 
991  /* Process locked */
992  __HAL_LOCK(hdma2d);
993 
994  /* Change DMA2D peripheral state */
995  hdma2d->State = HAL_DMA2D_STATE_BUSY;
996 
997  /* Configure the CLUT of the background DMA2D layer */
998  if(LayerIdx == DMA2D_BACKGROUND_LAYER)
999  {
1000  /* Write background CLUT memory address */
1001  WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1002 
1003  /* Write background CLUT size and CLUT color mode */
1004  MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1005  ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1006 
1007  /* Enable the CLUT loading for the background */
1008  SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1009  }
1010  /* Configure the CLUT of the foreground DMA2D layer */
1011  else
1012  {
1013  /* Write foreground CLUT memory address */
1014  WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1015 
1016  /* Write foreground CLUT size and CLUT color mode */
1017  MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1018  ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1019 
1020  /* Enable the CLUT loading for the foreground */
1021  SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1022  }
1023 
1024  return HAL_OK;
1025 }
1026 
1038 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1039 {
1040  /* Check the parameters */
1041  assert_param(IS_DMA2D_LAYER(LayerIdx));
1042  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1043  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1044 
1045  /* Process locked */
1046  __HAL_LOCK(hdma2d);
1047 
1048  /* Change DMA2D peripheral state */
1049  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1050 
1051  /* Configure the CLUT of the background DMA2D layer */
1052  if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1053  {
1054  /* Write background CLUT memory address */
1055  WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1056 
1057  /* Write background CLUT size and CLUT color mode */
1058  MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1059  ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1060 
1061  /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1062  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1063 
1064  /* Enable the CLUT loading for the background */
1065  SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1066  }
1067  /* Configure the CLUT of the foreground DMA2D layer */
1068  else
1069  {
1070  /* Write foreground CLUT memory address */
1071  WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1072 
1073  /* Write foreground CLUT size and CLUT color mode */
1074  MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1075  ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1076 
1077  /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1078  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1079 
1080  /* Enable the CLUT loading for the foreground */
1081  SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1082  }
1083 
1084  return HAL_OK;
1085 }
1086 
1096 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1097 {
1098  uint32_t tickstart;
1099  const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1100 
1101  /* Abort the CLUT loading */
1102  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1103 
1104  /* If foreground CLUT loading is considered, update local variables */
1105  if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1106  {
1107  reg = &(hdma2d->Instance->FGPFCCR);
1108  }
1109 
1110 
1111  /* Get tick */
1112  tickstart = HAL_GetTick();
1113 
1114  /* Check if the CLUT loading is aborted */
1115  while((*reg & DMA2D_BGPFCCR_START) != 0U)
1116  {
1117  if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
1118  {
1119  /* Update error code */
1120  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1121 
1122  /* Change the DMA2D state */
1123  hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1124 
1125  /* Process Unlocked */
1126  __HAL_UNLOCK(hdma2d);
1127 
1128  return HAL_TIMEOUT;
1129  }
1130  }
1131 
1132  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1133  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1134 
1135  /* Change the DMA2D state*/
1136  hdma2d->State = HAL_DMA2D_STATE_READY;
1137 
1138  /* Process Unlocked */
1139  __HAL_UNLOCK(hdma2d);
1140 
1141  return HAL_OK;
1142 }
1143 
1153 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1154 {
1155  uint32_t tickstart;
1156  uint32_t loadsuspended;
1157  const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1158 
1159  /* Suspend the CLUT loading */
1160  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1161 
1162  /* If foreground CLUT loading is considered, update local variables */
1163  if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1164  {
1165  reg = &(hdma2d->Instance->FGPFCCR);
1166  }
1167 
1168  /* Get tick */
1169  tickstart = HAL_GetTick();
1170 
1171  /* Check if the CLUT loading is suspended */
1172  loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1173  loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1174  while (loadsuspended == 0UL)
1175  {
1176  if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
1177  {
1178  /* Update error code */
1179  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1180 
1181  /* Change the DMA2D state */
1182  hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1183 
1184  return HAL_TIMEOUT;
1185  }
1186  loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1187  loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1188  }
1189 
1190  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1191  if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1192  {
1193  hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1194  }
1195  else
1196  {
1197  /* Make sure SUSP bit is cleared since it is meaningless
1198  when no tranfer is on-going */
1199  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1200  }
1201 
1202  return HAL_OK;
1203 }
1204 
1214 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1215 {
1216  /* Check the SUSP and START bits for background or foreground CLUT loading */
1217  if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1218  {
1219  /* Background CLUT loading suspension check */
1220  if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1221  {
1222  if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1223  {
1224  /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1225  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1226  }
1227  }
1228  }
1229  else
1230  {
1231  /* Foreground CLUT loading suspension check */
1232  if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1233  {
1234  if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1235  {
1236  /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1237  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1238  }
1239  }
1240  }
1241 
1242  /* Resume the CLUT loading */
1243  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1244 
1245  return HAL_OK;
1246 }
1247 
1248 
1257 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1258 {
1259  uint32_t tickstart;
1260  uint32_t layer_start;
1261  __IO uint32_t isrflags = 0x0U;
1262 
1263  /* Polling for DMA2D transfer */
1264  if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1265  {
1266  /* Get tick */
1267  tickstart = HAL_GetTick();
1268 
1269  while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1270  {
1271  isrflags = READ_REG(hdma2d->Instance->ISR);
1272  if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1273  {
1274  if ((isrflags & DMA2D_FLAG_CE) != 0U)
1275  {
1276  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1277  }
1278  if ((isrflags & DMA2D_FLAG_TE) != 0U)
1279  {
1280  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1281  }
1282  /* Clear the transfer and configuration error flags */
1283  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1284 
1285  /* Change DMA2D state */
1286  hdma2d->State = HAL_DMA2D_STATE_ERROR;
1287 
1288  /* Process unlocked */
1289  __HAL_UNLOCK(hdma2d);
1290 
1291  return HAL_ERROR;
1292  }
1293  /* Check for the Timeout */
1294  if(Timeout != HAL_MAX_DELAY)
1295  {
1296  if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1297  {
1298  /* Update error code */
1299  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1300 
1301  /* Change the DMA2D state */
1302  hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1303 
1304  /* Process unlocked */
1305  __HAL_UNLOCK(hdma2d);
1306 
1307  return HAL_TIMEOUT;
1308  }
1309  }
1310  }
1311  }
1312  /* Polling for CLUT loading (foreground or background) */
1313  layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1314  layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1315  if (layer_start != 0U)
1316  {
1317  /* Get tick */
1318  tickstart = HAL_GetTick();
1319 
1320  while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1321  {
1322  isrflags = READ_REG(hdma2d->Instance->ISR);
1323  if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1324  {
1325  if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1326  {
1327  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1328  }
1329  if ((isrflags & DMA2D_FLAG_CE) != 0U)
1330  {
1331  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1332  }
1333  if ((isrflags & DMA2D_FLAG_TE) != 0U)
1334  {
1335  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1336  }
1337  /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1338  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1339 
1340  /* Change DMA2D state */
1341  hdma2d->State= HAL_DMA2D_STATE_ERROR;
1342 
1343  /* Process unlocked */
1344  __HAL_UNLOCK(hdma2d);
1345 
1346  return HAL_ERROR;
1347  }
1348  /* Check for the Timeout */
1349  if(Timeout != HAL_MAX_DELAY)
1350  {
1351  if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1352  {
1353  /* Update error code */
1354  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1355 
1356  /* Change the DMA2D state */
1357  hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1358 
1359  /* Process unlocked */
1360  __HAL_UNLOCK(hdma2d);
1361 
1362  return HAL_TIMEOUT;
1363  }
1364  }
1365  }
1366  }
1367 
1368  /* Clear the transfer complete and CLUT loading flags */
1369  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1370 
1371  /* Change DMA2D state */
1372  hdma2d->State = HAL_DMA2D_STATE_READY;
1373 
1374  /* Process unlocked */
1375  __HAL_UNLOCK(hdma2d);
1376 
1377  return HAL_OK;
1378 }
1385 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1386 {
1387  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1388  uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1389 
1390  /* Transfer Error Interrupt management ***************************************/
1391  if ((isrflags & DMA2D_FLAG_TE) != 0U)
1392  {
1393  if ((crflags & DMA2D_IT_TE) != 0U)
1394  {
1395  /* Disable the transfer Error interrupt */
1396  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1397 
1398  /* Update error code */
1399  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1400 
1401  /* Clear the transfer error flag */
1402  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1403 
1404  /* Change DMA2D state */
1405  hdma2d->State = HAL_DMA2D_STATE_ERROR;
1406 
1407  /* Process Unlocked */
1408  __HAL_UNLOCK(hdma2d);
1409 
1410  if(hdma2d->XferErrorCallback != NULL)
1411  {
1412  /* Transfer error Callback */
1413  hdma2d->XferErrorCallback(hdma2d);
1414  }
1415  }
1416  }
1417  /* Configuration Error Interrupt management **********************************/
1418  if ((isrflags & DMA2D_FLAG_CE) != 0U)
1419  {
1420  if ((crflags & DMA2D_IT_CE) != 0U)
1421  {
1422  /* Disable the Configuration Error interrupt */
1423  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1424 
1425  /* Clear the Configuration error flag */
1426  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1427 
1428  /* Update error code */
1429  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1430 
1431  /* Change DMA2D state */
1432  hdma2d->State = HAL_DMA2D_STATE_ERROR;
1433 
1434  /* Process Unlocked */
1435  __HAL_UNLOCK(hdma2d);
1436 
1437  if(hdma2d->XferErrorCallback != NULL)
1438  {
1439  /* Transfer error Callback */
1440  hdma2d->XferErrorCallback(hdma2d);
1441  }
1442  }
1443  }
1444  /* CLUT access Error Interrupt management ***********************************/
1445  if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1446  {
1447  if ((crflags & DMA2D_IT_CAE) != 0U)
1448  {
1449  /* Disable the CLUT access error interrupt */
1450  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1451 
1452  /* Clear the CLUT access error flag */
1453  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1454 
1455  /* Update error code */
1456  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1457 
1458  /* Change DMA2D state */
1459  hdma2d->State = HAL_DMA2D_STATE_ERROR;
1460 
1461  /* Process Unlocked */
1462  __HAL_UNLOCK(hdma2d);
1463 
1464  if(hdma2d->XferErrorCallback != NULL)
1465  {
1466  /* Transfer error Callback */
1467  hdma2d->XferErrorCallback(hdma2d);
1468  }
1469  }
1470  }
1471  /* Transfer watermark Interrupt management **********************************/
1472  if ((isrflags & DMA2D_FLAG_TW) != 0U)
1473  {
1474  if ((crflags & DMA2D_IT_TW) != 0U)
1475  {
1476  /* Disable the transfer watermark interrupt */
1477  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1478 
1479  /* Clear the transfer watermark flag */
1480  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1481 
1482  /* Transfer watermark Callback */
1483 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1484  hdma2d->LineEventCallback(hdma2d);
1485 #else
1486  HAL_DMA2D_LineEventCallback(hdma2d);
1487 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1488 
1489  }
1490  }
1491  /* Transfer Complete Interrupt management ************************************/
1492  if ((isrflags & DMA2D_FLAG_TC) != 0U)
1493  {
1494  if ((crflags & DMA2D_IT_TC) != 0U)
1495  {
1496  /* Disable the transfer complete interrupt */
1497  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1498 
1499  /* Clear the transfer complete flag */
1500  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1501 
1502  /* Update error code */
1503  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1504 
1505  /* Change DMA2D state */
1506  hdma2d->State = HAL_DMA2D_STATE_READY;
1507 
1508  /* Process Unlocked */
1509  __HAL_UNLOCK(hdma2d);
1510 
1511  if(hdma2d->XferCpltCallback != NULL)
1512  {
1513  /* Transfer complete Callback */
1514  hdma2d->XferCpltCallback(hdma2d);
1515  }
1516  }
1517  }
1518  /* CLUT Transfer Complete Interrupt management ******************************/
1519  if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1520  {
1521  if ((crflags & DMA2D_IT_CTC) != 0U)
1522  {
1523  /* Disable the CLUT transfer complete interrupt */
1524  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1525 
1526  /* Clear the CLUT transfer complete flag */
1527  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1528 
1529  /* Update error code */
1530  hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1531 
1532  /* Change DMA2D state */
1533  hdma2d->State = HAL_DMA2D_STATE_READY;
1534 
1535  /* Process Unlocked */
1536  __HAL_UNLOCK(hdma2d);
1537 
1538  /* CLUT Transfer complete Callback */
1539 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1540  hdma2d->CLUTLoadingCpltCallback(hdma2d);
1541 #else
1542  HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1543 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1544  }
1545  }
1546 
1547 }
1548 
1555 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1556 {
1557  /* Prevent unused argument(s) compilation warning */
1558  UNUSED(hdma2d);
1559 
1560  /* NOTE : This function should not be modified; when the callback is needed,
1561  the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1562  */
1563 }
1564 
1571 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1572 {
1573  /* Prevent unused argument(s) compilation warning */
1574  UNUSED(hdma2d);
1575 
1576  /* NOTE : This function should not be modified; when the callback is needed,
1577  the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1578  */
1579 }
1580 
1614 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1615 {
1616  DMA2D_LayerCfgTypeDef *pLayerCfg;
1617  uint32_t regMask, regValue;
1618 
1619  /* Check the parameters */
1620  assert_param(IS_DMA2D_LAYER(LayerIdx));
1621  assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1622  if(hdma2d->Init.Mode != DMA2D_R2M)
1623  {
1624  assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1625  if(hdma2d->Init.Mode != DMA2D_M2M)
1626  {
1627  assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1628  }
1629  }
1630  assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
1631  assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
1632 
1633  /* Process locked */
1634  __HAL_LOCK(hdma2d);
1635 
1636  /* Change DMA2D peripheral state */
1637  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1638 
1639  pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1640 
1641  /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1642  regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
1643  (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
1644  regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
1645 
1646 
1647  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1648  {
1649  regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1650  }
1651  else
1652  {
1653  regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1654  }
1655 
1656  /* Configure the background DMA2D layer */
1657  if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1658  {
1659  /* Write DMA2D BGPFCCR register */
1660  MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1661 
1662  /* DMA2D BGOR register configuration -------------------------------------*/
1663  WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1664 
1665  /* DMA2D BGCOLR register configuration -------------------------------------*/
1666  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1667  {
1668  WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1669  }
1670  }
1671  /* Configure the foreground DMA2D layer */
1672  else
1673  {
1674 
1675 
1676  /* Write DMA2D FGPFCCR register */
1677  MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1678 
1679  /* DMA2D FGOR register configuration -------------------------------------*/
1680  WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1681 
1682  /* DMA2D FGCOLR register configuration -------------------------------------*/
1683  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1684  {
1685  WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1686  }
1687  }
1688  /* Initialize the DMA2D state*/
1689  hdma2d->State = HAL_DMA2D_STATE_READY;
1690 
1691  /* Process unlocked */
1692  __HAL_UNLOCK(hdma2d);
1693 
1694  return HAL_OK;
1695 }
1696 
1708 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1709 {
1710  /* Check the parameters */
1711  assert_param(IS_DMA2D_LAYER(LayerIdx));
1712  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1713  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1714 
1715  /* Process locked */
1716  __HAL_LOCK(hdma2d);
1717 
1718  /* Change DMA2D peripheral state */
1719  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1720 
1721  /* Configure the CLUT of the background DMA2D layer */
1722  if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1723  {
1724  /* Write background CLUT memory address */
1725  WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1726 
1727  /* Write background CLUT size and CLUT color mode */
1728  MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1729  ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1730  }
1731  /* Configure the CLUT of the foreground DMA2D layer */
1732  else
1733  {
1734  /* Write foreground CLUT memory address */
1735  WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1736 
1737  /* Write foreground CLUT size and CLUT color mode */
1738  MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1739  ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1740  }
1741 
1742  /* Set the DMA2D state to Ready*/
1743  hdma2d->State = HAL_DMA2D_STATE_READY;
1744 
1745  /* Process unlocked */
1746  __HAL_UNLOCK(hdma2d);
1747 
1748  return HAL_OK;
1749 }
1750 
1751 
1762 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1763 {
1764  /* Check the parameters */
1765  assert_param(IS_DMA2D_LINEWATERMARK(Line));
1766 
1767  if (Line > DMA2D_LWR_LW)
1768  {
1769  return HAL_ERROR;
1770  }
1771  else
1772  {
1773  /* Process locked */
1774  __HAL_LOCK(hdma2d);
1775 
1776  /* Change DMA2D peripheral state */
1777  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1778 
1779  /* Sets the Line watermark configuration */
1780  WRITE_REG(hdma2d->Instance->LWR, Line);
1781 
1782  /* Enable the Line interrupt */
1783  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1784 
1785  /* Initialize the DMA2D state*/
1786  hdma2d->State = HAL_DMA2D_STATE_READY;
1787 
1788  /* Process unlocked */
1789  __HAL_UNLOCK(hdma2d);
1790 
1791  return HAL_OK;
1792  }
1793 }
1794 
1800 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1801 {
1802  /* Process Locked */
1803  __HAL_LOCK(hdma2d);
1804 
1805  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1806 
1807  /* Set DMA2D_AMTCR EN bit */
1808  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1809 
1810  hdma2d->State = HAL_DMA2D_STATE_READY;
1811 
1812  /* Process Unlocked */
1813  __HAL_UNLOCK(hdma2d);
1814 
1815  return HAL_OK;
1816 }
1817 
1823 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1824 {
1825  /* Process Locked */
1826  __HAL_LOCK(hdma2d);
1827 
1828  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1829 
1830  /* Clear DMA2D_AMTCR EN bit */
1831  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1832 
1833  hdma2d->State = HAL_DMA2D_STATE_READY;
1834 
1835  /* Process Unlocked */
1836  __HAL_UNLOCK(hdma2d);
1837 
1838  return HAL_OK;
1839 }
1840 
1849 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1850 {
1851  /* Process Locked */
1852  __HAL_LOCK(hdma2d);
1853 
1854  hdma2d->State = HAL_DMA2D_STATE_BUSY;
1855 
1856  /* Set DMA2D_AMTCR DT field */
1857  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
1858 
1859  hdma2d->State = HAL_DMA2D_STATE_READY;
1860 
1861  /* Process Unlocked */
1862  __HAL_UNLOCK(hdma2d);
1863 
1864  return HAL_OK;
1865 }
1866 
1894 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
1895 {
1896  return hdma2d->State;
1897 }
1898 
1905 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
1906 {
1907  return hdma2d->ErrorCode;
1908 }
1909 
1933 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
1934 {
1935  uint32_t tmp;
1936  uint32_t tmp1;
1937  uint32_t tmp2;
1938  uint32_t tmp3;
1939  uint32_t tmp4;
1940 
1941  /* Configure DMA2D data size */
1942  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
1943 
1944  /* Configure DMA2D destination address */
1945  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
1946 
1947  /* Register to memory DMA2D mode selected */
1948  if (hdma2d->Init.Mode == DMA2D_R2M)
1949  {
1950  tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
1951  tmp2 = pdata & DMA2D_OCOLR_RED_1;
1952  tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
1953  tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
1954 
1955  /* Prepare the value to be written to the OCOLR register according to the color mode */
1956  if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
1957  {
1958  tmp = (tmp3 | tmp2 | tmp1| tmp4);
1959  }
1960  else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
1961  {
1962  tmp = (tmp3 | tmp2 | tmp4);
1963  }
1964  else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
1965  {
1966  tmp2 = (tmp2 >> 19U);
1967  tmp3 = (tmp3 >> 10U);
1968  tmp4 = (tmp4 >> 3U );
1969  tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
1970  }
1971  else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
1972  {
1973  tmp1 = (tmp1 >> 31U);
1974  tmp2 = (tmp2 >> 19U);
1975  tmp3 = (tmp3 >> 11U);
1976  tmp4 = (tmp4 >> 3U );
1977  tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
1978  }
1979  else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
1980  {
1981  tmp1 = (tmp1 >> 28U);
1982  tmp2 = (tmp2 >> 20U);
1983  tmp3 = (tmp3 >> 12U);
1984  tmp4 = (tmp4 >> 4U );
1985  tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
1986  }
1987  /* Write to DMA2D OCOLR register */
1988  WRITE_REG(hdma2d->Instance->OCOLR, tmp);
1989  }
1990  else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
1991  {
1992  /* Configure DMA2D source address */
1993  WRITE_REG(hdma2d->Instance->FGMAR, pdata);
1994  }
1995 }
1996 
2008 #endif /* DMA2D */
2009 #endif /* HAL_DMA2D_MODULE_ENABLED */
2010 
2011 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_DMA2D_CallbackIDTypeDef
HAL_DMA2D_CallbackIDTypeDef
HAL DMA2D common Callback ID enumeration definition.
Definition: stm32l4xx_hal_dma2d.h:364
__DMA2D_HandleTypeDef::LayerCfg
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]
Definition: stm32l4xx_hal_dma2d.h:178
DMA2D_LayerCfgTypeDef::InputOffset
uint32_t InputOffset
Definition: stm32l4xx_hal_dma2d.h:115
HAL_DMA2D_MspDeInit
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
DeInitializes the DMA2D MSP.
Definition: stm32l4xx_hal_dma2d.c:429
HAL_DMA2D_GetState
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D state.
Definition: stm32l4xx_hal_dma2d.c:1894
HAL_DMA2D_CLUTLoading_Abort
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Abort the DMA2D CLUT loading.
Definition: stm32l4xx_hal_dma2d.c:1096
HAL_UNLOCKED
Definition: stm32l4xx_hal_def.h:52
HAL_DMA2D_CLUTLoading_Resume
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Resume the DMA2D CLUT loading.
Definition: stm32l4xx_hal_dma2d.c:1214
DMA2D_LayerCfgTypeDef::AlphaMode
uint32_t AlphaMode
Definition: stm32l4xx_hal_dma2d.h:121
HAL_DMA2D_BlendingStart_IT
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer with interrupt enabled.
Definition: stm32l4xx_hal_dma2d.c:787
HAL_DMA2D_CLUTLoading_Suspend
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Suspend the DMA2D CLUT loading.
Definition: stm32l4xx_hal_dma2d.c:1153
HAL_DMA2D_PollForTransfer
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
Polling for transfer complete or CLUT loading.
Definition: stm32l4xx_hal_dma2d.c:1257
HAL_DMA2D_Start_IT
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer with interrupt enabled.
Definition: stm32l4xx_hal_dma2d.c:717
HAL_DMA2D_MspInit
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
Initializes the DMA2D MSP.
Definition: stm32l4xx_hal_dma2d.c:413
__DMA2D_HandleTypeDef
DMA2D handle Structure definition.
Definition: stm32l4xx_hal_dma2d.h:157
DMA2D_InitTypeDef::LineOffsetMode
uint32_t LineOffsetMode
Definition: stm32l4xx_hal_dma2d.h:103
HAL_DMA2D_Start
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the DMA2D Transfer.
Definition: stm32l4xx_hal_dma2d.c:683
HAL_DMA2D_STATE_ERROR
Definition: stm32l4xx_hal_dma2d.h:150
HAL_DMA2D_Resume
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
Resume the DMA2D Transfer.
Definition: stm32l4xx_hal_dma2d.c:918
stm32l4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
DMA2D_CLUTCfgTypeDef
DMA2D CLUT Structure definition.
Definition: stm32l4xx_hal_dma2d.h:65
HAL_DMA2D_Init
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
Initialize the DMA2D according to the specified parameters in the DMA2D_InitTypeDef and create the as...
Definition: stm32l4xx_hal_dma2d.c:237
HAL_DMA2D_TRANSFERCOMPLETE_CB_ID
Definition: stm32l4xx_hal_dma2d.h:368
HAL_DMA2D_ConfigLayer
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Configure the DMA2D Layer according to the specified parameters in the DMA2D_HandleTypeDef.
Definition: stm32l4xx_hal_dma2d.c:1614
HAL_DMA2D_BlendingStart
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Start the multi-source DMA2D Transfer.
Definition: stm32l4xx_hal_dma2d.c:752
HAL_DMA2D_Suspend
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
Suspend the DMA2D Transfer.
Definition: stm32l4xx_hal_dma2d.c:869
DMA2D_LayerCfgTypeDef::RedBlueSwap
uint32_t RedBlueSwap
Definition: stm32l4xx_hal_dma2d.h:135
__DMA2D_HandleTypeDef::Instance
DMA2D_TypeDef * Instance
Definition: stm32l4xx_hal_dma2d.h:159
__DMA2D_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32l4xx_hal_dma2d.h:184
DMA2D_InitTypeDef::RedBlueSwap
uint32_t RedBlueSwap
Definition: stm32l4xx_hal_dma2d.h:92
__DMA2D_HandleTypeDef::MspDeInitCallback
void(* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d)
Definition: stm32l4xx_hal_dma2d.h:174
__DMA2D_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32l4xx_hal_dma2d.h:180
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
pDMA2D_CallbackTypeDef
void(* pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d)
HAL DMA2D Callback pointer definition.
Definition: stm32l4xx_hal_dma2d.h:191
HAL_DMA2D_EnableDeadTime
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
Enable DMA2D dead time feature.
Definition: stm32l4xx_hal_dma2d.c:1800
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
DMA2D_InitTypeDef::Mode
uint32_t Mode
Definition: stm32l4xx_hal_dma2d.h:81
DMA2D_CLUTCfgTypeDef::CLUTColorMode
uint32_t CLUTColorMode
Definition: stm32l4xx_hal_dma2d.h:69
HAL_DMA2D_DeInit
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
Deinitializes the DMA2D peripheral registers to their default reset values.
Definition: stm32l4xx_hal_dma2d.c:323
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
HAL_DMA2D_TRANSFERERROR_CB_ID
Definition: stm32l4xx_hal_dma2d.h:369
HAL_DMA2D_ProgramLineEvent
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
Configure the line watermark.
Definition: stm32l4xx_hal_dma2d.c:1762
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_DMA2D_DisableDeadTime
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
Disable DMA2D dead time feature.
Definition: stm32l4xx_hal_dma2d.c:1823
HAL_DMA2D_ConfigCLUT
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Configure the DMA2D CLUT Transfer.
Definition: stm32l4xx_hal_dma2d.c:1708
DMA2D_LayerCfgTypeDef::AlphaInverted
uint32_t AlphaInverted
Definition: stm32l4xx_hal_dma2d.h:132
HAL_DMA2D_UnRegisterCallback
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
Unregister a DMA2D Callback DMA2D Callback is redirected to the weak (surcharged) predefined callback...
Definition: stm32l4xx_hal_dma2d.c:553
HAL_DMA2D_STATE_SUSPEND
Definition: stm32l4xx_hal_dma2d.h:151
__DMA2D_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d)
Definition: stm32l4xx_hal_dma2d.h:165
DMA2D_CLUTCfgTypeDef::Size
uint32_t Size
Definition: stm32l4xx_hal_dma2d.h:72
HAL_DMA2D_LineEventCallback
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
Transfer watermark callback.
Definition: stm32l4xx_hal_dma2d.c:1555
HAL_DMA2D_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_dma2d.h:367
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
DMA2D_InitTypeDef::ColorMode
uint32_t ColorMode
Definition: stm32l4xx_hal_dma2d.h:84
DMA2D_InitTypeDef::BytesSwap
uint32_t BytesSwap
Definition: stm32l4xx_hal_dma2d.h:98
HAL_DMA2D_IRQHandler
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
Handle DMA2D interrupt request.
Definition: stm32l4xx_hal_dma2d.c:1385
DMA2D_LayerCfgTypeDef::InputColorMode
uint32_t InputColorMode
Definition: stm32l4xx_hal_dma2d.h:118
DMA2D_LayerCfgTypeDef
DMA2D Layer structure definition.
Definition: stm32l4xx_hal_dma2d.h:113
DMA2D_CLUTCfgTypeDef::pCLUT
uint32_t * pCLUT
Definition: stm32l4xx_hal_dma2d.h:67
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID
Definition: stm32l4xx_hal_dma2d.h:371
HAL_DMA2D_LINEEVENT_CB_ID
Definition: stm32l4xx_hal_dma2d.h:370
HAL_DMA2D_CLUTLoad
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading.
Definition: stm32l4xx_hal_dma2d.c:984
HAL_DMA2D_ConfigDeadTime
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
Configure dead time.
Definition: stm32l4xx_hal_dma2d.c:1849
HAL_DMA2D_STATE_TIMEOUT
Definition: stm32l4xx_hal_dma2d.h:149
DMA2D_LayerCfgTypeDef::InputAlpha
uint32_t InputAlpha
Definition: stm32l4xx_hal_dma2d.h:124
HAL_DMA2D_StateTypeDef
HAL_DMA2D_StateTypeDef
HAL DMA2D State structures definition.
Definition: stm32l4xx_hal_dma2d.h:144
DMA2D_InitTypeDef::OutputOffset
uint32_t OutputOffset
Definition: stm32l4xx_hal_dma2d.h:87
DMA2D_SetConfig
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
Set the DMA2D transfer parameters.
Definition: stm32l4xx_hal_dma2d.c:1933
HAL_DMA2D_STATE_BUSY
Definition: stm32l4xx_hal_dma2d.h:148
HAL_DMA2D_MSPINIT_CB_ID
Definition: stm32l4xx_hal_dma2d.h:366
HAL_DMA2D_GetError
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
Return the DMA2D error code.
Definition: stm32l4xx_hal_dma2d.c:1905
DMA2D_InitTypeDef::AlphaInverted
uint32_t AlphaInverted
Definition: stm32l4xx_hal_dma2d.h:89
HAL_DMA2D_STATE_READY
Definition: stm32l4xx_hal_dma2d.h:147
__DMA2D_HandleTypeDef::Init
DMA2D_InitTypeDef Init
Definition: stm32l4xx_hal_dma2d.h:161
__DMA2D_HandleTypeDef::State
__IO HAL_DMA2D_StateTypeDef State
Definition: stm32l4xx_hal_dma2d.h:182
__DMA2D_HandleTypeDef::MspInitCallback
void(* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d)
Definition: stm32l4xx_hal_dma2d.h:172
__DMA2D_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d)
Definition: stm32l4xx_hal_dma2d.h:163
HAL_DMA2D_CLUTLoad_IT
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
Start DMA2D CLUT Loading with interrupt enabled.
Definition: stm32l4xx_hal_dma2d.c:1038
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)
HAL_DMA2D_CLUTLoadingCpltCallback
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
CLUT Transfer Complete callback.
Definition: stm32l4xx_hal_dma2d.c:1571
__DMA2D_HandleTypeDef::LineEventCallback
void(* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d)
Definition: stm32l4xx_hal_dma2d.h:168
HAL_DMA2D_RegisterCallback
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
Register a User DMA2D Callback To be used instead of the weak (surcharged) predefined callback...
Definition: stm32l4xx_hal_dma2d.c:456
__DMA2D_HandleTypeDef::CLUTLoadingCpltCallback
void(* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d)
Definition: stm32l4xx_hal_dma2d.h:170
HAL_DMA2D_Abort
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
Abort the DMA2D Transfer.
Definition: stm32l4xx_hal_dma2d.c:820
HAL_DMA2D_EnableCLUT
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
Enable the DMA2D CLUT Transfer.
Definition: stm32l4xx_hal_dma2d.c:946
HAL_DMA2D_STATE_RESET
Definition: stm32l4xx_hal_dma2d.h:146
assert_param
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock))