FMC Low Layer Exported Types

Data Structures
struct	FMC_NORSRAM_InitTypeDef
	FMC NORSRAM Configuration Structure definition. More...
struct	FMC_NORSRAM_TimingTypeDef
	FMC NORSRAM Timing parameters structure definition. More...
struct	FMC_NAND_InitTypeDef
	FMC NAND Configuration Structure definition. More...
struct	FMC_NAND_PCC_TimingTypeDef
	FMC NAND Timing parameters structure definition. More...

Detailed Description

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Data Structure Documentation

FMC_NORSRAM_InitTypeDef

struct FMC_NORSRAM_InitTypeDef

FMC NORSRAM Configuration Structure definition.

Definition at line 161 of file stm32l4xx_ll_fmc.h.

Data Fields
uint32_t	AsynchronousWait	Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of FMC Asynchronous Wait
uint32_t	BurstAccessMode	Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of FMC Burst Access Mode
uint32_t	ContinuousClock	Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. This parameter can be a value of FMC Continuous Clock
uint32_t	DataAddressMux	Specifies whether the address and data values are multiplexed on the data bus or not. This parameter can be a value of FMC Data Address Bus Multiplexing
uint32_t	ExtendedMode	Enables or disables the extended mode. This parameter can be a value of FMC Extended Mode
uint32_t	MemoryDataWidth	Specifies the external memory device width. This parameter can be a value of FMC NOR/SRAM Data Width
uint32_t	MemoryType	Specifies the type of external memory attached to the corresponding memory device. This parameter can be a value of FMC Memory Type
uint32_t	NBLSetupTime	Specifies the NBL setup timing clock cycle number This parameter can be a value of FMC Byte Lane(NBL) Setup
uint32_t	NSBank	Specifies the NORSRAM memory device that will be used. This parameter can be a value of FMC NOR/SRAM Bank
uint32_t	PageSize	Specifies the memory page size. This parameter can be a value of FMC Page Size
uint32_t	WaitSignal	Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of FMC Wait Signal
uint32_t	WaitSignalActive	Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of FMC Wait Timing
uint32_t	WaitSignalPolarity	Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of FMC Wait Signal Polarity
uint32_t	WriteBurst	Enables or disables the write burst operation. This parameter can be a value of FMC Write Burst
uint32_t	WriteFifo	Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. This parameter can be a value of FMC Write FIFO. Note This Parameter is not available for STM32L47x/L48x devices.
uint32_t	WriteOperation	Enables or disables the write operation in the selected device by the FMC. This parameter can be a value of FMC Write Operation

FMC_NORSRAM_TimingTypeDef

struct FMC_NORSRAM_TimingTypeDef

FMC NORSRAM Timing parameters structure definition.

Definition at line 231 of file stm32l4xx_ll_fmc.h.

Data Fields
uint32_t	AccessMode	Specifies the asynchronous access mode. This parameter can be a value of FMC Access Mode
uint32_t	AddressHoldTime	Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. Note This parameter is not used with synchronous NOR Flash memories.
uint32_t	AddressSetupTime	Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. Note This parameter is not used with synchronous NOR Flash memories.
uint32_t	BusTurnAroundDuration	Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. Note This parameter is only used for multiplexed NOR Flash memories.
uint32_t	CLKDivision	Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. Note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses.
uint32_t	DataHoldTime	Defines the number of HCLK cycles to configure the duration of the data hold time. This parameter can be a value between Min_Data = 0 and Max_Data = 3. Note This parameter is used for used in asynchronous accesses.
uint32_t	DataLatency	Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: It must be set to 0 in case of a CRAM It is don't care in asynchronous NOR, SRAM or ROM accesses It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories with synchronous burst mode enable
uint32_t	DataSetupTime	Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. Note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories.

FMC_NAND_InitTypeDef

struct FMC_NAND_InitTypeDef

FMC NAND Configuration Structure definition.

Definition at line 283 of file stm32l4xx_ll_fmc.h.

Data Fields
uint32_t	EccComputation	Enables or disables the ECC computation. This parameter can be any value of FMC ECC
uint32_t	ECCPageSize	Defines the page size for the extended ECC. This parameter can be any value of FMC ECC Page Size
uint32_t	MemoryDataWidth	Specifies the external memory device width. This parameter can be any value of FMC NAND Data Width
uint32_t	NandBank	Specifies the NAND memory device that will be used. This parameter can be a value of FMC NAND Bank
uint32_t	TARSetupTime	Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255
uint32_t	TCLRSetupTime	Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between Min_Data = 0 and Max_Data = 255
uint32_t	Waitfeature	Enables or disables the Wait feature for the NAND Memory device. This parameter can be any value of FMC Wait feature

FMC_NAND_PCC_TimingTypeDef

struct FMC_NAND_PCC_TimingTypeDef

FMC NAND Timing parameters structure definition.

Definition at line 312 of file stm32l4xx_ll_fmc.h.

Data Fields
uint32_t	HiZSetupTime	Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254
uint32_t	HoldSetupTime	Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254
uint32_t	SetupTime	Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between Min_Data = 0 and Max_Data = 254
uint32_t	WaitSetupTime	Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254