stm32l4xx_ll_fmc.h

Go to the documentation of this file.

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_LL_FMC_H
#define __STM32L4xx_LL_FMC_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"

#if defined(FMC_BANK1)

#define IS_FMC_NORSRAM_BANK(__BANK__)                (((__BANK__) == FMC_NORSRAM_BANK1)                || \
                                                      ((__BANK__) == FMC_NORSRAM_BANK2)                || \
                                                      ((__BANK__) == FMC_NORSRAM_BANK3)                || \
                                                      ((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__)                          (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE)      || \
                                                      ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__)                    (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM)           || \
                                                      ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)          || \
                                                      ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__)       (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)     || \
                                                      ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16)    || \
                                                      ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_PAGESIZE(__SIZE__)                    (((__SIZE__) == FMC_PAGE_SIZE_NONE)               || \
                                                      ((__SIZE__) == FMC_PAGE_SIZE_128)                || \
                                                      ((__SIZE__) == FMC_PAGE_SIZE_256)                || \
                                                      ((__SIZE__) == FMC_PAGE_SIZE_512)                || \
                                                      ((__SIZE__) == FMC_PAGE_SIZE_1024))
#if defined(FMC_BCR1_WFDIS)
#define IS_FMC_WRITE_FIFO(__FIFO__)                  (((__FIFO__) == FMC_WRITE_FIFO_DISABLE)           || \
                                                      ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
#endif /* FMC_BCR1_WFDIS */
#define IS_FMC_ACCESS_MODE(__MODE__)                 (((__MODE__) == FMC_ACCESS_MODE_A)                || \
                                                      ((__MODE__) == FMC_ACCESS_MODE_B)                || \
                                                      ((__MODE__) == FMC_ACCESS_MODE_C)                || \
                                                      ((__MODE__) == FMC_ACCESS_MODE_D))
#if defined(FMC_BCRx_NBLSET)
#define IS_FMC_NBL_SETUPTIME(__NBL__)                (((__NBL__) == FMC_NBL_SETUPTIME_0)               || \
                                                      ((__NBL__) == FMC_NBL_SETUPTIME_1)               || \
                                                      ((__NBL__) == FMC_NBL_SETUPTIME_2)               || \
                                                      ((__NBL__) == FMC_NBL_SETUPTIME_3))
#endif /* FMC_BCRx_NBLSET */
#define IS_FMC_BURSTMODE(__STATE__)                  (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE)   || \
                                                      ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__)           (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
                                                      ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__)        (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS)      || \
                                                      ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__)        (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
                                                      ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__)              (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE)        || \
                                                      ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__)               (((__MODE__) == FMC_EXTENDED_MODE_DISABLE)        || \
                                                      ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__)                   (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE)   || \
                                                      ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__)             (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
#define IS_FMC_WRITE_BURST(__BURST__)                (((__BURST__) == FMC_WRITE_BURST_DISABLE)         || \
                                                      ((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__)           (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
                                                      ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__)          ((__TIME__) <= 15)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__)           (((__TIME__) > 0) && ((__TIME__) <= 15))
#define IS_FMC_DATASETUP_TIME(__TIME__)              (((__TIME__) > 0) && ((__TIME__) <= 255))
#if defined(FMC_BTRx_DATAHLD)
#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__)       ((__DATAHOLD__) <= 3)
#endif /* FMC_BTRx_DATAHLD */
#define IS_FMC_TURNAROUND_TIME(__TIME__)             ((__TIME__) <= 15)
#define IS_FMC_CLK_DIV(__DIV__)                      (((__DIV__) > 1) && ((__DIV__) <= 16))
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__)          ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)

#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)

#define IS_FMC_NAND_BANK(__BANK__)          ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__)    (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
                                             ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8)        || \
                                             ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__)         (((__STATE__) == FMC_NAND_ECC_DISABLE)            || \
                                             ((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__)       (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)   || \
                                             ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)   || \
                                             ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE)  || \
                                             ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE)  || \
                                             ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE)  || \
                                             ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_TCLR_TIME(__TIME__)          ((__TIME__) <= 255)
#define IS_FMC_TAR_TIME(__TIME__)           ((__TIME__) <= 255)
#define IS_FMC_SETUP_TIME(__TIME__)         ((__TIME__) <= 254)
#define IS_FMC_WAIT_TIME(__TIME__)          ((__TIME__) <= 254)
#define IS_FMC_HOLD_TIME(__TIME__)          ((__TIME__) <= 254)
#define IS_FMC_HIZ_TIME(__TIME__)           ((__TIME__) <= 254)
#define IS_FMC_NAND_DEVICE(__INSTANCE__)    ((__INSTANCE__) == FMC_NAND_DEVICE)

#endif /* FMC_BANK3 */

/* Exported typedef ----------------------------------------------------------*/

#if defined(FMC_BANK1)
#define FMC_NORSRAM_TypeDef           FMC_Bank1_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef  FMC_Bank1E_TypeDef
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_TypeDef              FMC_Bank3_TypeDef
#endif /* FMC_BANK3 */

#if defined(FMC_BANK1)
#define FMC_NORSRAM_DEVICE            FMC_Bank1_R
#define FMC_NORSRAM_EXTENDED_DEVICE   FMC_Bank1E_R
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_DEVICE               FMC_Bank3_R
#endif /* FMC_BANK3 */

#if defined(FMC_BANK1)

typedef struct
{
  uint32_t NSBank;                       
  uint32_t DataAddressMux;               
  uint32_t MemoryType;                   
  uint32_t MemoryDataWidth;              
  uint32_t BurstAccessMode;              
  uint32_t WaitSignalPolarity;           
  uint32_t WaitSignalActive;             
  uint32_t WriteOperation;               
  uint32_t WaitSignal;                   
  uint32_t ExtendedMode;                 
  uint32_t AsynchronousWait;             
  uint32_t WriteBurst;                   
  uint32_t ContinuousClock;              
  uint32_t WriteFifo;                    
  uint32_t PageSize;                     
#if defined(FMC_BCRx_NBLSET)
  uint32_t NBLSetupTime;                 
#endif /* FMC_BCRx_NBLSET */

}FMC_NORSRAM_InitTypeDef;

typedef struct
{
  uint32_t AddressSetupTime;             
  uint32_t AddressHoldTime;              
  uint32_t DataSetupTime;                
#if defined(FMC_BTRx_DATAHLD)
  uint32_t DataHoldTime;                 
#endif /* FMC_BTRx_DATAHLD */

  uint32_t BusTurnAroundDuration;        
  uint32_t CLKDivision;                  
  uint32_t DataLatency;                  
  uint32_t AccessMode;                   
}FMC_NORSRAM_TimingTypeDef;
#endif /* FMC_BANK1 */

#if defined(FMC_BANK3)

typedef struct
{
  uint32_t NandBank;               
  uint32_t Waitfeature;            
  uint32_t MemoryDataWidth;        
  uint32_t EccComputation;         
  uint32_t ECCPageSize;            
  uint32_t TCLRSetupTime;          
  uint32_t TARSetupTime;           
}FMC_NAND_InitTypeDef;

typedef struct
{
  uint32_t SetupTime;            
  uint32_t WaitSetupTime;        
  uint32_t HoldSetupTime;        
  uint32_t HiZSetupTime;         
}FMC_NAND_PCC_TimingTypeDef;
#endif /* FMC_BANK3 */

/* Exported constants --------------------------------------------------------*/
#if defined(FMC_BANK1)

#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000U)
#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002U)
#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004U)
#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006U)

#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FMC_BCRx_MUXEN)

#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FMC_BCRx_MTYP_0)
#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)FMC_BCRx_MTYP_1)

#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FMC_BCRx_MWID_0)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FMC_BCRx_MWID_1)

#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FMC_BCRx_FACCEN)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000U)

#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FMC_BCRx_BURSTEN)

#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FMC_BCRx_WAITPOL)

#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)FMC_BCRx_WAITCFG)

#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)FMC_BCRx_WREN)

#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FMC_BCRx_WAITEN)

#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)FMC_BCRx_EXTMOD)

#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FMC_BCRx_ASYNCWAIT)

#define FMC_PAGE_SIZE_NONE                      ((uint32_t)0x00000000U)
#define FMC_PAGE_SIZE_128                       ((uint32_t)FMC_BCRx_CPSIZE_0)
#define FMC_PAGE_SIZE_256                       ((uint32_t)FMC_BCRx_CPSIZE_1)
#define FMC_PAGE_SIZE_512                       ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
#define FMC_PAGE_SIZE_1024                      ((uint32_t)FMC_BCRx_CPSIZE_2)

#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000U)
#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)FMC_BCRx_CBURSTRW)

#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)FMC_BCR1_CCLKEN)

#if defined(FMC_BCR1_WFDIS)

#define FMC_WRITE_FIFO_DISABLE                  ((uint32_t)FMC_BCR1_WFDIS)
#define FMC_WRITE_FIFO_ENABLE                   ((uint32_t)0x00000000U)

#endif /* FMC_BCR1_WFDIS */

#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000U)
#define FMC_ACCESS_MODE_B                        ((uint32_t)FMC_BTRx_ACCMOD_0)
#define FMC_ACCESS_MODE_C                        ((uint32_t)FMC_BTRx_ACCMOD_1)
#define FMC_ACCESS_MODE_D                        ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))

#if defined(FMC_BCRx_NBLSET)

#define FMC_NBL_SETUPTIME_0                     ((uint32_t)0x00000000U)
#define FMC_NBL_SETUPTIME_1                     ((uint32_t)FMC_BCRx_NBLSET_0)
#define FMC_NBL_SETUPTIME_2                     ((uint32_t)FMC_BCRx_NBLSET_1)
#define FMC_NBL_SETUPTIME_3                     ((uint32_t)(FMC_BCRx_NBLSET_0 | FMC_BCRx_NBLSET_1))

#endif /* FMC_BCRx_NBLSET */

#endif /* FMC_BANK1 */

#if defined(FMC_BANK3)

#define FMC_NAND_BANK3                          ((uint32_t)0x00000100U)

#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000U)
#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)FMC_PCR_PWAITEN)

#define FMC_PCR_MEMORY_TYPE_NAND                ((uint32_t)FMC_PCR_PTYP)

#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000U)
#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)FMC_PCR_PWID_0)

#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_ENABLE                     ((uint32_t)FMC_PCR_ECCEN)

#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FMC_PCR_ECCPS_0)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FMC_PCR_ECCPS_1)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FMC_PCR_ECCPS_2)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2)

#endif /* FMC_BANK3 */


#if defined(FMC_BANK3)
#define FMC_IT_RISING_EDGE                      ((uint32_t)FMC_SR_IREN)
#define FMC_IT_LEVEL                            ((uint32_t)FMC_SR_ILEN)
#define FMC_IT_FALLING_EDGE                     ((uint32_t)FMC_SR_IFEN)
#endif /* FMC_BANK3 */

#if defined(FMC_BANK3)
#define FMC_FLAG_RISING_EDGE                    ((uint32_t)FMC_SR_IRS)
#define FMC_FLAG_LEVEL                          ((uint32_t)FMC_SR_ILS)
#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)FMC_SR_IFS)
#define FMC_FLAG_FEMPT                          ((uint32_t)FMC_SR_FEMPT)
#endif /* FMC_BANK3 */

/* Private macro -------------------------------------------------------------*/
#if defined(FMC_BANK1)

#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)

#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)

#endif /* FMC_BANK1 */

#if defined(FMC_BANK3)

#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)

#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)

#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR |= (__INTERRUPT__))

#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR &= ~(__INTERRUPT__))

#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))

#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR &= ~(__FLAG__))

#endif /* FMC_BANK3 */

/* Private functions ---------------------------------------------------------*/
#if defined(FMC_BANK1)

HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
#endif /* FMC_BANK1 */

#if defined(FMC_BANK3)

HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
#endif /* FMC_BANK3 */



#ifdef __cplusplus
}
#endif

#endif /* __STM32L4xx_LL_FMC_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/