PLL

Functions
__STATIC_INLINE void	LL_RCC_PLL_Enable (void)
	Enable PLL CR PLLON LL_RCC_PLL_Enable. More...
__STATIC_INLINE void	LL_RCC_PLL_Disable (void)
	Disable PLL. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_IsReady (void)
	Check if PLL Ready CR PLLRDY LL_RCC_PLL_IsReady. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLL used for SYSCLK Domain. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLL used for SAI domain clock. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLL used for 48Mhz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
	Configure PLL clock source PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetMainSource (void)
	Get the oscillator used as PLL clock source. PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetN (void)
	Get Main PLL multiplication factor for VCO PLLCFGR PLLN LL_RCC_PLL_GetN. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetP (void)
	Get Main PLL division factor for PLLP. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetQ (void)
	Get Main PLL division factor for PLLQ. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetR (void)
	Get Main PLL division factor for PLLR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetDivider (void)
	Get Division factor for the main PLL and other PLL PLLCFGR PLLM LL_RCC_PLL_GetDivider. More...
__STATIC_INLINE void	LL_RCC_PLL_EnableDomain_SAI (void)
	Enable PLL output mapped on SAI domain clock PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI. More...
__STATIC_INLINE void	LL_RCC_PLL_DisableDomain_SAI (void)
	Disable PLL output mapped on SAI domain clock. More...
__STATIC_INLINE void	LL_RCC_PLL_EnableDomain_48M (void)
	Enable PLL output mapped on 48MHz domain clock PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M. More...
__STATIC_INLINE void	LL_RCC_PLL_DisableDomain_48M (void)
	Disable PLL output mapped on 48MHz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLL_EnableDomain_SYS (void)
	Enable PLL output mapped on SYSCLK domain PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS. More...
__STATIC_INLINE void	LL_RCC_PLL_DisableDomain_SYS (void)
	Disable PLL output mapped on SYSCLK domain. More...

Detailed Description

Function Documentation

LL_RCC_PLL_ConfigDomain_48M()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ
	)

Configure PLL used for 48Mhz domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLN/PLLQ can be written only when PLL is disabled.

This can be selected for USB, RNG, SDMMC PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 (*) LL_RCC_PLLM_DIV_10 (*) LL_RCC_PLLM_DIV_11 (*) LL_RCC_PLLM_DIV_12 (*) LL_RCC_PLLM_DIV_13 (*) LL_RCC_PLLM_DIV_14 (*) LL_RCC_PLLM_DIV_15 (*) LL_RCC_PLLM_DIV_16 (*) (*) value not defined in all devices.
PLLN	Between 8 and 86
PLLQ	This parameter can be one of the following values: LL_RCC_PLLQ_DIV_2 LL_RCC_PLLQ_DIV_4 LL_RCC_PLLQ_DIV_6 LL_RCC_PLLQ_DIV_8

Return values

None

Definition at line 3960 of file stm32l4xx_ll_rcc.h.

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
}

LL_RCC_PLL_ConfigDomain_SAI()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP
	)

Configure PLL used for SAI domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLN/PLLP can be written only when PLL is disabled.

This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 (*) LL_RCC_PLLM_DIV_10 (*) LL_RCC_PLLM_DIV_11 (*) LL_RCC_PLLM_DIV_12 (*) LL_RCC_PLLM_DIV_13 (*) LL_RCC_PLLM_DIV_14 (*) LL_RCC_PLLM_DIV_15 (*) LL_RCC_PLLM_DIV_16 (*) (*) value not defined in all devices.
PLLN	Between 8 and 86
PLLP	This parameter can be one of the following values: LL_RCC_PLLP_DIV_2 LL_RCC_PLLP_DIV_3 LL_RCC_PLLP_DIV_4 LL_RCC_PLLP_DIV_5 LL_RCC_PLLP_DIV_6 LL_RCC_PLLP_DIV_7 LL_RCC_PLLP_DIV_8 LL_RCC_PLLP_DIV_9 LL_RCC_PLLP_DIV_10 LL_RCC_PLLP_DIV_11 LL_RCC_PLLP_DIV_12 LL_RCC_PLLP_DIV_13 LL_RCC_PLLP_DIV_14 LL_RCC_PLLP_DIV_15 LL_RCC_PLLP_DIV_16 LL_RCC_PLLP_DIV_17 LL_RCC_PLLP_DIV_18 LL_RCC_PLLP_DIV_19 LL_RCC_PLLP_DIV_20 LL_RCC_PLLP_DIV_21 LL_RCC_PLLP_DIV_22 LL_RCC_PLLP_DIV_23 LL_RCC_PLLP_DIV_24 LL_RCC_PLLP_DIV_25 LL_RCC_PLLP_DIV_26 LL_RCC_PLLP_DIV_27 LL_RCC_PLLP_DIV_28 LL_RCC_PLLP_DIV_29 LL_RCC_PLLP_DIV_30 LL_RCC_PLLP_DIV_31

Return values

None	Configure PLL used for SAI domain clock

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLN/PLLP can be written only when PLL is disabled.

This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86
PLLP	This parameter can be one of the following values: LL_RCC_PLLP_DIV_7 LL_RCC_PLLP_DIV_17

Return values

None

Definition at line 3906 of file stm32l4xx_ll_rcc.h.

{
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
#else
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
}

LL_RCC_PLL_ConfigDomain_SYS()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLL used for SYSCLK Domain.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLN/PLLR can be written only when PLL is disabled. PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 (*) LL_RCC_PLLM_DIV_10 (*) LL_RCC_PLLM_DIV_11 (*) LL_RCC_PLLM_DIV_12 (*) LL_RCC_PLLM_DIV_13 (*) LL_RCC_PLLM_DIV_14 (*) LL_RCC_PLLM_DIV_15 (*) LL_RCC_PLLM_DIV_16 (*) (*) value not defined in all devices.
PLLN	Between 8 and 86
PLLR	This parameter can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_8

Return values

None

Definition at line 3798 of file stm32l4xx_ll_rcc.h.

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
}

LL_RCC_PLL_Disable()

__STATIC_INLINE void LL_RCC_PLL_Disable

(

void

)

Disable PLL.

Note

Cannot be disabled if the PLL clock is used as the system clock CR PLLON LL_RCC_PLL_Disable

Return values

None

Definition at line 3742 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
}

LL_RCC_PLL_DisableDomain_48M()

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M

(

void

)

Disable PLL output mapped on 48MHz domain clock.

Note

Cannot be disabled if the PLL clock is used as the system clock

In order to save power, when the PLLCLK of the PLL is not used, should be 0 PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M

Return values

None

Definition at line 4166 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
}

LL_RCC_PLL_DisableDomain_SAI()

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI

(

void

)

Disable PLL output mapped on SAI domain clock.

Note

Cannot be disabled if the PLL clock is used as the system clock

In order to save power, when the PLLCLK of the PLL is not used, should be 0 PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI

Return values

None

Definition at line 4141 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
}

LL_RCC_PLL_DisableDomain_SYS()

__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS

(

void

)

Disable PLL output mapped on SYSCLK domain.

Note

Cannot be disabled if the PLL clock is used as the system clock

In order to save power, when the PLLCLK of the PLL is not used, Main PLL should be 0 PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS

Return values

None

Definition at line 4190 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
}

LL_RCC_PLL_Enable()

__STATIC_INLINE void LL_RCC_PLL_Enable

(

void

)

Enable PLL CR PLLON LL_RCC_PLL_Enable.

Return values

None

Definition at line 3731 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->CR, RCC_CR_PLLON);
}

LL_RCC_PLL_EnableDomain_48M()

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M

(

void

)

Enable PLL output mapped on 48MHz domain clock PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M.

Return values

None

Definition at line 4152 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
}

LL_RCC_PLL_EnableDomain_SAI()

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI

(

void

)

Enable PLL output mapped on SAI domain clock PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI.

Return values

None

Definition at line 4127 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
}

LL_RCC_PLL_EnableDomain_SYS()

__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS

(

void

)

Enable PLL output mapped on SYSCLK domain PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS.

Return values

None

Definition at line 4176 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
}

LL_RCC_PLL_GetDivider()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider

(

void

)

Get Division factor for the main PLL and other PLL PLLCFGR PLLM LL_RCC_PLL_GetDivider.

Return values

Returned

value can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 (*) LL_RCC_PLLM_DIV_10 (*) LL_RCC_PLLM_DIV_11 (*) LL_RCC_PLLM_DIV_12 (*) LL_RCC_PLLM_DIV_13 (*) LL_RCC_PLLM_DIV_14 (*) LL_RCC_PLLM_DIV_15 (*) LL_RCC_PLLM_DIV_16 (*) (*) value not defined in all devices.

Definition at line 4116 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
}

LL_RCC_PLL_GetMainSource()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource

(

void

)

Get the oscillator used as PLL clock source. PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource.

Return values

Returned

value can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE

Definition at line 3990 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
}

LL_RCC_PLL_GetN()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetN

(

void

)

Get Main PLL multiplication factor for VCO PLLCFGR PLLN LL_RCC_PLL_GetN.

Return values

Between

8 and 86

Definition at line 4000 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
}

LL_RCC_PLL_GetP()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetP

(

void

)

Get Main PLL division factor for PLLP.

Note

Used for PLLSAI3CLK (SAI1 and SAI2 clock) PLLCFGR PLLPDIV LL_RCC_PLL_GetP

Return values

Returned

value can be one of the following values: LL_RCC_PLLP_DIV_2 LL_RCC_PLLP_DIV_3 LL_RCC_PLLP_DIV_4 LL_RCC_PLLP_DIV_5 LL_RCC_PLLP_DIV_6 LL_RCC_PLLP_DIV_7 LL_RCC_PLLP_DIV_8 LL_RCC_PLLP_DIV_9 LL_RCC_PLLP_DIV_10 LL_RCC_PLLP_DIV_11 LL_RCC_PLLP_DIV_12 LL_RCC_PLLP_DIV_13 LL_RCC_PLLP_DIV_14 LL_RCC_PLLP_DIV_15 LL_RCC_PLLP_DIV_16 LL_RCC_PLLP_DIV_17 LL_RCC_PLLP_DIV_18 LL_RCC_PLLP_DIV_19 LL_RCC_PLLP_DIV_20 LL_RCC_PLLP_DIV_21 LL_RCC_PLLP_DIV_22 LL_RCC_PLLP_DIV_23 LL_RCC_PLLP_DIV_24 LL_RCC_PLLP_DIV_25 LL_RCC_PLLP_DIV_26 LL_RCC_PLLP_DIV_27 LL_RCC_PLLP_DIV_28 LL_RCC_PLLP_DIV_29 LL_RCC_PLLP_DIV_30 LL_RCC_PLLP_DIV_31

Note

Used for PLLSAI3CLK (SAI1 and SAI2 clock) PLLCFGR PLLP LL_RCC_PLL_GetP

Return values

Returned

value can be one of the following values: LL_RCC_PLLP_DIV_7 LL_RCC_PLLP_DIV_17

Definition at line 4043 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
}

LL_RCC_PLL_GetQ()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ

(

void

)

Get Main PLL division factor for PLLQ.

Note

Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) PLLCFGR PLLQ LL_RCC_PLL_GetQ

Return values

Returned

value can be one of the following values: LL_RCC_PLLQ_DIV_2 LL_RCC_PLLQ_DIV_4 LL_RCC_PLLQ_DIV_6 LL_RCC_PLLQ_DIV_8

Definition at line 4073 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
}

LL_RCC_PLL_GetR()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetR

(

void

)

Get Main PLL division factor for PLLR.

Note

Used for PLLCLK (system clock) PLLCFGR PLLR LL_RCC_PLL_GetR

Return values

Returned

value can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_8

Definition at line 4088 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
}

LL_RCC_PLL_IsReady()

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady

(

void

)

Check if PLL Ready CR PLLRDY LL_RCC_PLL_IsReady.

Return values

State

of bit (1 or 0).

Definition at line 3752 of file stm32l4xx_ll_rcc.h.

{
  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
}

LL_RCC_PLL_SetMainSource()

__STATIC_INLINE void LL_RCC_PLL_SetMainSource

(

uint32_t

PLLSource

)

Configure PLL clock source PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource.

Parameters

PLLSource

This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE

Return values

None

Definition at line 3976 of file stm32l4xx_ll_rcc.h.

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
}