STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_ll_rcc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_RCC_H
22 #define STM32L4xx_LL_RCC_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30 
35 #if defined(RCC)
36 
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
47 /* Defines used to perform offsets*/
48 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
49 #define RCC_OFFSET_CCIPR 0U
50 #define RCC_OFFSET_CCIPR2 0x14U
51 
56 /* Private macros ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 
64 #endif /*USE_FULL_LL_DRIVER*/
65 
66 /* Exported types ------------------------------------------------------------*/
67 #if defined(USE_FULL_LL_DRIVER)
68 
79 typedef struct
80 {
81  uint32_t SYSCLK_Frequency;
82  uint32_t HCLK_Frequency;
83  uint32_t PCLK1_Frequency;
84  uint32_t PCLK2_Frequency;
85 } LL_RCC_ClocksTypeDef;
86 
94 #endif /* USE_FULL_LL_DRIVER */
95 
96 /* Exported constants --------------------------------------------------------*/
107 #if !defined (HSE_VALUE)
108 #define HSE_VALUE 8000000U
109 #endif /* HSE_VALUE */
110 
111 #if !defined (HSI_VALUE)
112 #define HSI_VALUE 16000000U
113 #endif /* HSI_VALUE */
114 
115 #if !defined (LSE_VALUE)
116 #define LSE_VALUE 32768U
117 #endif /* LSE_VALUE */
118 
119 #if !defined (LSI_VALUE)
120 #define LSI_VALUE 32000U
121 #endif /* LSI_VALUE */
122 #if defined(RCC_HSI48_SUPPORT)
123 
124 #if !defined (HSI48_VALUE)
125 #define HSI48_VALUE 48000000U
126 #endif /* HSI48_VALUE */
127 #endif /* RCC_HSI48_SUPPORT */
128 
129 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
130 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U
131 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
132 
133 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
134 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U
135 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
136 
144 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
145 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
146 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
147 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
148 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
149 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
150 #if defined(RCC_HSI48_SUPPORT)
151 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC
152 #endif /* RCC_HSI48_SUPPORT */
153 #if defined(RCC_PLLSAI1_SUPPORT)
154 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
155 #endif /* RCC_PLLSAI1_SUPPORT */
156 #if defined(RCC_PLLSAI2_SUPPORT)
157 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC
158 #endif /* RCC_PLLSAI2_SUPPORT */
159 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
160 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC
169 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
170 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
171 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
172 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
173 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
174 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
175 #if defined(RCC_HSI48_SUPPORT)
176 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF
177 #endif /* RCC_HSI48_SUPPORT */
178 #if defined(RCC_PLLSAI1_SUPPORT)
179 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
180 #endif /* RCC_PLLSAI1_SUPPORT */
181 #if defined(RCC_PLLSAI2_SUPPORT)
182 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF
183 #endif /* RCC_PLLSAI2_SUPPORT */
184 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
185 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
186 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF
187 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
188 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
189 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
190 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
191 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
192 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
193 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
202 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
203 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
204 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
205 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
206 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
207 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
208 #if defined(RCC_HSI48_SUPPORT)
209 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE
210 #endif /* RCC_HSI48_SUPPORT */
211 #if defined(RCC_PLLSAI1_SUPPORT)
212 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
213 #endif /* RCC_PLLSAI1_SUPPORT */
214 #if defined(RCC_PLLSAI2_SUPPORT)
215 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE
216 #endif /* RCC_PLLSAI2_SUPPORT */
217 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE
225 #define LL_RCC_LSEDRIVE_LOW 0x00000000U
226 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
227 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
228 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
236 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0
237 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1
238 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2
239 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3
240 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4
241 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5
242 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6
243 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7
244 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8
245 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9
246 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10
247 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11
255 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1
256 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2
257 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4
258 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8
266 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U
267 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL
275 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI
276 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
277 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
278 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
286 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI
287 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
288 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
289 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
297 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
298 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
299 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
300 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
301 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
302 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
303 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
304 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
305 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
313 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
314 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
315 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
316 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
317 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
325 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
326 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
327 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
328 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
329 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
337 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U
338 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
346 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U
347 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0
348 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1
349 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1)
350 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2
351 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)
352 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
353 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)
354 #if defined(RCC_HSI48_SUPPORT)
355 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3
356 #endif /* RCC_HSI48_SUPPORT */
357 
364 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1
365 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
366 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
367 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
368 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16
373 #if defined(USE_FULL_LL_DRIVER)
374 
377 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
378 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
382 #endif /* USE_FULL_LL_DRIVER */
383 
387 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U)
388 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)
389 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)
390 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)
391 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U)
392 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)
393 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)
394 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)
395 #if defined(RCC_CCIPR_USART3SEL)
396 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U)
397 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0)
398 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1)
399 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)
400 #endif /* RCC_CCIPR_USART3SEL */
401 
405 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
406 
409 #if defined(RCC_CCIPR_UART4SEL)
410 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U)
411 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)
412 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)
413 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)
414 #endif /* RCC_CCIPR_UART4SEL */
415 #if defined(RCC_CCIPR_UART5SEL)
416 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U)
417 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0)
418 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1)
419 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL)
420 #endif /* RCC_CCIPR_UART5SEL */
421 
424 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
425 
429 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U
430 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
431 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
432 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL
440 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U))
441 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos))
442 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos))
443 #if defined(RCC_CCIPR_I2C2SEL)
444 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U))
445 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos))
446 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos))
447 #endif /* RCC_CCIPR_I2C2SEL */
448 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U))
449 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos))
450 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos))
451 #if defined(RCC_CCIPR2_I2C4SEL)
452 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U))
453 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos))
454 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos))
455 #endif /* RCC_CCIPR2_I2C4SEL */
456 
463 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL
464 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U))
465 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U))
466 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))
467 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL
468 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U))
469 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U))
470 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))
478 #if defined(RCC_CCIPR2_SAI1SEL)
479 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U)
480 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0)
481 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1)
482 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2)
483 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0))
484 #elif defined(RCC_CCIPR_SAI1SEL)
485 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL
486 #if defined(RCC_PLLSAI2_SUPPORT)
487 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U))
488 #endif /* RCC_PLLSAI2_SUPPORT */
489 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U))
490 #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U))
491 #endif /* RCC_CCIPR2_SAI1SEL */
492 
493 #if defined(RCC_CCIPR2_SAI2SEL)
494 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U)
495 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0)
496 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1)
497 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2)
498 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0))
499 #elif defined(RCC_CCIPR_SAI2SEL)
500 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL
501 #if defined(RCC_PLLSAI2_SUPPORT)
502 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U))
503 #endif /* RCC_PLLSAI2_SUPPORT */
504 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U))
505 #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U))
506 #endif /* RCC_CCIPR2_SAI2SEL */
507 
511 #if defined(RCC_CCIPR2_SDMMCSEL)
512 
515 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U
516 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL
520 #endif /* RCC_CCIPR2_SDMMCSEL */
521 
522 #if defined(SDMMC1)
523 
526 #if defined(RCC_HSI48_SUPPORT)
527 #define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U
528 #else
529 #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U
530 #endif
531 #if defined(RCC_PLLSAI1_SUPPORT)
532 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
533 #endif /* RCC_PLLSAI1_SUPPORT */
534 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
535 #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
539 #endif /* SDMMC1 */
540 
544 #if defined(RCC_HSI48_SUPPORT)
545 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U
546 #else
547 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U
548 #endif
549 #if defined(RCC_PLLSAI1_SUPPORT)
550 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
551 #endif /* RCC_PLLSAI1_SUPPORT */
552 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
553 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
558 #if defined(USB_OTG_FS) || defined(USB)
559 
562 #if defined(RCC_HSI48_SUPPORT)
563 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U
564 #else
565 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U
566 #endif
567 #if defined(RCC_PLLSAI1_SUPPORT)
568 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
569 #endif /* RCC_PLLSAI1_SUPPORT */
570 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
571 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
576 #endif /* USB_OTG_FS || USB */
577 
581 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U
582 #if defined(RCC_PLLSAI1_SUPPORT)
583 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
584 #endif /* RCC_PLLSAI1_SUPPORT */
585 #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
586 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
587 #endif /* RCC_PLLSAI2_SUPPORT */
588 #if defined(RCC_CCIPR_ADCSEL)
589 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
590 #else
591 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U
592 #endif
593 
597 #if defined(SWPMI1)
598 
601 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U
602 #define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
606 #endif /* SWPMI1 */
607 
608 #if defined(DFSDM1_Channel0)
609 #if defined(RCC_CCIPR2_ADFSDM1SEL)
610 
613 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U
614 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0
615 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1
619 #endif /* RCC_CCIPR2_ADFSDM1SEL */
620 
624 #if defined(RCC_CCIPR2_DFSDM1SEL)
625 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U
626 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL
627 #else
628 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U
629 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
630 #endif /* RCC_CCIPR2_DFSDM1SEL */
631 
634 #endif /* DFSDM1_Channel0 */
635 
636 #if defined(DSI)
637 
640 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U
641 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL
645 #endif /* DSI */
646 
647 #if defined(LTDC)
648 
651 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U
652 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0
653 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1
654 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR
658 #endif /* LTDC */
659 
660 #if defined(OCTOSPI1)
661 
664 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U
665 #define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0
666 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1
670 #endif /* OCTOSPI1 */
671 
675 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
676 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
677 #if defined(RCC_CCIPR_USART3SEL)
678 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL
679 #endif /* RCC_CCIPR_USART3SEL */
680 
684 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
685 
688 #if defined(RCC_CCIPR_UART4SEL)
689 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL
690 #endif /* RCC_CCIPR_UART4SEL */
691 #if defined(RCC_CCIPR_UART5SEL)
692 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL
693 #endif /* RCC_CCIPR_UART5SEL */
694 
697 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
698 
702 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
710 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos))
711 #if defined(RCC_CCIPR_I2C2SEL)
712 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos))
713 #endif /* RCC_CCIPR_I2C2SEL */
714 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos))
715 #if defined(RCC_CCIPR2_I2C4SEL)
716 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos))
717 #endif /* RCC_CCIPR2_I2C4SEL */
718 
725 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
726 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL
731 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
732 
735 #if defined(RCC_CCIPR2_SAI1SEL)
736 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL
737 #else
738 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
739 #endif /* RCC_CCIPR2_SAI1SEL */
740 #if defined(RCC_CCIPR2_SAI2SEL)
741 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL
742 #elif defined(RCC_CCIPR_SAI2SEL)
743 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL
744 #endif /* RCC_CCIPR2_SAI2SEL */
745 
748 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
749 
750 #if defined(SDMMC1)
751 #if defined(RCC_CCIPR2_SDMMCSEL)
752 
755 #define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL
759 #endif /* RCC_CCIPR2_SDMMCSEL */
760 
764 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL
768 #endif /* SDMMC1 */
769 
773 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL
778 #if defined(USB_OTG_FS) || defined(USB)
779 
782 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL
786 #endif /* USB_OTG_FS || USB */
787 
791 #if defined(RCC_CCIPR_ADCSEL)
792 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL
793 #else
794 #define LL_RCC_ADC_CLKSOURCE 0x30000000U
795 #endif
796 
800 #if defined(SWPMI1)
801 
804 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL
808 #endif /* SWPMI1 */
809 
810 #if defined(DFSDM1_Channel0)
811 #if defined(RCC_CCIPR2_ADFSDM1SEL)
812 
815 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
816 
820 #endif /* RCC_CCIPR2_ADFSDM1SEL */
821 
824 #if defined(RCC_CCIPR2_DFSDM1SEL)
825 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL
826 #else
827 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL
828 #endif /* RCC_CCIPR2_DFSDM1SEL */
829 
832 #endif /* DFSDM1_Channel0 */
833 
834 #if defined(DSI)
835 
838 #define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL
842 #endif /* DSI */
843 
844 #if defined(LTDC)
845 
848 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR
852 #endif /* LTDC */
853 
854 #if defined(OCTOSPI1)
855 
858 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL
862 #endif /* OCTOSPI1 */
863 
864 
868 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
869 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
870 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
871 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
880 #define LL_RCC_PLLSOURCE_NONE 0x00000000U
881 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI
882 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
883 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
891 #define LL_RCC_PLLM_DIV_1 0x00000000U
892 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
893 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
894 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
895 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
896 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
897 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
898 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
899 #if defined(RCC_PLLM_DIV_1_16_SUPPORT)
900 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3)
901 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
902 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
903 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
904 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
905 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
906 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
907 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
908 #endif /* RCC_PLLM_DIV_1_16_SUPPORT */
909 
916 #define LL_RCC_PLLR_DIV_2 0x00000000U
917 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
918 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
919 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
924 #if defined(RCC_PLLP_SUPPORT)
925 
928 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
929 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1)
930 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
931 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2)
932 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
933 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
934 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
935 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3)
936 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)
937 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)
938 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
939 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)
940 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
941 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
942 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
943 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4)
944 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)
945 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)
946 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
947 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)
948 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
949 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
950 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
951 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)
952 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)
953 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)
954 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
955 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)
956 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)
957 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)
958 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)
959 #else
960 #define LL_RCC_PLLP_DIV_7 0x00000000U
961 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP)
962 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
963 
966 #endif /* RCC_PLLP_SUPPORT */
967 
971 #define LL_RCC_PLLQ_DIV_2 0x00000000U
972 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
973 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
974 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
979 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
980 
983 #define LL_RCC_PLLSAI1M_DIV_1 0x00000000U
984 #define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0)
985 #define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1)
986 #define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0)
987 #define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2)
988 #define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0)
989 #define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1)
990 #define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0)
991 #define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3)
992 #define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0)
993 #define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1)
994 #define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0)
995 #define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2)
996 #define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0)
997 #define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1)
998 #define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0)
1002 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1003 
1004 #if defined(RCC_PLLSAI1_SUPPORT)
1005 
1008 #define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U
1009 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0)
1010 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1)
1011 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q)
1019 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1020 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1021 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1022 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
1023 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1024 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1025 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1026 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)
1027 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1028 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1029 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1030 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
1031 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1032 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1033 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1034 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)
1035 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1036 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1037 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1038 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
1039 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1040 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1041 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1042 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)
1043 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1044 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1045 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1046 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)
1047 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1048 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)
1049 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0)
1050 #else
1051 #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U
1052 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P)
1053 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1054 
1061 #define LL_RCC_PLLSAI1R_DIV_2 0x00000000U
1062 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0)
1063 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1)
1064 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R)
1068 #endif /* RCC_PLLSAI1_SUPPORT */
1069 
1070 #if defined(RCC_PLLSAI2_SUPPORT)
1071 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1072 
1075 #define LL_RCC_PLLSAI2M_DIV_1 0x00000000U
1076 #define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0)
1077 #define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1)
1078 #define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1079 #define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2)
1080 #define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1081 #define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1)
1082 #define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1083 #define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3)
1084 #define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1085 #define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1)
1086 #define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1087 #define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2)
1088 #define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1089 #define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1)
1090 #define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0)
1094 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
1095 
1096 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
1097 
1100 #define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U
1101 #define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0)
1102 #define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1)
1103 #define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q)
1107 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
1108 
1112 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1113 #define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1114 #define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1115 #define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2)
1116 #define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1117 #define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1118 #define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1119 #define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3)
1120 #define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1121 #define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1122 #define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1123 #define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2)
1124 #define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1125 #define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1126 #define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1127 #define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4)
1128 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1129 #define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1130 #define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1131 #define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2)
1132 #define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1133 #define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1134 #define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1135 #define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3)
1136 #define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1137 #define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1138 #define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1139 #define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2)
1140 #define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1141 #define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)
1142 #define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0)
1143 #else
1144 #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U
1145 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P)
1146 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
1147 
1154 #define LL_RCC_PLLSAI2R_DIV_2 0x00000000U
1155 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0)
1156 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1)
1157 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R)
1162 #if defined(RCC_CCIPR2_PLLSAI2DIVR)
1163 
1166 #define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U
1167 #define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0
1168 #define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1
1169 #define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0)
1173 #endif /* RCC_CCIPR2_PLLSAI2DIVR */
1174 #endif /* RCC_PLLSAI2_SUPPORT */
1175 
1179 #define LL_RCC_MSIRANGESEL_STANDBY 0U
1180 #define LL_RCC_MSIRANGESEL_RUN 1U
1185 #if defined(RCC_CSR_LSIPREDIV)
1186 
1189 #define LL_RCC_LSI_PREDIV_1 0x00000000U
1190 #define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV
1194 #endif /* RCC_CSR_LSIPREDIV */
1195 
1199 #if defined(DFSDM1_Channel0)
1200 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
1201 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
1202 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
1203 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
1204 #endif /* DFSDM1_Channel0 */
1205 #if defined(SWPMI1)
1206 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
1207 #endif /* SWPMI1 */
1208 
1216 /* Exported macro ------------------------------------------------------------*/
1231 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1232 
1238 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1239 
1279 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1280  ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
1281 
1282 #if defined(RCC_PLLSAI1_SUPPORT)
1283 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
1284 
1342 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1343  ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
1344 
1345 #else
1346 
1366 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1367  (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
1368 
1369 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
1370 #endif /* RCC_PLLSAI1_SUPPORT */
1371 
1404 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1405  ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
1406 
1407 #if defined(RCC_PLLSAI1_SUPPORT)
1408 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1409 
1465 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
1466  ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1467  ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1468 
1469 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1470 
1518 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1519  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1520  ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1521 
1522 #else
1523 
1543 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1544  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1545  (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
1546 
1547 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1548 
1549 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1550 
1580 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
1581  ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1582  ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1583 
1584 #else
1585 
1607 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
1608  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1609  ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1610 
1611 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1612 
1613 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1614 
1644 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
1645  ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1646  ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1647 
1648 #else
1649 
1671 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
1672  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1673  ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1674 
1675 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1676 #endif /* RCC_PLLSAI1_SUPPORT */
1677 
1678 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1679 
1735 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
1736  ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1737  ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1738 
1739 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1740 
1788 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
1789  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
1790  ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1791 
1792 #else
1793 
1813 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
1814  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
1815  (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
1816 
1817 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
1818 
1819 #if defined(LTDC)
1820 
1855 #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
1856  (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1857  (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos))))
1858 #elif defined(RCC_PLLSAI2_SUPPORT)
1859 
1881 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
1882  ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
1883  ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
1884 
1885 #endif /* LTDC */
1886 
1887 #if defined(DSI)
1888 
1918 #define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
1919  ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1920  ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
1921 #endif /* DSI */
1922 
1923 
1924 
1940 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1941 
1953 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1954 
1966 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1967 
2000 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
2001  (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
2002  (MSIRangeTable[(__MSIRANGE__) >> 4U]))
2003 
2012 /* Exported functions --------------------------------------------------------*/
2026 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2027 {
2028  SET_BIT(RCC->CR, RCC_CR_CSSON);
2029 }
2030 
2036 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2037 {
2038  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2039 }
2040 
2046 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2047 {
2048  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2049 }
2050 
2056 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2057 {
2058  SET_BIT(RCC->CR, RCC_CR_HSEON);
2059 }
2060 
2066 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2067 {
2068  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2069 }
2070 
2076 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2077 {
2078  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
2079 }
2080 
2095 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
2096 {
2097  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
2098 }
2099 
2105 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
2106 {
2107  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
2108 }
2109 
2115 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
2116 {
2117  return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
2118 }
2119 
2125 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2126 {
2127  SET_BIT(RCC->CR, RCC_CR_HSION);
2128 }
2129 
2135 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2136 {
2137  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
2138 }
2139 
2145 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
2146 {
2147  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
2148 }
2149 
2155 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
2156 {
2157  SET_BIT(RCC->CR, RCC_CR_HSIASFS);
2158 }
2159 
2165 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
2166 {
2167  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
2168 }
2176 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
2177 {
2178  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
2179 }
2180 
2190 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
2191 {
2192  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
2193 }
2194 
2200 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
2201 {
2202  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
2203 }
2204 
2209 #if defined(RCC_HSI48_SUPPORT)
2210 
2219 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
2220 {
2221  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2222 }
2223 
2229 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2230 {
2231  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2232 }
2233 
2239 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2240 {
2241  return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
2242 }
2243 
2249 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2250 {
2251  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2252 }
2253 
2257 #endif /* RCC_HSI48_SUPPORT */
2258 
2268 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2269 {
2270  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2271 }
2272 
2278 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2279 {
2280  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2281 }
2282 
2288 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2289 {
2290  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2291 }
2292 
2298 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2299 {
2300  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2301 }
2302 
2314 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2315 {
2316  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2317 }
2318 
2328 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2329 {
2330  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2331 }
2332 
2338 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2339 {
2340  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2341 }
2342 
2350 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
2351 {
2352  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2353 }
2354 
2360 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2361 {
2362  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
2363 }
2364 
2370 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
2371 {
2372  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
2373 }
2374 
2375 #if defined(RCC_BDCR_LSESYSDIS)
2376 
2383 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
2384 {
2385  SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
2386 }
2387 
2394 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
2395 {
2396  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
2397 }
2398 
2404 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void)
2405 {
2406  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL);
2407 }
2408 #endif /* RCC_BDCR_LSESYSDIS */
2409 
2422 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2423 {
2424  SET_BIT(RCC->CSR, RCC_CSR_LSION);
2425 }
2426 
2432 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2433 {
2434  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2435 }
2436 
2442 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2443 {
2444  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
2445 }
2446 
2447 #if defined(RCC_CSR_LSIPREDIV)
2448 
2456 __STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)
2457 {
2458  MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV);
2459 }
2460 
2468 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)
2469 {
2470  return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV));
2471 }
2472 #endif /* RCC_CSR_LSIPREDIV */
2473 
2487 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
2488 {
2489  SET_BIT(RCC->CR, RCC_CR_MSION);
2490 }
2491 
2497 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
2498 {
2499  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
2500 }
2501 
2507 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
2508 {
2509  return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
2510 }
2511 
2521 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
2522 {
2523  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2524 }
2525 
2533 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
2534 {
2535  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2536 }
2537 
2546 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
2547 {
2548  SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
2549 }
2550 
2556 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
2557 {
2558  return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL);
2559 }
2560 
2579 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
2580 {
2581  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
2582 }
2583 
2601 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
2602 {
2603  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
2604 }
2605 
2616 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
2617 {
2618  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
2619 }
2620 
2630 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
2631 {
2632  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
2633 }
2634 
2642 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
2643 {
2644  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
2645 }
2646 
2654 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
2655 {
2656  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
2657 }
2658 
2664 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
2665 {
2666  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
2667 }
2668 
2682 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2683 {
2684  SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2685 }
2686 
2692 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2693 {
2694  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2695 }
2696 
2705 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2706 {
2707  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2708 }
2709 
2717 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2718 {
2719  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2720 }
2721 
2740 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2741 {
2742  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2743 }
2744 
2754 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2755 {
2756  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2757 }
2758 
2774 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2775 {
2776  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2777 }
2778 
2790 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2791 {
2792  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2793 }
2794 
2806 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2807 {
2808  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2809 }
2810 
2825 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2826 {
2827  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2828 }
2829 
2840 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2841 {
2842  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2843 }
2844 
2855 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2856 {
2857  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2858 }
2859 
2868 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2869 {
2870  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2871 }
2872 
2880 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2881 {
2882  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2883 }
2884 
2917 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2918 {
2919  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2920 }
2921 
2950 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2951 {
2952  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2953 }
2954 
2955 #if defined(UART4) || defined(UART5)
2956 
2970 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2971 {
2972  MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2973 }
2974 #endif /* UART4 || UART5 */
2975 
2986 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2987 {
2988  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2989 }
2990 
3011 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
3012 {
3013  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
3014  MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
3015 }
3016 
3031 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3032 {
3033  MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
3034 }
3035 
3036 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
3037 
3057 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3058 {
3059 #if defined(RCC_CCIPR2_SAI1SEL)
3060  MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
3061 #else
3062  MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3063 #endif /* RCC_CCIPR2_SAI1SEL */
3064 }
3065 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
3066 
3067 #if defined(RCC_CCIPR2_SDMMCSEL)
3068 
3078 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
3079 {
3080  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
3081 }
3082 #endif /* RCC_CCIPR2_SDMMCSEL */
3083 
3097 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
3098 {
3099  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
3100 }
3101 
3115 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3116 {
3117  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
3118 }
3119 
3120 #if defined(USB_OTG_FS) || defined(USB)
3121 
3134 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3135 {
3136  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
3137 }
3138 #endif /* USB_OTG_FS || USB */
3139 
3140 #if defined(RCC_CCIPR_ADCSEL)
3141 
3153 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
3154 {
3155  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
3156 }
3157 #endif /* RCC_CCIPR_ADCSEL */
3158 
3159 #if defined(SWPMI1)
3160 
3168 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
3169 {
3170  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
3171 }
3172 #endif /* SWPMI1 */
3173 
3174 #if defined(DFSDM1_Channel0)
3175 #if defined(RCC_CCIPR2_ADFSDM1SEL)
3176 
3185 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3186 {
3187  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
3188 }
3189 #endif /* RCC_CCIPR2_ADFSDM1SEL */
3190 
3203 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
3204 {
3205 #if defined(RCC_CCIPR2_DFSDM1SEL)
3206  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
3207 #else
3208  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
3209 #endif /* RCC_CCIPR2_DFSDM1SEL */
3210 }
3211 #endif /* DFSDM1_Channel0 */
3212 
3213 #if defined(DSI)
3214 
3222 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3223 {
3224  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
3225 }
3226 #endif /* DSI */
3227 
3228 #if defined(LTDC)
3229 
3239 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
3240 {
3241  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
3242 }
3243 #endif /* LTDC */
3244 
3245 #if defined(OCTOSPI1)
3246 
3255 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
3256 {
3257  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
3258 }
3259 #endif /* OCTOSPI1 */
3260 
3286 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
3287 {
3288  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
3289 }
3290 
3291 #if defined(UART4) || defined(UART5)
3292 
3308 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
3309 {
3310  return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
3311 }
3312 #endif /* UART4 || UART5 */
3313 
3325 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
3326 {
3327  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
3328 }
3329 
3356 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
3357 {
3358  __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
3359  return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
3360 }
3361 
3378 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3379 {
3380  return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
3381 }
3382 
3383 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
3384 
3408 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3409 {
3410 #if defined(RCC_CCIPR2_SAI1SEL)
3411  return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
3412 #else
3413  return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);
3414 #endif /* RCC_CCIPR2_SAI1SEL */
3415 }
3416 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
3417 
3418 #if defined(SDMMC1)
3419 #if defined(RCC_CCIPR2_SDMMCSEL)
3420 
3431 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
3432 {
3433  return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
3434 }
3435 #endif /* RCC_CCIPR2_SDMMCSEL */
3436 
3451 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
3452 {
3453  return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
3454 }
3455 #endif /* SDMMC1 */
3456 
3471 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3472 {
3473  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
3474 }
3475 
3476 #if defined(USB_OTG_FS) || defined(USB)
3477 
3491 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3492 {
3493  return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
3494 }
3495 #endif /* USB_OTG_FS || USB */
3496 
3510 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
3511 {
3512 #if defined(RCC_CCIPR_ADCSEL)
3513  return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
3514 #else
3515  (void)ADCx; /* unused */
3516  return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE);
3517 #endif /* RCC_CCIPR_ADCSEL */
3518 }
3519 
3520 #if defined(SWPMI1)
3521 
3530 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
3531 {
3532  return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
3533 }
3534 #endif /* SWPMI1 */
3535 
3536 #if defined(DFSDM1_Channel0)
3537 #if defined(RCC_CCIPR2_ADFSDM1SEL)
3538 
3548 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3549 {
3550  return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
3551 }
3552 #endif /* RCC_CCIPR2_ADFSDM1SEL */
3553 
3567 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3568 {
3569 #if defined(RCC_CCIPR2_DFSDM1SEL)
3570  return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
3571 #else
3572  return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
3573 #endif /* RCC_CCIPR2_DFSDM1SEL */
3574 }
3575 #endif /* DFSDM1_Channel0 */
3576 
3577 #if defined(DSI)
3578 
3587 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3588 {
3589  return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
3590 }
3591 #endif /* DSI */
3592 
3593 #if defined(LTDC)
3594 
3605 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
3606 {
3607  return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
3608 }
3609 #endif /* LTDC */
3610 
3611 #if defined(OCTOSPI1)
3612 
3622 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
3623 {
3624  return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
3625 }
3626 #endif /* OCTOSPI1 */
3627 
3648 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3649 {
3650  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3651 }
3652 
3662 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3663 {
3664  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3665 }
3666 
3672 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3673 {
3674  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3675 }
3676 
3682 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3683 {
3684  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3685 }
3686 
3692 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3693 {
3694  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
3695 }
3696 
3702 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3703 {
3704  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3705 }
3706 
3712 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3713 {
3714  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3715 }
3716 
3731 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
3732 {
3733  SET_BIT(RCC->CR, RCC_CR_PLLON);
3734 }
3735 
3742 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
3743 {
3744  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
3745 }
3746 
3752 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3753 {
3754  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
3755 }
3756 
3798 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3799 {
3800  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3801  Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
3802 }
3803 
3804 #if defined(RCC_PLLP_SUPPORT)
3805 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3806 
3874 #else
3875 
3905 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
3906 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3907 {
3908 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3909  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
3910  Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3911 #else
3912  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3913  Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3914 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
3915 }
3916 #endif /* RCC_PLLP_SUPPORT */
3917 
3960 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3961 {
3962  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3963  Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3964 }
3965 
3976 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3977 {
3978  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3979 }
3980 
3990 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3991 {
3992  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3993 }
3994 
4000 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4001 {
4002  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4003 }
4004 
4005 #if defined(RCC_PLLP_SUPPORT)
4006 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
4007 
4043 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4044 {
4045  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
4046 }
4047 #else
4048 
4056 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4057 {
4058  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4059 }
4060 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
4061 #endif /* RCC_PLLP_SUPPORT */
4062 
4073 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4074 {
4075  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4076 }
4077 
4088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4089 {
4090  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4091 }
4092 
4116 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
4117 {
4118  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
4119 }
4120 
4121 #if defined(RCC_PLLP_SUPPORT)
4122 
4127 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
4128 {
4129  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
4130 }
4131 
4141 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
4142 {
4143  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
4144 }
4145 #endif /* RCC_PLLP_SUPPORT */
4146 
4152 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
4153 {
4154  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
4155 }
4156 
4166 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
4167 {
4168  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
4169 }
4170 
4176 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
4177 {
4178  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
4179 }
4180 
4190 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
4191 {
4192  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
4193 }
4194 
4199 #if defined(RCC_PLLSAI1_SUPPORT)
4200 
4209 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
4210 {
4211  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
4212 }
4213 
4219 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
4220 {
4221  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
4222 }
4223 
4229 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
4230 {
4231  return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL);
4232 }
4233 
4234 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4235 
4274 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4275 {
4276  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4277  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
4278  PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ);
4279 }
4280 #else
4281 
4313 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4314 {
4315  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4316  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
4317 }
4318 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4319 
4320 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4321 
4386 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4387 {
4388  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4389  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
4390  PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP);
4391 }
4392 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4393 
4451 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4452 {
4453  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4454  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
4455  PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
4456 }
4457 #else
4458 
4488 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4489 {
4490  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4491  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
4492 }
4493 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
4494 
4495 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4496 
4535 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4536 {
4537  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4538  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
4539  PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR);
4540 }
4541 #else
4542 
4574 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4575 {
4576  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4577  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
4578 }
4579 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4580 
4586 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
4587 {
4588  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
4589 }
4590 
4591 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4592 
4628 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
4629 {
4630  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
4631 }
4632 #else
4633 
4641 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
4642 {
4643  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
4644 }
4645 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
4646 
4657 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
4658 {
4659  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
4660 }
4661 
4672 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
4673 {
4674  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
4675 }
4676 
4677 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4678 
4699 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
4700 {
4701  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
4702 }
4703 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4704 
4710 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
4711 {
4712  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
4713 }
4714 
4722 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
4723 {
4724  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
4725 }
4726 
4732 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
4733 {
4734  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
4735 }
4736 
4744 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
4745 {
4746  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
4747 }
4748 
4754 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
4755 {
4756  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
4757 }
4758 
4766 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
4767 {
4768  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
4769 }
4770 
4774 #endif /* RCC_PLLSAI1_SUPPORT */
4775 
4776 #if defined(RCC_PLLSAI2_SUPPORT)
4777 
4786 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
4787 {
4788  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4789 }
4790 
4796 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
4797 {
4798  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4799 }
4800 
4806 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
4807 {
4808  return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL);
4809 }
4810 
4811 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
4812 
4877 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4878 {
4879  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4880  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
4881  PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP);
4882 }
4883 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
4884 
4942 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4943 {
4944  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4945  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
4946 }
4947 #else
4948 
4978 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4979 {
4980  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4981  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
4982 }
4983 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
4984 
4985 #if defined(DSI)
4986 
5025 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5026 {
5027  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5028  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
5029  (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM);
5030 }
5031 #endif /* DSI */
5032 
5033 #if defined(LTDC)
5034 
5079 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
5080 {
5081  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5082  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
5083  (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM);
5084  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
5085 }
5086 #else
5087 
5119 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5120 {
5121  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
5122  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
5123 }
5124 #endif /* LTDC */
5125 
5131 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
5132 {
5133  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
5134 }
5135 
5136 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
5137 
5173 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
5174 {
5175  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
5176 }
5177 #else
5178 
5186 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
5187 {
5188  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
5189 }
5190 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
5191 
5192 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
5193 
5203 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
5204 {
5205  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
5206 }
5207 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
5208 
5219 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
5220 {
5221  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
5222 }
5223 
5224 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
5225 
5246 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
5247 {
5248  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
5249 }
5250 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
5251 
5252 #if defined(RCC_CCIPR2_PLLSAI2DIVR)
5253 
5263 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
5264 {
5265  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
5266 }
5267 #endif /* RCC_CCIPR2_PLLSAI2DIVR */
5268 
5274 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
5275 {
5276  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5277 }
5278 
5286 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
5287 {
5288  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5289 }
5290 
5291 #if defined(DSI)
5292 
5297 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
5298 {
5299  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5300 }
5301 
5309 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
5310 {
5311  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5312 }
5313 #endif /* DSI */
5314 
5315 #if defined(LTDC)
5316 
5321 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
5322 {
5323  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5324 }
5325 
5333 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
5334 {
5335  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5336 }
5337 #else
5338 
5343 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
5344 {
5345  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5346 }
5347 
5355 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
5356 {
5357  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5358 }
5359 #endif /* LTDC */
5360 
5364 #endif /* RCC_PLLSAI2_SUPPORT */
5365 
5366 
5367 
5377 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5378 {
5379  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5380 }
5381 
5387 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5388 {
5389  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5390 }
5391 
5397 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
5398 {
5399  SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
5400 }
5401 
5407 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5408 {
5409  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5410 }
5411 
5417 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5418 {
5419  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5420 }
5421 
5427 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
5428 {
5429  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5430 }
5431 
5432 #if defined(RCC_HSI48_SUPPORT)
5433 
5438 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5439 {
5440  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5441 }
5442 #endif /* RCC_HSI48_SUPPORT */
5443 
5444 #if defined(RCC_PLLSAI1_SUPPORT)
5445 
5450 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
5451 {
5452  SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
5453 }
5454 #endif /* RCC_PLLSAI1_SUPPORT */
5455 
5456 #if defined(RCC_PLLSAI2_SUPPORT)
5457 
5462 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
5463 {
5464  SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
5465 }
5466 #endif /* RCC_PLLSAI2_SUPPORT */
5467 
5473 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5474 {
5475  SET_BIT(RCC->CICR, RCC_CICR_CSSC);
5476 }
5477 
5483 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5484 {
5485  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5486 }
5487 
5493 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5494 {
5495  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
5496 }
5497 
5503 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5504 {
5505  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
5506 }
5507 
5513 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
5514 {
5515  return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
5516 }
5517 
5523 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5524 {
5525  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
5526 }
5527 
5533 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5534 {
5535  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
5536 }
5537 
5543 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
5544 {
5545  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
5546 }
5547 
5548 #if defined(RCC_HSI48_SUPPORT)
5549 
5554 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5555 {
5556  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
5557 }
5558 #endif /* RCC_HSI48_SUPPORT */
5559 
5560 #if defined(RCC_PLLSAI1_SUPPORT)
5561 
5566 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
5567 {
5568  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL);
5569 }
5570 #endif /* RCC_PLLSAI1_SUPPORT */
5571 
5572 #if defined(RCC_PLLSAI2_SUPPORT)
5573 
5578 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
5579 {
5580  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL);
5581 }
5582 #endif /* RCC_PLLSAI2_SUPPORT */
5583 
5589 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5590 {
5591  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
5592 }
5593 
5599 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5600 {
5601  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
5602 }
5603 
5609 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
5610 {
5611  return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL);
5612 }
5613 
5619 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
5620 {
5621  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
5622 }
5623 
5629 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5630 {
5631  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
5632 }
5633 
5639 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
5640 {
5641  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
5642 }
5643 
5649 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5650 {
5651  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
5652 }
5653 
5659 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5660 {
5661  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
5662 }
5663 
5669 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
5670 {
5671  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
5672 }
5673 
5679 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5680 {
5681  return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
5682 }
5683 
5689 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5690 {
5691  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
5692 }
5693 
5707 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5708 {
5709  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5710 }
5711 
5717 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5718 {
5719  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5720 }
5721 
5727 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
5728 {
5729  SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
5730 }
5731 
5737 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5738 {
5739  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5740 }
5741 
5747 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5748 {
5749  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5750 }
5751 
5757 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
5758 {
5759  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
5760 }
5761 
5762 #if defined(RCC_HSI48_SUPPORT)
5763 
5768 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
5769 {
5770  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5771 }
5772 #endif /* RCC_HSI48_SUPPORT */
5773 
5774 #if defined(RCC_PLLSAI1_SUPPORT)
5775 
5780 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
5781 {
5782  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
5783 }
5784 #endif /* RCC_PLLSAI1_SUPPORT */
5785 
5786 #if defined(RCC_PLLSAI2_SUPPORT)
5787 
5792 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
5793 {
5794  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
5795 }
5796 #endif /* RCC_PLLSAI2_SUPPORT */
5797 
5803 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
5804 {
5805  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5806 }
5807 
5813 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5814 {
5815  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5816 }
5817 
5823 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5824 {
5825  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5826 }
5827 
5833 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
5834 {
5835  CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
5836 }
5837 
5843 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5844 {
5845  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5846 }
5847 
5853 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5854 {
5855  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5856 }
5857 
5863 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
5864 {
5865  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
5866 }
5867 
5868 #if defined(RCC_HSI48_SUPPORT)
5869 
5874 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
5875 {
5876  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5877 }
5878 #endif /* RCC_HSI48_SUPPORT */
5879 
5880 #if defined(RCC_PLLSAI1_SUPPORT)
5881 
5886 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
5887 {
5888  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
5889 }
5890 #endif /* RCC_PLLSAI1_SUPPORT */
5891 
5892 #if defined(RCC_PLLSAI2_SUPPORT)
5893 
5898 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
5899 {
5900  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
5901 }
5902 #endif /* RCC_PLLSAI2_SUPPORT */
5903 
5909 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
5910 {
5911  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5912 }
5913 
5919 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5920 {
5921  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
5922 }
5923 
5929 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5930 {
5931  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
5932 }
5933 
5939 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
5940 {
5941  return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
5942 }
5943 
5949 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5950 {
5951  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
5952 }
5953 
5959 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5960 {
5961  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
5962 }
5963 
5969 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
5970 {
5971  return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
5972 }
5973 
5974 #if defined(RCC_HSI48_SUPPORT)
5975 
5980 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
5981 {
5982  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
5983 }
5984 #endif /* RCC_HSI48_SUPPORT */
5985 
5986 #if defined(RCC_PLLSAI1_SUPPORT)
5987 
5992 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
5993 {
5994  return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL);
5995 }
5996 #endif /* RCC_PLLSAI1_SUPPORT */
5997 
5998 #if defined(RCC_PLLSAI2_SUPPORT)
5999 
6004 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
6005 {
6006  return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL);
6007 }
6008 #endif /* RCC_PLLSAI2_SUPPORT */
6009 
6015 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
6016 {
6017  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
6018 }
6019 
6024 #if defined(USE_FULL_LL_DRIVER)
6025 
6028 ErrorStatus LL_RCC_DeInit(void);
6036 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6037 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6038 #if defined(UART4) || defined(UART5)
6039 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
6040 #endif /* UART4 || UART5 */
6041 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6042 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6043 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6044 #if defined(SAI1)
6045 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6046 #endif /* SAI1 */
6047 #if defined(SDMMC1)
6048 #if defined(RCC_CCIPR2_SDMMCSEL)
6049 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
6050 #endif
6051 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6052 #endif /* SDMMC1 */
6053 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6054 #if defined(USB_OTG_FS) || defined(USB)
6055 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6056 #endif /* USB_OTG_FS || USB */
6057 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6058 #if defined(SWPMI1)
6059 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
6060 #endif /* SWPMI1 */
6061 #if defined(DFSDM1_Channel0)
6062 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6063 #if defined(RCC_CCIPR2_DFSDM1SEL)
6064 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
6065 #endif /* RCC_CCIPR2_DFSDM1SEL */
6066 #endif /* DFSDM1_Channel0 */
6067 #if defined(LTDC)
6068 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
6069 #endif /* LTDC */
6070 #if defined(DSI)
6071 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6072 #endif /* DSI */
6073 #if defined(OCTOSPI1)
6074 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
6075 #endif /* OCTOSPI1 */
6076 
6079 #endif /* USE_FULL_LL_DRIVER */
6080 
6089 #endif /* defined(RCC) */
6090 
6095 #ifdef __cplusplus
6096 }
6097 #endif
6098 
6099 #endif /* STM32L4xx_LL_RCC_H */
6100 
6101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
LL_RCC_HSE_Disable
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
Disable HSE crystal oscillator (HSE ON) CR HSEON LL_RCC_HSE_Disable.
Definition: stm32l4xx_ll_rcc.h:2066
LL_RCC_GetRNGClockFreq
uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
Return RNGx clock frequency.
Definition: stm32l4xx_ll_rcc.c:1049
LL_RCC_PLLSAI1_ConfigDomain_SAI
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI1 used for SAI domain clock.
Definition: stm32l4xx_ll_rcc.h:4386
LL_RCC_ClearFlag_MSIRDY
__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
Clear MSI ready interrupt flag CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY.
Definition: stm32l4xx_ll_rcc.h:5397
LL_RCC_EnableIT_HSIRDY
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
Enable HSI ready interrupt CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY.
Definition: stm32l4xx_ll_rcc.h:5737
LL_RCC_PLLSAI2_GetN
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
Get SAI2PLL multiplication factor for VCO PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN.
Definition: stm32l4xx_ll_rcc.h:5131
LL_RCC_ClocksTypeDef::PCLK1_Frequency
uint32_t PCLK1_Frequency
Definition: stm32l4xx_ll_rcc.h:83
LL_RCC_ClocksTypeDef::PCLK2_Frequency
uint32_t PCLK2_Frequency
Definition: stm32l4xx_ll_rcc.h:84
LL_RCC_ClearFlag_HSI48RDY
__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
Clear HSI48 ready interrupt flag CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY.
Definition: stm32l4xx_ll_rcc.h:5438
LL_RCC_EnableIT_PLLRDY
__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
Enable PLL ready interrupt CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY.
Definition: stm32l4xx_ll_rcc.h:5757
LL_RCC_GetSDMMCKernelClockFreq
uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
Return SDMMCx kernel clock frequency.
Definition: stm32l4xx_ll_rcc.c:946
LL_RCC_IsEnabledIT_MSIRDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
Checks if MSI ready interrupt source is enabled or disabled. CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY...
Definition: stm32l4xx_ll_rcc.h:5939
LL_RCC_IsActiveFlag_MSIRDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
Check if MSI ready interrupt occurred or not CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY.
Definition: stm32l4xx_ll_rcc.h:5513
LL_RCC_IsActiveFlag_OBLRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
Check if RCC flag is set or not. CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST.
Definition: stm32l4xx_ll_rcc.h:5639
LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure.
Definition: stm32l4xx_ll_rcc.h:79
LL_RCC_IsActiveFlag_HSI48RDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
Check if HSI48 ready interrupt occurred or not CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY.
Definition: stm32l4xx_ll_rcc.h:5554
LL_RCC_HSI48_Enable
__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
Enable HSI48 CRRCR HSI48ON LL_RCC_HSI48_Enable.
Definition: stm32l4xx_ll_rcc.h:2219
LL_RCC_PLLSAI2_GetDivider
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
Get Division factor for the PLLSAI2 PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider.
Definition: stm32l4xx_ll_rcc.h:5246
LL_RCC_PLL_EnableDomain_48M
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
Enable PLL output mapped on 48MHz domain clock PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M.
Definition: stm32l4xx_ll_rcc.h:4152
LL_RCC_PLLSAI1_DisableDomain_48M
__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
Disable PLLSAI1 output mapped on 48MHz domain clock.
Definition: stm32l4xx_ll_rcc.h:4744
LL_RCC_GetSAIClockFreq
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
Return SAIx clock frequency.
Definition: stm32l4xx_ll_rcc.c:847
LL_RCC_PLL_Enable
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
Enable PLL CR PLLON LL_RCC_PLL_Enable.
Definition: stm32l4xx_ll_rcc.h:3731
LL_RCC_PLLSAI2_DisableDomain_ADC
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
Disable PLLSAI2 output mapped on ADC domain clock.
Definition: stm32l4xx_ll_rcc.h:5355
LL_RCC_SetAPB2Prescaler
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
Set APB2 prescaler CFGR PPRE2 LL_RCC_SetAPB2Prescaler.
Definition: stm32l4xx_ll_rcc.h:2806
LL_RCC_PLLSAI2_GetQ
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
Get division factor for PLLSAI2Q.
Definition: stm32l4xx_ll_rcc.h:5203
LL_RCC_HSI_EnableInStopMode
__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
Enable HSI even in stop mode.
Definition: stm32l4xx_ll_rcc.h:2095
LL_RCC_ClearFlag_HSIRDY
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
Clear HSI ready interrupt flag CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY.
Definition: stm32l4xx_ll_rcc.h:5407
LL_RCC_GetLTDCClockSource
__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
Get LTDC Clock Source CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource.
Definition: stm32l4xx_ll_rcc.h:3605
LL_RCC_MSI_DisablePLLMode
__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
Disable MSI-PLL mode.
Definition: stm32l4xx_ll_rcc.h:2533
LL_RCC_IsActiveFlag_FWRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
Check if RCC flag FW reset is set or not. CSR FWRSTF LL_RCC_IsActiveFlag_FWRST.
Definition: stm32l4xx_ll_rcc.h:5609
LL_RCC_ClearFlag_PLLRDY
__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
Clear PLL ready interrupt flag CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY.
Definition: stm32l4xx_ll_rcc.h:5427
LL_RCC_ClearFlag_LSECSS
__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
Clear LSE Clock security system interrupt flag CICR LSECSSC LL_RCC_ClearFlag_LSECSS.
Definition: stm32l4xx_ll_rcc.h:5483
LL_RCC_IsEnabledIT_HSIRDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
Checks if HSI ready interrupt source is enabled or disabled. CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY...
Definition: stm32l4xx_ll_rcc.h:5949
LL_RCC_GetOCTOSPIClockFreq
uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
Return OCTOSPI clock frequency.
Definition: stm32l4xx_ll_rcc.c:1402
LL_RCC_PLLSAI1_GetP
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
Get SAI1PLL division factor for PLLSAI1P.
Definition: stm32l4xx_ll_rcc.h:4628
LL_RCC_EnableIT_PLLSAI2RDY
__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
Enable PLLSAI2 ready interrupt CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY.
Definition: stm32l4xx_ll_rcc.h:5792
LL_RCC_EnableRTC
__STATIC_INLINE void LL_RCC_EnableRTC(void)
Enable RTC BDCR RTCEN LL_RCC_EnableRTC.
Definition: stm32l4xx_ll_rcc.h:3672
LL_RCC_HSI_IsReady
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
Check if HSI clock is ready CR HSIRDY LL_RCC_HSI_IsReady.
Definition: stm32l4xx_ll_rcc.h:2145
LL_RCC_LSI_Enable
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
Enable LSI Oscillator CSR LSION LL_RCC_LSI_Enable.
Definition: stm32l4xx_ll_rcc.h:2422
LL_RCC_PLLSAI2_IsReady
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
Check if PLLSAI2 Ready CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady.
Definition: stm32l4xx_ll_rcc.h:4806
LL_RCC_LSCO_SetSource
__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
Configure Low speed clock selection BDCR LSCOSEL LL_RCC_LSCO_SetSource.
Definition: stm32l4xx_ll_rcc.h:2705
LL_RCC_IsEnabledIT_PLLSAI1RDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
Checks if PLLSAI1 ready interrupt source is enabled or disabled. CIER PLLSAI1RDYIE LL_RCC_IsEnabledI...
Definition: stm32l4xx_ll_rcc.h:5992
LL_RCC_DisableIT_HSI48RDY
__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
Disable HSI48 ready interrupt CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY.
Definition: stm32l4xx_ll_rcc.h:5874
LL_RCC_HSE_Enable
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
Enable HSE crystal oscillator (HSE ON) CR HSEON LL_RCC_HSE_Enable.
Definition: stm32l4xx_ll_rcc.h:2056
LL_RCC_HSI_GetCalibTrimming
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
Get HSI Calibration trimming ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming.
Definition: stm32l4xx_ll_rcc.h:2200
LL_RCC_PLLSAI2_EnableDomain_SAI
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
Enable PLLSAI2 output mapped on SAI domain clock PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_...
Definition: stm32l4xx_ll_rcc.h:5274
LL_RCC_HSI48_IsReady
__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
Check if HSI48 oscillator Ready CRRCR HSI48RDY LL_RCC_HSI48_IsReady.
Definition: stm32l4xx_ll_rcc.h:2239
LL_RCC_PLL_GetQ
__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
Get Main PLL division factor for PLLQ.
Definition: stm32l4xx_ll_rcc.h:4073
LL_RCC_IsActiveFlag_HSERDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
Check if HSE ready interrupt occurred or not CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY.
Definition: stm32l4xx_ll_rcc.h:5533
LL_RCC_IsEnabledIT_LSECSS
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
Checks if LSECSS interrupt source is enabled or disabled. CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS.
Definition: stm32l4xx_ll_rcc.h:6015
LL_RCC_DisableIT_HSERDY
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
Disable HSE ready interrupt CIER HSERDYIE LL_RCC_DisableIT_HSERDY.
Definition: stm32l4xx_ll_rcc.h:5853
LL_RCC_LSI_IsReady
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
Check if LSI is Ready CSR LSIRDY LL_RCC_LSI_IsReady.
Definition: stm32l4xx_ll_rcc.h:2442
LL_RCC_PLLSAI1_EnableDomain_ADC
__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
Enable PLLSAI1 output mapped on ADC domain clock PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_...
Definition: stm32l4xx_ll_rcc.h:4754
LL_RCC_PLLSAI1_GetQ
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
Get SAI1PLL division factor for PLLSAI1Q.
Definition: stm32l4xx_ll_rcc.h:4657
LL_RCC_PLLSAI1_EnableDomain_48M
__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
Enable PLLSAI1 output mapped on 48MHz domain clock PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomai...
Definition: stm32l4xx_ll_rcc.h:4732
LL_RCC_PLLSAI1_GetR
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
Get PLLSAI1 division factor for PLLSAIR.
Definition: stm32l4xx_ll_rcc.h:4672
LL_RCC_IsActiveFlag_PINRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
Check if RCC flag Pin reset is set or not. CSR PINRSTF LL_RCC_IsActiveFlag_PINRST.
Definition: stm32l4xx_ll_rcc.h:5649
LL_RCC_IsEnabledIT_LSIRDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
Checks if LSI ready interrupt source is enabled or disabled. CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY...
Definition: stm32l4xx_ll_rcc.h:5919
LL_RCC_EnableIT_PLLSAI1RDY
__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
Enable PLLSAI1 ready interrupt CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY.
Definition: stm32l4xx_ll_rcc.h:5780
LL_RCC_SetAHBPrescaler
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
Set AHB prescaler CFGR HPRE LL_RCC_SetAHBPrescaler.
Definition: stm32l4xx_ll_rcc.h:2774
LL_RCC_PLLSAI1_ConfigDomain_48M
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLLSAI1 used for 48Mhz domain clock.
Definition: stm32l4xx_ll_rcc.h:4274
LL_RCC_GetDSIClockFreq
uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
Return DSI clock frequency.
Definition: stm32l4xx_ll_rcc.c:1343
LL_RCC_ClearFlag_PLLSAI1RDY
__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
Clear PLLSAI1 ready interrupt flag CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY. ...
Definition: stm32l4xx_ll_rcc.h:5450
LL_RCC_SetLPTIMClockSource
__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
Configure LPTIMx clock source CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource.
Definition: stm32l4xx_ll_rcc.h:3031
LL_RCC_PLLSAI1_EnableDomain_SAI
__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
Enable PLLSAI1 output mapped on SAI domain clock PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_...
Definition: stm32l4xx_ll_rcc.h:4710
LL_RCC_GetClkAfterWakeFromStop
__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
Get Clock After Wake-Up From Stop mode CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop.
Definition: stm32l4xx_ll_rcc.h:2880
LL_RCC_PLL_ConfigDomain_48M
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLL used for 48Mhz domain clock.
Definition: stm32l4xx_ll_rcc.h:3960
LL_RCC_ClearFlag_PLLSAI2RDY
__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
Clear PLLSAI1 ready interrupt flag CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY. ...
Definition: stm32l4xx_ll_rcc.h:5462
LL_RCC_IsActiveFlag_PLLSAI1RDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
Check if PLLSAI1 ready interrupt occurred or not CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY.
Definition: stm32l4xx_ll_rcc.h:5566
LL_RCC_EnableIT_HSI48RDY
__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
Enable HSI48 ready interrupt CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY.
Definition: stm32l4xx_ll_rcc.h:5768
LL_RCC_MSI_GetRangeAfterStandby
__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
Get MSI range used after standby CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby.
Definition: stm32l4xx_ll_rcc.h:2630
LL_RCC_PLL_DisableDomain_48M
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
Disable PLL output mapped on 48MHz domain clock.
Definition: stm32l4xx_ll_rcc.h:4166
LL_RCC_SetSAIClockSource
__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
Configure SAIx clock source CCIPR SAIxSEL LL_RCC_SetSAIClockSource.
Definition: stm32l4xx_ll_rcc.h:3057
LL_RCC_LSE_DisablePropagation
__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
Disable LSE oscillator propagation.
Definition: stm32l4xx_ll_rcc.h:2383
LL_RCC_PLL_EnableDomain_SAI
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
Enable PLL output mapped on SAI domain clock PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI.
Definition: stm32l4xx_ll_rcc.h:4127
LL_RCC_GetADCClockFreq
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
Return ADCx clock frequency.
Definition: stm32l4xx_ll_rcc.c:1178
LL_RCC_ReleaseBackupDomainReset
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
Release the Backup domain reset BDCR BDRST LL_RCC_ReleaseBackupDomainReset.
Definition: stm32l4xx_ll_rcc.h:3712
LL_RCC_GetSysClkSource
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
Get the system clock source CFGR SWS LL_RCC_GetSysClkSource.
Definition: stm32l4xx_ll_rcc.h:2754
LL_RCC_PLLSAI2_DisableDomain_SAI
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
Disable PLLSAI2 output mapped on SAI domain clock.
Definition: stm32l4xx_ll_rcc.h:5286
LL_RCC_GetAPB1Prescaler
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
Get APB1 prescaler CFGR PPRE1 LL_RCC_GetAPB1Prescaler.
Definition: stm32l4xx_ll_rcc.h:2840
LL_RCC_SetUSBClockSource
__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
Configure USB clock source CCIPR CLK48SEL LL_RCC_SetUSBClockSource.
Definition: stm32l4xx_ll_rcc.h:3134
LL_RCC_LSI_GetPrediv
__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)
Get LSI division factor CSR LSIPREDIV LL_RCC_LSI_GetPrediv.
Definition: stm32l4xx_ll_rcc.h:2468
LL_RCC_GetSDMMCClockSource
__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
Get SDMMCx clock source CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource.
Definition: stm32l4xx_ll_rcc.h:3451
LL_RCC_PLLSAI2_ConfigDomain_LTDC
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
Configure PLLSAI2 used for LTDC domain clock.
Definition: stm32l4xx_ll_rcc.h:5079
LL_RCC_GetDFSDMAudioClockFreq
uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
Return DFSDMx Audio clock frequency.
Definition: stm32l4xx_ll_rcc.c:1296
LL_RCC_ClearFlag_HSERDY
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
Clear HSE ready interrupt flag CICR HSERDYC LL_RCC_ClearFlag_HSERDY.
Definition: stm32l4xx_ll_rcc.h:5417
LL_RCC_IsEnabledIT_PLLSAI2RDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
Checks if PLLSAI2 ready interrupt source is enabled or disabled. CIER PLLSAI2RDYIE LL_RCC_IsEnabledI...
Definition: stm32l4xx_ll_rcc.h:6004
LL_RCC_GetUARTClockFreq
uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
Return UARTx clock frequency.
Definition: stm32l4xx_ll_rcc.c:472
LL_RCC_SetLTDCClockSource
__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
Configure LTDC Clock Source CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource.
Definition: stm32l4xx_ll_rcc.h:3239
LL_RCC_LSE_DisableBypass
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
Disable external clock source (LSE bypass). BDCR LSEBYP LL_RCC_LSE_DisableBypass.
Definition: stm32l4xx_ll_rcc.h:2298
LL_RCC_GetOCTOSPIClockSource
__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
Get OCTOSPI clock source CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource.
Definition: stm32l4xx_ll_rcc.h:3622
LL_RCC_PLL_GetDivider
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
Get Division factor for the main PLL and other PLL PLLCFGR PLLM LL_RCC_PLL_GetDivider.
Definition: stm32l4xx_ll_rcc.h:4116
LL_RCC_EnableIT_LSIRDY
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
Enable LSI ready interrupt CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY.
Definition: stm32l4xx_ll_rcc.h:5707
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
LL_RCC_GetADCClockSource
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
Get ADCx clock source CCIPR ADCSEL LL_RCC_GetADCClockSource.
Definition: stm32l4xx_ll_rcc.h:3510
LL_RCC_PLLSAI2_Disable
__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
Disable PLLSAI2 CR PLLSAI2ON LL_RCC_PLLSAI2_Disable.
Definition: stm32l4xx_ll_rcc.h:4796
LL_RCC_HSE_DisableBypass
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
Disable HSE external oscillator (HSE Bypass) CR HSEBYP LL_RCC_HSE_DisableBypass. ...
Definition: stm32l4xx_ll_rcc.h:2046
LL_RCC_LSI_Disable
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
Disable LSI Oscillator CSR LSION LL_RCC_LSI_Disable.
Definition: stm32l4xx_ll_rcc.h:2432
LL_RCC_PLLSAI2_GetP
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
Get SAI2PLL division factor for PLLSAI2P.
Definition: stm32l4xx_ll_rcc.h:5173
LL_RCC_IsActiveFlag_IWDGRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
Check if RCC flag Independent Watchdog reset is set or not. CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST...
Definition: stm32l4xx_ll_rcc.h:5619
LL_RCC_PLL_IsReady
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
Check if PLL Ready CR PLLRDY LL_RCC_PLL_IsReady.
Definition: stm32l4xx_ll_rcc.h:3752
LL_RCC_GetLTDCClockFreq
uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
Return LTDC clock frequency.
Definition: stm32l4xx_ll_rcc.c:1378
LL_RCC_DisableIT_LSERDY
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
Disable LSE ready interrupt CIER LSERDYIE LL_RCC_DisableIT_LSERDY.
Definition: stm32l4xx_ll_rcc.h:5823
LL_RCC_MSI_EnableRangeSelection
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
Enable MSI clock range selection with MSIRANGE register.
Definition: stm32l4xx_ll_rcc.h:2546
LL_RCC_LSCO_Enable
__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
Enable Low speed clock BDCR LSCOEN LL_RCC_LSCO_Enable.
Definition: stm32l4xx_ll_rcc.h:2682
LL_RCC_MSI_IsReady
__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
Check if MSI oscillator Ready CR MSIRDY LL_RCC_MSI_IsReady.
Definition: stm32l4xx_ll_rcc.h:2507
LL_RCC_GetSDMMCKernelClockSource
__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
Get SDMMCx kernel clock source CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource. ...
Definition: stm32l4xx_ll_rcc.h:3431
LL_RCC_HSI_Disable
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
Disable HSI oscillator CR HSION LL_RCC_HSI_Disable.
Definition: stm32l4xx_ll_rcc.h:2135
LL_RCC_EnableIT_MSIRDY
__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
Enable MSI ready interrupt CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY.
Definition: stm32l4xx_ll_rcc.h:5727
LL_RCC_LSE_EnableCSS
__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
Enable Clock security system on LSE. BDCR LSECSSON LL_RCC_LSE_EnableCSS.
Definition: stm32l4xx_ll_rcc.h:2338
LL_RCC_PLL_ConfigDomain_SAI
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLL used for SAI domain clock.
Definition: stm32l4xx_ll_rcc.h:3906
LL_RCC_PLLSAI2_ConfigDomain_DSI
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
Configure PLLSAI2 used for DSI domain clock.
Definition: stm32l4xx_ll_rcc.h:5025
LL_RCC_PLL_GetMainSource
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
Get the oscillator used as PLL clock source. PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource.
Definition: stm32l4xx_ll_rcc.h:3990
LL_RCC_MSI_IsEnabledRangeSelect
__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
Check if MSI clock range is selected with MSIRANGE register CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSel...
Definition: stm32l4xx_ll_rcc.h:2556
LL_RCC_LSE_EnableBypass
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
Enable external clock source (LSE bypass). BDCR LSEBYP LL_RCC_LSE_EnableBypass.
Definition: stm32l4xx_ll_rcc.h:2288
LL_RCC_HSE_EnableBypass
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
Enable HSE external oscillator (HSE Bypass) CR HSEBYP LL_RCC_HSE_EnableBypass.
Definition: stm32l4xx_ll_rcc.h:2036
LL_RCC_SetAPB1Prescaler
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
Set APB1 prescaler CFGR PPRE1 LL_RCC_SetAPB1Prescaler.
Definition: stm32l4xx_ll_rcc.h:2790
LL_RCC_GetDFSDMClockFreq
uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
Return DFSDMx clock frequency.
Definition: stm32l4xx_ll_rcc.c:1263
LL_RCC_IsActiveFlag_SFTRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
Check if RCC flag Software reset is set or not. CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST.
Definition: stm32l4xx_ll_rcc.h:5659
LL_RCC_PLLSAI2_EnableDomain_DSI
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
Enable PLLSAI2 output mapped on DSI domain clock PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_...
Definition: stm32l4xx_ll_rcc.h:5297
LL_RCC_GetSystemClocksFreq
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks...
Definition: stm32l4xx_ll_rcc.c:329
LL_RCC_HSI_DisableInStopMode
__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
Disable HSI in stop mode CR HSIKERON LL_RCC_HSI_DisableInStopMode.
Definition: stm32l4xx_ll_rcc.h:2105
LL_RCC_MSI_Enable
__STATIC_INLINE void LL_RCC_MSI_Enable(void)
Enable MSI oscillator CR MSION LL_RCC_MSI_Enable.
Definition: stm32l4xx_ll_rcc.h:2487
LL_RCC_SetSDMMCClockSource
__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
Configure SDMMC1 clock source CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource.
Definition: stm32l4xx_ll_rcc.h:3097
LL_RCC_HSI_SetCalibTrimming
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
Set HSI Calibration trimming.
Definition: stm32l4xx_ll_rcc.h:2190
LL_RCC_SetSDMMCKernelClockSource
__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
Configure SDMMC1 kernel clock source CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource.
Definition: stm32l4xx_ll_rcc.h:3078
LL_RCC_GetDSIClockSource
__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
Get DSI Clock Source CCIPR2 DSISEL LL_RCC_GetDSIClockSource.
Definition: stm32l4xx_ll_rcc.h:3587
LL_RCC_DisableIT_MSIRDY
__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
Disable MSI ready interrupt CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY.
Definition: stm32l4xx_ll_rcc.h:5833
LL_RCC_SetSWPMIClockSource
__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
Configure SWPMI clock source CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource.
Definition: stm32l4xx_ll_rcc.h:3168
LL_RCC_MSI_GetCalibration
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
Get MSI Calibration value.
Definition: stm32l4xx_ll_rcc.h:2642
LL_RCC_GetDFSDMClockSource
__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
Get DFSDMx Kernel clock source CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource.
Definition: stm32l4xx_ll_rcc.h:3567
LL_RCC_PLL_Disable
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
Disable PLL.
Definition: stm32l4xx_ll_rcc.h:3742
LL_RCC_IsActiveFlag_HSIRDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
Check if HSI ready interrupt occurred or not CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY.
Definition: stm32l4xx_ll_rcc.h:5523
LL_RCC_GetUARTClockSource
__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
Get UARTx clock source CCIPR UARTxSEL LL_RCC_GetUARTClockSource.
Definition: stm32l4xx_ll_rcc.h:3308
LL_RCC_PLLSAI1_GetN
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
Get SAI1PLL multiplication factor for VCO PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN.
Definition: stm32l4xx_ll_rcc.h:4586
LL_RCC_SetOCTOSPIClockSource
__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
Configure OCTOSPI clock source CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource.
Definition: stm32l4xx_ll_rcc.h:3255
LL_RCC_PLLSAI2_GetR
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
Get SAI2PLL division factor for PLLSAI2R.
Definition: stm32l4xx_ll_rcc.h:5219
LL_RCC_PLLSAI2_ConfigDomain_ADC
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI2 used for ADC domain clock.
Definition: stm32l4xx_ll_rcc.h:5119
LL_RCC_SetLPUARTClockSource
__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
Configure LPUART1x clock source CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource.
Definition: stm32l4xx_ll_rcc.h:2986
LL_RCC_PLL_EnableDomain_SYS
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
Enable PLL output mapped on SYSCLK domain PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS.
Definition: stm32l4xx_ll_rcc.h:4176
LL_RCC_HSI_Enable
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
Enable HSI oscillator CR HSION LL_RCC_HSI_Enable.
Definition: stm32l4xx_ll_rcc.h:2125
LL_RCC_GetUSARTClockFreq
uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
Return USARTx clock frequency.
Definition: stm32l4xx_ll_rcc.c:355
LL_RCC_PLL_ConfigDomain_SYS
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLL used for SYSCLK Domain.
Definition: stm32l4xx_ll_rcc.h:3798
LL_RCC_EnableIT_LSECSS
__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
Enable LSE clock security system interrupt CIER LSECSSIE LL_RCC_EnableIT_LSECSS. ...
Definition: stm32l4xx_ll_rcc.h:5803
LL_RCC_LSE_Enable
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
Enable Low Speed External (LSE) crystal. BDCR LSEON LL_RCC_LSE_Enable.
Definition: stm32l4xx_ll_rcc.h:2268
LL_RCC_PLLSAI2_EnableDomain_LTDC
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
Enable PLLSAI2 output mapped on LTDC domain clock PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain...
Definition: stm32l4xx_ll_rcc.h:5321
LL_RCC_SetDSIClockSource
__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
Configure DSI clock source CCIPR2 DSISEL LL_RCC_SetDSIClockSource.
Definition: stm32l4xx_ll_rcc.h:3222
LL_RCC_GetSDMMCClockFreq
uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
Return SDMMCx clock frequency.
Definition: stm32l4xx_ll_rcc.c:984
LL_RCC_IsActiveFlag_BORRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
Check if RCC flag BOR reset is set or not. CSR BORRSTF LL_RCC_IsActiveFlag_BORRST.
Definition: stm32l4xx_ll_rcc.h:5679
LL_RCC_LSE_IsReady
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
Check if LSE oscillator Ready BDCR LSERDY LL_RCC_LSE_IsReady.
Definition: stm32l4xx_ll_rcc.h:2360
LL_RCC_LSE_Disable
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
Disable Low Speed External (LSE) crystal. BDCR LSEON LL_RCC_LSE_Disable.
Definition: stm32l4xx_ll_rcc.h:2278
LL_RCC_PLL_GetP
__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
Get Main PLL division factor for PLLP.
Definition: stm32l4xx_ll_rcc.h:4043
LL_RCC_ClocksTypeDef::HCLK_Frequency
uint32_t HCLK_Frequency
Definition: stm32l4xx_ll_rcc.h:82
LL_RCC_GetAHBPrescaler
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
Get AHB prescaler CFGR HPRE LL_RCC_GetAHBPrescaler.
Definition: stm32l4xx_ll_rcc.h:2825
LL_RCC_PLLSAI1_GetDivider
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
Get Division factor for the PLLSAI1 PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider.
Definition: stm32l4xx_ll_rcc.h:4699
LL_RCC_EnableIT_HSERDY
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
Enable HSE ready interrupt CIER HSERDYIE LL_RCC_EnableIT_HSERDY.
Definition: stm32l4xx_ll_rcc.h:5747
LL_RCC_GetI2CClockSource
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
Get I2Cx clock source CCIPR I2CxSEL LL_RCC_GetI2CClockSource.
Definition: stm32l4xx_ll_rcc.h:3356
LL_RCC_SetRTCClockSource
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
Set RTC Clock Source.
Definition: stm32l4xx_ll_rcc.h:3648
LL_RCC_PLL_DisableDomain_SAI
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
Disable PLL output mapped on SAI domain clock.
Definition: stm32l4xx_ll_rcc.h:4141
LL_RCC_GetLPTIMClockFreq
uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
Return LPTIMx clock frequency.
Definition: stm32l4xx_ll_rcc.c:735
LL_RCC_PLLSAI2_DisableDomain_LTDC
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
Disable PLLSAI2 output mapped on LTDC domain clock.
Definition: stm32l4xx_ll_rcc.h:5333
LL_RCC_PLLSAI2_EnableDomain_ADC
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
Enable PLLSAI2 output mapped on ADC domain clock PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_...
Definition: stm32l4xx_ll_rcc.h:5343
LL_RCC_IsActiveFlag_LSECSS
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
Check if LSE Clock security system interrupt occurred or not CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS...
Definition: stm32l4xx_ll_rcc.h:5599
LL_RCC_DisableIT_LSECSS
__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
Disable LSE clock security system interrupt CIER LSECSSIE LL_RCC_DisableIT_LSECSS.
Definition: stm32l4xx_ll_rcc.h:5909
LL_RCC_PLLSAI1_IsReady
__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
Check if PLLSAI1 Ready CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady.
Definition: stm32l4xx_ll_rcc.h:4229
LL_RCC_DisableRTC
__STATIC_INLINE void LL_RCC_DisableRTC(void)
Disable RTC BDCR RTCEN LL_RCC_DisableRTC.
Definition: stm32l4xx_ll_rcc.h:3682
LL_RCC_HSI_IsEnabledInStopMode
__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
Check if HSI is enabled in stop mode CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode. ...
Definition: stm32l4xx_ll_rcc.h:2115
LL_RCC_HSI_GetCalibration
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
Get HSI Calibration value.
Definition: stm32l4xx_ll_rcc.h:2176
LL_RCC_HSE_IsReady
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
Check if HSE oscillator Ready CR HSERDY LL_RCC_HSE_IsReady.
Definition: stm32l4xx_ll_rcc.h:2076
LL_RCC_IsActiveFlag_LPWRRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
Check if RCC flag Low Power reset is set or not. CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST.
Definition: stm32l4xx_ll_rcc.h:5629
LL_RCC_IsActiveFlag_LSIRDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
Check if LSI ready interrupt occurred or not CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY.
Definition: stm32l4xx_ll_rcc.h:5493
LL_RCC_GetLPUARTClockFreq
uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
Return LPUARTx clock frequency.
Definition: stm32l4xx_ll_rcc.c:688
LL_RCC_IsActiveFlag_PLLRDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
Check if PLL ready interrupt occurred or not CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY.
Definition: stm32l4xx_ll_rcc.h:5543
LL_RCC_DisableIT_PLLRDY
__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
Disable PLL ready interrupt CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY.
Definition: stm32l4xx_ll_rcc.h:5863
LL_RCC_GetUSARTClockSource
__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
Get USARTx clock source CCIPR USARTxSEL LL_RCC_GetUSARTClockSource.
Definition: stm32l4xx_ll_rcc.h:3286
LL_RCC_ClocksTypeDef::SYSCLK_Frequency
uint32_t SYSCLK_Frequency
Definition: stm32l4xx_ll_rcc.h:81
LL_RCC_SetI2CClockSource
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
Configure I2Cx clock source CCIPR I2CxSEL LL_RCC_SetI2CClockSource.
Definition: stm32l4xx_ll_rcc.h:3011
LL_RCC_ClearFlag_LSERDY
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
Clear LSE ready interrupt flag CICR LSERDYC LL_RCC_ClearFlag_LSERDY.
Definition: stm32l4xx_ll_rcc.h:5387
LL_RCC_HSI_DisableAutoFromStop
__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
Disable HSI Automatic from stop mode CR HSIASFS LL_RCC_HSI_DisableAutoFromStop.
Definition: stm32l4xx_ll_rcc.h:2165
LL_RCC_IsActiveFlag_HSECSS
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
Check if Clock security system interrupt occurred or not CIFR CSSF LL_RCC_IsActiveFlag_HSECSS.
Definition: stm32l4xx_ll_rcc.h:5589
LL_RCC_LSE_EnablePropagation
__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
Enable LSE oscillator propagation.
Definition: stm32l4xx_ll_rcc.h:2394
LL_RCC_GetRTCClockSource
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
Get RTC Clock Source BDCR RTCSEL LL_RCC_GetRTCClockSource.
Definition: stm32l4xx_ll_rcc.h:3662
LL_RCC_DisableIT_HSIRDY
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
Disable HSI ready interrupt CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY.
Definition: stm32l4xx_ll_rcc.h:5843
LL_RCC_PLLSAI2_GetDIVR
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
Get PLLSAI2 division factor for PLLSAI2DIVR.
Definition: stm32l4xx_ll_rcc.h:5263
LL_RCC_PLLSAI1_DisableDomain_SAI
__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
Disable PLLSAI1 output mapped on SAI domain clock.
Definition: stm32l4xx_ll_rcc.h:4722
LL_RCC_IsActiveFlag_PLLSAI2RDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
Check if PLLSAI1 ready interrupt occurred or not CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY.
Definition: stm32l4xx_ll_rcc.h:5578
LL_RCC_ClearFlag_LSIRDY
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
Clear LSI ready interrupt flag CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY.
Definition: stm32l4xx_ll_rcc.h:5377
LL_RCC_GetLPUARTClockSource
__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
Get LPUARTx clock source CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource.
Definition: stm32l4xx_ll_rcc.h:3325
LL_RCC_IsEnabledIT_HSI48RDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
Checks if HSI48 ready interrupt source is enabled or disabled. CIER HSI48RDYIE LL_RCC_IsEnabledIT_HS...
Definition: stm32l4xx_ll_rcc.h:5980
LL_RCC_GetUSBClockFreq
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
Return USBx clock frequency.
Definition: stm32l4xx_ll_rcc.c:1115
LL_RCC_IsEnabledRTC
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
Check if RTC has been enabled or not BDCR RTCEN LL_RCC_IsEnabledRTC.
Definition: stm32l4xx_ll_rcc.h:3692
LL_RCC_HSI48_Disable
__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
Disable HSI48 CRRCR HSI48ON LL_RCC_HSI48_Disable.
Definition: stm32l4xx_ll_rcc.h:2229
LL_RCC_MSI_EnablePLLMode
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
Enable MSI PLL-mode (Hardware auto calibration with LSE)
Definition: stm32l4xx_ll_rcc.h:2521
LL_RCC_DeInit
ErrorStatus LL_RCC_DeInit(void)
Reset the RCC clock configuration to the default reset state.
Definition: stm32l4xx_ll_rcc.c:192
LL_RCC_ClearFlag_HSECSS
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
Clear Clock security system interrupt flag CICR CSSC LL_RCC_ClearFlag_HSECSS.
Definition: stm32l4xx_ll_rcc.h:5473
LL_RCC_PLL_SetMainSource
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
Configure PLL clock source PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource.
Definition: stm32l4xx_ll_rcc.h:3976
LL_RCC_SetADCClockSource
__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
Configure ADC clock source CCIPR ADCSEL LL_RCC_SetADCClockSource.
Definition: stm32l4xx_ll_rcc.h:3153
LL_RCC_SetDFSDMClockSource
__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
Configure DFSDM Kernel clock source CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource.
Definition: stm32l4xx_ll_rcc.h:3203
LL_RCC_HSE_EnableCSS
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
Enable the Clock Security System. CR CSSON LL_RCC_HSE_EnableCSS.
Definition: stm32l4xx_ll_rcc.h:2026
LL_RCC_MSI_SetRangeAfterStandby
__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
Configure MSI range used after standby CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby.
Definition: stm32l4xx_ll_rcc.h:2616
LL_RCC_ConfigMCO
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
Configure MCOx CFGR MCOSEL LL_RCC_ConfigMCO CFGR MCOPRE LL_RCC_ConfigMCO.
Definition: stm32l4xx_ll_rcc.h:2917
LL_RCC_HSI48_GetCalibration
__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
Get HSI48 Calibration value CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration.
Definition: stm32l4xx_ll_rcc.h:2249
LL_RCC_SetDFSDMAudioClockSource
__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
Configure DFSDM Audio clock source CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource.
Definition: stm32l4xx_ll_rcc.h:3185
LL_RCC_PLLSAI1_ConfigDomain_ADC
__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
Configure PLLSAI1 used for ADC domain clock.
Definition: stm32l4xx_ll_rcc.h:4535
LL_RCC_SetSysClkSource
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
Configure the system clock source CFGR SW LL_RCC_SetSysClkSource.
Definition: stm32l4xx_ll_rcc.h:2740
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)
LL_RCC_GetSWPMIClockSource
__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
Get SWPMIx clock source CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource.
Definition: stm32l4xx_ll_rcc.h:3530
LL_RCC_MSI_GetRange
__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
Get the Internal Multi Speed oscillator (MSI) clock range in run mode. CR MSIRANGE LL_RCC_MSI_GetRan...
Definition: stm32l4xx_ll_rcc.h:2601
LL_RCC_IsActiveFlag_WWDGRST
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
Check if RCC flag Window Watchdog reset is set or not. CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST.
Definition: stm32l4xx_ll_rcc.h:5669
LL_RCC_GetSWPMIClockFreq
uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
Return SWPMIx clock frequency.
Definition: stm32l4xx_ll_rcc.c:1227
LL_RCC_GetI2CClockFreq
uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
Return I2Cx clock frequency.
Definition: stm32l4xx_ll_rcc.c:563
LL_RCC_HSI_EnableAutoFromStop
__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
Enable HSI Automatic from stop mode CR HSIASFS LL_RCC_HSI_EnableAutoFromStop.
Definition: stm32l4xx_ll_rcc.h:2155
LL_RCC_EnableIT_LSERDY
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
Enable LSE ready interrupt CIER LSERDYIE LL_RCC_EnableIT_LSERDY.
Definition: stm32l4xx_ll_rcc.h:5717
LL_RCC_DisableIT_PLLSAI1RDY
__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
Disable PLLSAI1 ready interrupt CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY.
Definition: stm32l4xx_ll_rcc.h:5886
LL_RCC_GetRNGClockSource
__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
Get RNGx clock source CCIPR CLK48SEL LL_RCC_GetRNGClockSource.
Definition: stm32l4xx_ll_rcc.h:3471
LL_RCC_LSE_SetDriveCapability
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
Set LSE oscillator drive capability.
Definition: stm32l4xx_ll_rcc.h:2314
LL_RCC_ForceBackupDomainReset
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
Force the Backup domain reset BDCR BDRST LL_RCC_ForceBackupDomainReset.
Definition: stm32l4xx_ll_rcc.h:3702
LL_RCC_MSI_GetCalibTrimming
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
Get MSI Calibration trimming ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming.
Definition: stm32l4xx_ll_rcc.h:2664
LL_RCC_GetAPB2Prescaler
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
Get APB2 prescaler CFGR PPRE2 LL_RCC_GetAPB2Prescaler.
Definition: stm32l4xx_ll_rcc.h:2855
LL_RCC_LSCO_Disable
__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
Disable Low speed clock BDCR LSCOEN LL_RCC_LSCO_Disable.
Definition: stm32l4xx_ll_rcc.h:2692
LL_RCC_GetDFSDMAudioClockSource
__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
Get DFSDM Audio Clock Source CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource.
Definition: stm32l4xx_ll_rcc.h:3548
LL_RCC_LSE_IsPropagationEnabled
__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void)
Check if LSE oscillator propagation is enabled BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled.
Definition: stm32l4xx_ll_rcc.h:2404
LL_RCC_PLLSAI2_ConfigDomain_SAI
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
Configure PLLSAI2 used for SAI domain clock.
Definition: stm32l4xx_ll_rcc.h:4877
LL_RCC_LSE_IsCSSDetected
__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
Check if CSS on LSE failure Detection BDCR LSECSSD LL_RCC_LSE_IsCSSDetected.
Definition: stm32l4xx_ll_rcc.h:2370
LL_RCC_SetClkAfterWakeFromStop
__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
Set Clock After Wake-Up From Stop mode CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop.
Definition: stm32l4xx_ll_rcc.h:2868
LL_RCC_IsEnabledIT_HSERDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
Checks if HSE ready interrupt source is enabled or disabled. CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY...
Definition: stm32l4xx_ll_rcc.h:5959
LL_RCC_PLLSAI1_Enable
__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
Enable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Enable.
Definition: stm32l4xx_ll_rcc.h:4209
LL_RCC_SetUSARTClockSource
__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
Configure USARTx clock source CCIPR USARTxSEL LL_RCC_SetUSARTClockSource.
Definition: stm32l4xx_ll_rcc.h:2950
LL_RCC_PLL_DisableDomain_SYS
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
Disable PLL output mapped on SYSCLK domain.
Definition: stm32l4xx_ll_rcc.h:4190
LL_RCC_MSI_SetRange
__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. CR MSIRANGE LL_RCC_MSI_...
Definition: stm32l4xx_ll_rcc.h:2579
LL_RCC_DisableIT_PLLSAI2RDY
__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
Disable PLLSAI2 ready interrupt CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY.
Definition: stm32l4xx_ll_rcc.h:5898
LL_RCC_MSI_SetCalibTrimming
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
Set MSI Calibration trimming.
Definition: stm32l4xx_ll_rcc.h:2654
LL_RCC_PLLSAI2_DisableDomain_DSI
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
Disable PLLSAI2 output mapped on DSI domain clock.
Definition: stm32l4xx_ll_rcc.h:5309
LL_RCC_IsEnabledIT_PLLRDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
Checks if PLL ready interrupt source is enabled or disabled. CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY...
Definition: stm32l4xx_ll_rcc.h:5969
LL_RCC_PLL_GetN
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
Get Main PLL multiplication factor for VCO PLLCFGR PLLN LL_RCC_PLL_GetN.
Definition: stm32l4xx_ll_rcc.h:4000
LL_RCC_PLLSAI1_DisableDomain_ADC
__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
Disable PLLSAI1 output mapped on ADC domain clock.
Definition: stm32l4xx_ll_rcc.h:4766
LL_RCC_SetUARTClockSource
__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
Configure UARTx clock source CCIPR UARTxSEL LL_RCC_SetUARTClockSource.
Definition: stm32l4xx_ll_rcc.h:2970
LL_RCC_GetLPTIMClockSource
__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
Get LPTIMx clock source CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource.
Definition: stm32l4xx_ll_rcc.h:3378
LL_RCC_LSI_SetPrediv
__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)
Set LSI division factor CSR LSIPREDIV LL_RCC_LSI_SetPrediv.
Definition: stm32l4xx_ll_rcc.h:2456
LL_RCC_IsEnabledIT_LSERDY
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
Checks if LSE ready interrupt source is enabled or disabled. CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY...
Definition: stm32l4xx_ll_rcc.h:5929
LL_RCC_PLL_GetR
__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
Get Main PLL division factor for PLLR.
Definition: stm32l4xx_ll_rcc.h:4088
LL_RCC_LSE_GetDriveCapability
__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
Get LSE oscillator drive capability BDCR LSEDRV LL_RCC_LSE_GetDriveCapability.
Definition: stm32l4xx_ll_rcc.h:2328
LL_RCC_PLLSAI1_Disable
__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
Disable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Disable.
Definition: stm32l4xx_ll_rcc.h:4219
LL_RCC_ClearResetFlags
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
Set RMVF bit to clear the reset flags. CSR RMVF LL_RCC_ClearResetFlags.
Definition: stm32l4xx_ll_rcc.h:5689
LL_RCC_LSE_DisableCSS
__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
Disable Clock security system on LSE.
Definition: stm32l4xx_ll_rcc.h:2350
LL_RCC_PLLSAI2_Enable
__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
Enable PLLSAI2 CR PLLSAI2ON LL_RCC_PLLSAI2_Enable.
Definition: stm32l4xx_ll_rcc.h:4786
LL_RCC_GetSAIClockSource
__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
Get SAIx clock source CCIPR SAIxSEL LL_RCC_GetSAIClockSource.
Definition: stm32l4xx_ll_rcc.h:3408
LL_RCC_IsActiveFlag_LSERDY
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
Check if LSE ready interrupt occurred or not CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY.
Definition: stm32l4xx_ll_rcc.h:5503
LL_RCC_GetUSBClockSource
__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
Get USBx clock source CCIPR CLK48SEL LL_RCC_GetUSBClockSource.
Definition: stm32l4xx_ll_rcc.h:3491
LL_RCC_SetRNGClockSource
__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
Configure RNG clock source CCIPR CLK48SEL LL_RCC_SetRNGClockSource.
Definition: stm32l4xx_ll_rcc.h:3115
LL_RCC_DisableIT_LSIRDY
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
Disable LSI ready interrupt CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY.
Definition: stm32l4xx_ll_rcc.h:5813
LL_RCC_MSI_Disable
__STATIC_INLINE void LL_RCC_MSI_Disable(void)
Disable MSI oscillator CR MSION LL_RCC_MSI_Disable.
Definition: stm32l4xx_ll_rcc.h:2497
LL_RCC_LSCO_GetSource
__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
Get Low speed clock selection BDCR LSCOSEL LL_RCC_LSCO_GetSource.
Definition: stm32l4xx_ll_rcc.h:2717