PLLSAI1

Functions
__STATIC_INLINE void	LL_RCC_PLLSAI1_Enable (void)
	Enable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Enable. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_Disable (void)
	Disable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Disable. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_IsReady (void)
	Check if PLLSAI1 Ready CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLLSAI1 used for 48Mhz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLLSAI1 used for SAI domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLLSAI1 used for ADC domain clock. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetN (void)
	Get SAI1PLL multiplication factor for VCO PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetP (void)
	Get SAI1PLL division factor for PLLSAI1P. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetQ (void)
	Get SAI1PLL division factor for PLLSAI1Q. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetR (void)
	Get PLLSAI1 division factor for PLLSAIR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI1_GetDivider (void)
	Get Division factor for the PLLSAI1 PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_SAI (void)
	Enable PLLSAI1 output mapped on SAI domain clock PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_SAI (void)
	Disable PLLSAI1 output mapped on SAI domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_48M (void)
	Enable PLLSAI1 output mapped on 48MHz domain clock PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_48M (void)
	Disable PLLSAI1 output mapped on 48MHz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_EnableDomain_ADC (void)
	Enable PLLSAI1 output mapped on ADC domain clock PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC. More...
__STATIC_INLINE void	LL_RCC_PLLSAI1_DisableDomain_ADC (void)
	Disable PLLSAI1 output mapped on ADC domain clock. More...

Detailed Description

Function Documentation

LL_RCC_PLLSAI1_ConfigDomain_48M()

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ
	)

Configure PLLSAI1 used for 48Mhz domain clock.

Note

PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.

This can be selected for USB, RNG, SDMMC PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLSAI1M_DIV_1 LL_RCC_PLLSAI1M_DIV_2 LL_RCC_PLLSAI1M_DIV_3 LL_RCC_PLLSAI1M_DIV_4 LL_RCC_PLLSAI1M_DIV_5 LL_RCC_PLLSAI1M_DIV_6 LL_RCC_PLLSAI1M_DIV_7 LL_RCC_PLLSAI1M_DIV_8 LL_RCC_PLLSAI1M_DIV_9 LL_RCC_PLLSAI1M_DIV_10 LL_RCC_PLLSAI1M_DIV_11 LL_RCC_PLLSAI1M_DIV_12 LL_RCC_PLLSAI1M_DIV_13 LL_RCC_PLLSAI1M_DIV_14 LL_RCC_PLLSAI1M_DIV_15 LL_RCC_PLLSAI1M_DIV_16
PLLN	Between 8 and 86
PLLQ	This parameter can be one of the following values: LL_RCC_PLLSAI1Q_DIV_2 LL_RCC_PLLSAI1Q_DIV_4 LL_RCC_PLLSAI1Q_DIV_6 LL_RCC_PLLSAI1Q_DIV_8

Return values

None

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.

This can be selected for USB, RNG, SDMMC PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M
PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86
PLLQ	This parameter can be one of the following values: LL_RCC_PLLSAI1Q_DIV_2 LL_RCC_PLLSAI1Q_DIV_4 LL_RCC_PLLSAI1Q_DIV_6 LL_RCC_PLLSAI1Q_DIV_8

Return values

None

Definition at line 4274 of file stm32l4xx_ll_rcc.h.

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
             PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ);
}

LL_RCC_PLLSAI1_ConfigDomain_ADC()

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLLSAI1 used for ADC domain clock.

Note

PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.

This can be selected for ADC PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLSAI1M_DIV_1 LL_RCC_PLLSAI1M_DIV_2 LL_RCC_PLLSAI1M_DIV_3 LL_RCC_PLLSAI1M_DIV_4 LL_RCC_PLLSAI1M_DIV_5 LL_RCC_PLLSAI1M_DIV_6 LL_RCC_PLLSAI1M_DIV_7 LL_RCC_PLLSAI1M_DIV_8 LL_RCC_PLLSAI1M_DIV_9 LL_RCC_PLLSAI1M_DIV_10 LL_RCC_PLLSAI1M_DIV_11 LL_RCC_PLLSAI1M_DIV_12 LL_RCC_PLLSAI1M_DIV_13 LL_RCC_PLLSAI1M_DIV_14 LL_RCC_PLLSAI1M_DIV_15 LL_RCC_PLLSAI1M_DIV_16
PLLN	Between 8 and 86
PLLR	This parameter can be one of the following values: LL_RCC_PLLSAI1R_DIV_2 LL_RCC_PLLSAI1R_DIV_4 LL_RCC_PLLSAI1R_DIV_6 LL_RCC_PLLSAI1R_DIV_8

Return values

None

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLN/PLLR can be written only when PLLSAI1 is disabled.

This can be selected for ADC PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC
PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86
PLLR	This parameter can be one of the following values: LL_RCC_PLLSAI1R_DIV_2 LL_RCC_PLLSAI1R_DIV_4 LL_RCC_PLLSAI1R_DIV_6 LL_RCC_PLLSAI1R_DIV_8

Return values

None

Definition at line 4535 of file stm32l4xx_ll_rcc.h.

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
             PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR);
}

LL_RCC_PLLSAI1_ConfigDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP
	)

Configure PLLSAI1 used for SAI domain clock.

Note

PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.

This can be selected for SAI1 or SAI2 PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLSAI1M_DIV_1 LL_RCC_PLLSAI1M_DIV_2 LL_RCC_PLLSAI1M_DIV_3 LL_RCC_PLLSAI1M_DIV_4 LL_RCC_PLLSAI1M_DIV_5 LL_RCC_PLLSAI1M_DIV_6 LL_RCC_PLLSAI1M_DIV_7 LL_RCC_PLLSAI1M_DIV_8 LL_RCC_PLLSAI1M_DIV_9 LL_RCC_PLLSAI1M_DIV_10 LL_RCC_PLLSAI1M_DIV_11 LL_RCC_PLLSAI1M_DIV_12 LL_RCC_PLLSAI1M_DIV_13 LL_RCC_PLLSAI1M_DIV_14 LL_RCC_PLLSAI1M_DIV_15 LL_RCC_PLLSAI1M_DIV_16
PLLN	Between 8 and 86
PLLP	This parameter can be one of the following values: LL_RCC_PLLSAI1P_DIV_2 LL_RCC_PLLSAI1P_DIV_3 LL_RCC_PLLSAI1P_DIV_4 LL_RCC_PLLSAI1P_DIV_5 LL_RCC_PLLSAI1P_DIV_6 LL_RCC_PLLSAI1P_DIV_7 LL_RCC_PLLSAI1P_DIV_8 LL_RCC_PLLSAI1P_DIV_9 LL_RCC_PLLSAI1P_DIV_10 LL_RCC_PLLSAI1P_DIV_11 LL_RCC_PLLSAI1P_DIV_12 LL_RCC_PLLSAI1P_DIV_13 LL_RCC_PLLSAI1P_DIV_14 LL_RCC_PLLSAI1P_DIV_15 LL_RCC_PLLSAI1P_DIV_16 LL_RCC_PLLSAI1P_DIV_17 LL_RCC_PLLSAI1P_DIV_18 LL_RCC_PLLSAI1P_DIV_19 LL_RCC_PLLSAI1P_DIV_20 LL_RCC_PLLSAI1P_DIV_21 LL_RCC_PLLSAI1P_DIV_22 LL_RCC_PLLSAI1P_DIV_23 LL_RCC_PLLSAI1P_DIV_24 LL_RCC_PLLSAI1P_DIV_25 LL_RCC_PLLSAI1P_DIV_26 LL_RCC_PLLSAI1P_DIV_27 LL_RCC_PLLSAI1P_DIV_28 LL_RCC_PLLSAI1P_DIV_29 LL_RCC_PLLSAI1P_DIV_30 LL_RCC_PLLSAI1P_DIV_31

Return values

None

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.

This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86
PLLP	This parameter can be one of the following values: LL_RCC_PLLSAI1P_DIV_2 LL_RCC_PLLSAI1P_DIV_3 LL_RCC_PLLSAI1P_DIV_4 LL_RCC_PLLSAI1P_DIV_5 LL_RCC_PLLSAI1P_DIV_6 LL_RCC_PLLSAI1P_DIV_7 LL_RCC_PLLSAI1P_DIV_8 LL_RCC_PLLSAI1P_DIV_9 LL_RCC_PLLSAI1P_DIV_10 LL_RCC_PLLSAI1P_DIV_11 LL_RCC_PLLSAI1P_DIV_12 LL_RCC_PLLSAI1P_DIV_13 LL_RCC_PLLSAI1P_DIV_14 LL_RCC_PLLSAI1P_DIV_15 LL_RCC_PLLSAI1P_DIV_16 LL_RCC_PLLSAI1P_DIV_17 LL_RCC_PLLSAI1P_DIV_18 LL_RCC_PLLSAI1P_DIV_19 LL_RCC_PLLSAI1P_DIV_20 LL_RCC_PLLSAI1P_DIV_21 LL_RCC_PLLSAI1P_DIV_22 LL_RCC_PLLSAI1P_DIV_23 LL_RCC_PLLSAI1P_DIV_24 LL_RCC_PLLSAI1P_DIV_25 LL_RCC_PLLSAI1P_DIV_26 LL_RCC_PLLSAI1P_DIV_27 LL_RCC_PLLSAI1P_DIV_28 LL_RCC_PLLSAI1P_DIV_29 LL_RCC_PLLSAI1P_DIV_30 LL_RCC_PLLSAI1P_DIV_31

Return values

None

Note

PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.

PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.

This can be selected for SAI1 or SAI2 (*) PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI
PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_1 LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8
PLLN	Between 8 and 86
PLLP	This parameter can be one of the following values: LL_RCC_PLLSAI1P_DIV_7 LL_RCC_PLLSAI1P_DIV_17

Return values

None

Definition at line 4386 of file stm32l4xx_ll_rcc.h.

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
             PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP);
}

LL_RCC_PLLSAI1_Disable()

__STATIC_INLINE void LL_RCC_PLLSAI1_Disable

(

void

)

Disable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Disable.

Return values

None

Definition at line 4219 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
}

LL_RCC_PLLSAI1_DisableDomain_48M()

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M

(

void

)

Disable PLLSAI1 output mapped on 48MHz domain clock.

Note

In order to save power, when of the PLLSAI1 is not used, should be 0 PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M

Return values

None

Definition at line 4744 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
}

LL_RCC_PLLSAI1_DisableDomain_ADC()

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC

(

void

)

Disable PLLSAI1 output mapped on ADC domain clock.

Note

In order to save power, when of the PLLSAI1 is not used, Main PLLSAI1 should be 0 PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC

Return values

None

Definition at line 4766 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
}

LL_RCC_PLLSAI1_DisableDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI

(

void

)

Disable PLLSAI1 output mapped on SAI domain clock.

Note

In order to save power, when of the PLLSAI1 is not used, should be 0 PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI

Return values

None

Definition at line 4722 of file stm32l4xx_ll_rcc.h.

{
  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
}

LL_RCC_PLLSAI1_Enable()

__STATIC_INLINE void LL_RCC_PLLSAI1_Enable

(

void

)

Enable PLLSAI1 CR PLLSAI1ON LL_RCC_PLLSAI1_Enable.

Return values

None

Definition at line 4209 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
}

LL_RCC_PLLSAI1_EnableDomain_48M()

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M

(

void

)

Enable PLLSAI1 output mapped on 48MHz domain clock PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M.

Return values

None

Definition at line 4732 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
}

LL_RCC_PLLSAI1_EnableDomain_ADC()

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC

(

void

)

Enable PLLSAI1 output mapped on ADC domain clock PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC.

Return values

None

Definition at line 4754 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
}

LL_RCC_PLLSAI1_EnableDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI

(

void

)

Enable PLLSAI1 output mapped on SAI domain clock PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI.

Return values

None

Definition at line 4710 of file stm32l4xx_ll_rcc.h.

{
  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
}

LL_RCC_PLLSAI1_GetDivider()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider

(

void

)

Get Division factor for the PLLSAI1 PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider.

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAI1M_DIV_1 LL_RCC_PLLSAI1M_DIV_2 LL_RCC_PLLSAI1M_DIV_3 LL_RCC_PLLSAI1M_DIV_4 LL_RCC_PLLSAI1M_DIV_5 LL_RCC_PLLSAI1M_DIV_6 LL_RCC_PLLSAI1M_DIV_7 LL_RCC_PLLSAI1M_DIV_8 LL_RCC_PLLSAI1M_DIV_9 LL_RCC_PLLSAI1M_DIV_10 LL_RCC_PLLSAI1M_DIV_11 LL_RCC_PLLSAI1M_DIV_12 LL_RCC_PLLSAI1M_DIV_13 LL_RCC_PLLSAI1M_DIV_14 LL_RCC_PLLSAI1M_DIV_15 LL_RCC_PLLSAI1M_DIV_16

Definition at line 4699 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
}

LL_RCC_PLLSAI1_GetN()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN

(

void

)

Get SAI1PLL multiplication factor for VCO PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN.

Return values

Between

8 and 86

Definition at line 4586 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
}

LL_RCC_PLLSAI1_GetP()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP

(

void

)

Get SAI1PLL division factor for PLLSAI1P.

Note

Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAI1P_DIV_2 LL_RCC_PLLSAI1P_DIV_3 LL_RCC_PLLSAI1P_DIV_4 LL_RCC_PLLSAI1P_DIV_5 LL_RCC_PLLSAI1P_DIV_6 LL_RCC_PLLSAI1P_DIV_7 LL_RCC_PLLSAI1P_DIV_8 LL_RCC_PLLSAI1P_DIV_9 LL_RCC_PLLSAI1P_DIV_10 LL_RCC_PLLSAI1P_DIV_11 LL_RCC_PLLSAI1P_DIV_12 LL_RCC_PLLSAI1P_DIV_13 LL_RCC_PLLSAI1P_DIV_14 LL_RCC_PLLSAI1P_DIV_15 LL_RCC_PLLSAI1P_DIV_16 LL_RCC_PLLSAI1P_DIV_17 LL_RCC_PLLSAI1P_DIV_18 LL_RCC_PLLSAI1P_DIV_19 LL_RCC_PLLSAI1P_DIV_20 LL_RCC_PLLSAI1P_DIV_21 LL_RCC_PLLSAI1P_DIV_22 LL_RCC_PLLSAI1P_DIV_23 LL_RCC_PLLSAI1P_DIV_24 LL_RCC_PLLSAI1P_DIV_25 LL_RCC_PLLSAI1P_DIV_26 LL_RCC_PLLSAI1P_DIV_27 LL_RCC_PLLSAI1P_DIV_28 LL_RCC_PLLSAI1P_DIV_29 LL_RCC_PLLSAI1P_DIV_30 LL_RCC_PLLSAI1P_DIV_31

Note

Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAI1P_DIV_7 LL_RCC_PLLSAI1P_DIV_17

Definition at line 4628 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
}

LL_RCC_PLLSAI1_GetQ()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ

(

void

)

Get SAI1PLL division factor for PLLSAI1Q.

Note

Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAI1Q_DIV_2 LL_RCC_PLLSAI1Q_DIV_4 LL_RCC_PLLSAI1Q_DIV_6 LL_RCC_PLLSAI1Q_DIV_8

Definition at line 4657 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
}

LL_RCC_PLLSAI1_GetR()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR

(

void

)

Get PLLSAI1 division factor for PLLSAIR.

Note

Used for PLLADC1CLK (ADC clock) PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAI1R_DIV_2 LL_RCC_PLLSAI1R_DIV_4 LL_RCC_PLLSAI1R_DIV_6 LL_RCC_PLLSAI1R_DIV_8

Definition at line 4672 of file stm32l4xx_ll_rcc.h.

{
  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
}

LL_RCC_PLLSAI1_IsReady()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady

(

void

)

Check if PLLSAI1 Ready CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady.

Return values

State

of bit (1 or 0).

Definition at line 4229 of file stm32l4xx_ll_rcc.h.

{
  return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL);
}