STM32L4xx_HAL_Driver  1.14.0
Functions
PLLSAI2
STM32L4xx_LL_Driver » RCC » RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_PLLSAI2_Enable (void)
 Enable PLLSAI2 CR PLLSAI2ON LL_RCC_PLLSAI2_Enable. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_Disable (void)
 Disable PLLSAI2 CR PLLSAI2ON LL_RCC_PLLSAI2_Disable. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady (void)
 Check if PLLSAI2 Ready CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
 Configure PLLSAI2 used for SAI domain clock. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
 Configure PLLSAI2 used for DSI domain clock. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
 Configure PLLSAI2 used for LTDC domain clock. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
 Configure PLLSAI2 used for ADC domain clock. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN (void)
 Get SAI2PLL multiplication factor for VCO PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP (void)
 Get SAI2PLL division factor for PLLSAI2P. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ (void)
 Get division factor for PLLSAI2Q. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR (void)
 Get SAI2PLL division factor for PLLSAI2R. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider (void)
 Get Division factor for the PLLSAI2 PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider. More...
 
__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR (void)
 Get PLLSAI2 division factor for PLLSAI2DIVR. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI (void)
 Enable PLLSAI2 output mapped on SAI domain clock PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI (void)
 Disable PLLSAI2 output mapped on SAI domain clock. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI (void)
 Enable PLLSAI2 output mapped on DSI domain clock PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI (void)
 Disable PLLSAI2 output mapped on DSI domain clock. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC (void)
 Enable PLLSAI2 output mapped on LTDC domain clock PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC (void)
 Disable PLLSAI2 output mapped on LTDC domain clock. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC (void)
 Enable PLLSAI2 output mapped on ADC domain clock PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC. More...
 
__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC (void)
 Disable PLLSAI2 output mapped on ADC domain clock. More...
 

Detailed Description

Function Documentation

◆ LL_RCC_PLLSAI2_ConfigDomain_ADC()

__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLR 
)

Configure PLLSAI2 used for ADC domain clock.

Note
PLL Source and PLLM Divider can be written only when PLL, PLLSAI2 and PLLSAI2 are disabled.
PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
This can be selected for ADC PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC
PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC
PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
Parameters
SourceThis parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLRThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2R_DIV_2
  • LL_RCC_PLLSAI2R_DIV_4
  • LL_RCC_PLLSAI2R_DIV_6
  • LL_RCC_PLLSAI2R_DIV_8
Return values
None

Definition at line 5119 of file stm32l4xx_ll_rcc.h.

5120 {
5121  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
5122  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
5123 }
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)

◆ LL_RCC_PLLSAI2_ConfigDomain_DSI()

__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLQ 
)

Configure PLLSAI2 used for DSI domain clock.

Note
PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
This can be selected for DSI PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI
PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI
PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
Parameters
SourceThis parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2M_DIV_1
  • LL_RCC_PLLSAI2M_DIV_2
  • LL_RCC_PLLSAI2M_DIV_3
  • LL_RCC_PLLSAI2M_DIV_4
  • LL_RCC_PLLSAI2M_DIV_5
  • LL_RCC_PLLSAI2M_DIV_6
  • LL_RCC_PLLSAI2M_DIV_7
  • LL_RCC_PLLSAI2M_DIV_8
  • LL_RCC_PLLSAI2M_DIV_9
  • LL_RCC_PLLSAI2M_DIV_10
  • LL_RCC_PLLSAI2M_DIV_11
  • LL_RCC_PLLSAI2M_DIV_12
  • LL_RCC_PLLSAI2M_DIV_13
  • LL_RCC_PLLSAI2M_DIV_14
  • LL_RCC_PLLSAI2M_DIV_15
  • LL_RCC_PLLSAI2M_DIV_16
PLLNBetween 8 and 86
PLLQThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2Q_DIV_2
  • LL_RCC_PLLSAI2Q_DIV_4
  • LL_RCC_PLLSAI2Q_DIV_6
  • LL_RCC_PLLSAI2Q_DIV_8
Return values
None

Definition at line 5025 of file stm32l4xx_ll_rcc.h.

5026 {
5027  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5028  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
5029  (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM);
5030 }
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)

◆ LL_RCC_PLLSAI2_ConfigDomain_LTDC()

__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLR,
uint32_t  PLLDIVR 
)

Configure PLLSAI2 used for LTDC domain clock.

Note
PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
This can be selected for LTDC PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC
PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC
PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC
CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
Parameters
SourceThis parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2M_DIV_1
  • LL_RCC_PLLSAI2M_DIV_2
  • LL_RCC_PLLSAI2M_DIV_3
  • LL_RCC_PLLSAI2M_DIV_4
  • LL_RCC_PLLSAI2M_DIV_5
  • LL_RCC_PLLSAI2M_DIV_6
  • LL_RCC_PLLSAI2M_DIV_7
  • LL_RCC_PLLSAI2M_DIV_8
  • LL_RCC_PLLSAI2M_DIV_9
  • LL_RCC_PLLSAI2M_DIV_10
  • LL_RCC_PLLSAI2M_DIV_11
  • LL_RCC_PLLSAI2M_DIV_12
  • LL_RCC_PLLSAI2M_DIV_13
  • LL_RCC_PLLSAI2M_DIV_14
  • LL_RCC_PLLSAI2M_DIV_15
  • LL_RCC_PLLSAI2M_DIV_16
PLLNBetween 8 and 86
PLLRThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2R_DIV_2
  • LL_RCC_PLLSAI2R_DIV_4
  • LL_RCC_PLLSAI2R_DIV_6
  • LL_RCC_PLLSAI2R_DIV_8
PLLDIVRThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2DIVR_DIV_2
  • LL_RCC_PLLSAI2DIVR_DIV_4
  • LL_RCC_PLLSAI2DIVR_DIV_8
  • LL_RCC_PLLSAI2DIVR_DIV_16
Return values
None

Definition at line 5079 of file stm32l4xx_ll_rcc.h.

5080 {
5081  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5082  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
5083  (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM);
5084  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
5085 }
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)

◆ LL_RCC_PLLSAI2_ConfigDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI ( uint32_t  Source,
uint32_t  PLLM,
uint32_t  PLLN,
uint32_t  PLLP 
)

Configure PLLSAI2 used for SAI domain clock.

Note
PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
This can be selected for SAI1 or SAI2 PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
Parameters
SourceThis parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2M_DIV_1
  • LL_RCC_PLLSAI2M_DIV_2
  • LL_RCC_PLLSAI2M_DIV_3
  • LL_RCC_PLLSAI2M_DIV_4
  • LL_RCC_PLLSAI2M_DIV_5
  • LL_RCC_PLLSAI2M_DIV_6
  • LL_RCC_PLLSAI2M_DIV_7
  • LL_RCC_PLLSAI2M_DIV_8
  • LL_RCC_PLLSAI2M_DIV_9
  • LL_RCC_PLLSAI2M_DIV_10
  • LL_RCC_PLLSAI2M_DIV_11
  • LL_RCC_PLLSAI2M_DIV_12
  • LL_RCC_PLLSAI2M_DIV_13
  • LL_RCC_PLLSAI2M_DIV_14
  • LL_RCC_PLLSAI2M_DIV_15
  • LL_RCC_PLLSAI2M_DIV_16
PLLNBetween 8 and 86
PLLPThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_2
  • LL_RCC_PLLSAI2P_DIV_3
  • LL_RCC_PLLSAI2P_DIV_4
  • LL_RCC_PLLSAI2P_DIV_5
  • LL_RCC_PLLSAI2P_DIV_6
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_8
  • LL_RCC_PLLSAI2P_DIV_9
  • LL_RCC_PLLSAI2P_DIV_10
  • LL_RCC_PLLSAI2P_DIV_11
  • LL_RCC_PLLSAI2P_DIV_12
  • LL_RCC_PLLSAI2P_DIV_13
  • LL_RCC_PLLSAI2P_DIV_14
  • LL_RCC_PLLSAI2P_DIV_15
  • LL_RCC_PLLSAI2P_DIV_16
  • LL_RCC_PLLSAI2P_DIV_17
  • LL_RCC_PLLSAI2P_DIV_18
  • LL_RCC_PLLSAI2P_DIV_19
  • LL_RCC_PLLSAI2P_DIV_20
  • LL_RCC_PLLSAI2P_DIV_21
  • LL_RCC_PLLSAI2P_DIV_22
  • LL_RCC_PLLSAI2P_DIV_23
  • LL_RCC_PLLSAI2P_DIV_24
  • LL_RCC_PLLSAI2P_DIV_25
  • LL_RCC_PLLSAI2P_DIV_26
  • LL_RCC_PLLSAI2P_DIV_27
  • LL_RCC_PLLSAI2P_DIV_28
  • LL_RCC_PLLSAI2P_DIV_29
  • LL_RCC_PLLSAI2P_DIV_30
  • LL_RCC_PLLSAI2P_DIV_31
Return values
None
Note
PLL Source and PLLM Divider can be written only when PLL, PLLSAI1 and PLLSAI2 are disabled.
PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
This can be selected for SAI1 or SAI2 PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
Parameters
SourceThis parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLPThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_2
  • LL_RCC_PLLSAI2P_DIV_3
  • LL_RCC_PLLSAI2P_DIV_4
  • LL_RCC_PLLSAI2P_DIV_5
  • LL_RCC_PLLSAI2P_DIV_6
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_8
  • LL_RCC_PLLSAI2P_DIV_9
  • LL_RCC_PLLSAI2P_DIV_10
  • LL_RCC_PLLSAI2P_DIV_11
  • LL_RCC_PLLSAI2P_DIV_12
  • LL_RCC_PLLSAI2P_DIV_13
  • LL_RCC_PLLSAI2P_DIV_14
  • LL_RCC_PLLSAI2P_DIV_15
  • LL_RCC_PLLSAI2P_DIV_16
  • LL_RCC_PLLSAI2P_DIV_17
  • LL_RCC_PLLSAI2P_DIV_18
  • LL_RCC_PLLSAI2P_DIV_19
  • LL_RCC_PLLSAI2P_DIV_20
  • LL_RCC_PLLSAI2P_DIV_21
  • LL_RCC_PLLSAI2P_DIV_22
  • LL_RCC_PLLSAI2P_DIV_23
  • LL_RCC_PLLSAI2P_DIV_24
  • LL_RCC_PLLSAI2P_DIV_25
  • LL_RCC_PLLSAI2P_DIV_26
  • LL_RCC_PLLSAI2P_DIV_27
  • LL_RCC_PLLSAI2P_DIV_28
  • LL_RCC_PLLSAI2P_DIV_29
  • LL_RCC_PLLSAI2P_DIV_30
  • LL_RCC_PLLSAI2P_DIV_31
Return values
None
Note
PLL Source and PLLM Divider can be written only when PLL, PLLSAI2 and PLLSAI2 are disabled.
PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
This can be selected for SAI1 or SAI2 PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI
PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
Parameters
SourceThis parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_NONE
  • LL_RCC_PLLSOURCE_MSI
  • LL_RCC_PLLSOURCE_HSI
  • LL_RCC_PLLSOURCE_HSE
PLLMThis parameter can be one of the following values:
  • LL_RCC_PLLM_DIV_1
  • LL_RCC_PLLM_DIV_2
  • LL_RCC_PLLM_DIV_3
  • LL_RCC_PLLM_DIV_4
  • LL_RCC_PLLM_DIV_5
  • LL_RCC_PLLM_DIV_6
  • LL_RCC_PLLM_DIV_7
  • LL_RCC_PLLM_DIV_8
PLLNBetween 8 and 86
PLLPThis parameter can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_17
Return values
None

Definition at line 4877 of file stm32l4xx_ll_rcc.h.

4878 {
4879  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4880  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
4881  PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP);
4882 }
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)

◆ LL_RCC_PLLSAI2_Disable()

__STATIC_INLINE void LL_RCC_PLLSAI2_Disable ( void  )

Disable PLLSAI2 CR PLLSAI2ON LL_RCC_PLLSAI2_Disable.

Return values
None

Definition at line 4796 of file stm32l4xx_ll_rcc.h.

4797 {
4798  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4799 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_RCC_PLLSAI2_DisableDomain_ADC()

__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC ( void  )

Disable PLLSAI2 output mapped on ADC domain clock.

Note
In order to save power, when of the PLLSAI2 is not used, Main PLLSAI2 should be 0 PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
Return values
None

Definition at line 5355 of file stm32l4xx_ll_rcc.h.

5356 {
5357  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5358 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_RCC_PLLSAI2_DisableDomain_DSI()

__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI ( void  )

Disable PLLSAI2 output mapped on DSI domain clock.

Note
In order to save power, when of the PLLSAI2 is not used, Main PLLSAI2 should be 0 PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
Return values
None

Definition at line 5309 of file stm32l4xx_ll_rcc.h.

5310 {
5311  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5312 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_RCC_PLLSAI2_DisableDomain_LTDC()

__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC ( void  )

Disable PLLSAI2 output mapped on LTDC domain clock.

Note
In order to save power, when of the PLLSAI2 is not used, Main PLLSAI2 should be 0 PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
Return values
None

Definition at line 5333 of file stm32l4xx_ll_rcc.h.

5334 {
5335  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5336 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_RCC_PLLSAI2_DisableDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI ( void  )

Disable PLLSAI2 output mapped on SAI domain clock.

Note
In order to save power, when of the PLLSAI2 is not used, should be 0 PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
Return values
None

Definition at line 5286 of file stm32l4xx_ll_rcc.h.

5287 {
5288  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5289 }
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)

◆ LL_RCC_PLLSAI2_Enable()

__STATIC_INLINE void LL_RCC_PLLSAI2_Enable ( void  )

Enable PLLSAI2 CR PLLSAI2ON LL_RCC_PLLSAI2_Enable.

Return values
None

Definition at line 4786 of file stm32l4xx_ll_rcc.h.

4787 {
4788  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4789 }

◆ LL_RCC_PLLSAI2_EnableDomain_ADC()

__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC ( void  )

Enable PLLSAI2 output mapped on ADC domain clock PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC.

Return values
None

Definition at line 5343 of file stm32l4xx_ll_rcc.h.

5344 {
5345  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5346 }

◆ LL_RCC_PLLSAI2_EnableDomain_DSI()

__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI ( void  )

Enable PLLSAI2 output mapped on DSI domain clock PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI.

Return values
None

Definition at line 5297 of file stm32l4xx_ll_rcc.h.

5298 {
5299  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5300 }

◆ LL_RCC_PLLSAI2_EnableDomain_LTDC()

__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC ( void  )

Enable PLLSAI2 output mapped on LTDC domain clock PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC.

Return values
None

Definition at line 5321 of file stm32l4xx_ll_rcc.h.

5322 {
5323  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5324 }

◆ LL_RCC_PLLSAI2_EnableDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI ( void  )

Enable PLLSAI2 output mapped on SAI domain clock PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI.

Return values
None

Definition at line 5274 of file stm32l4xx_ll_rcc.h.

5275 {
5276  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5277 }

◆ LL_RCC_PLLSAI2_GetDivider()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider ( void  )

Get Division factor for the PLLSAI2 PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider.

Return values
Returnedvalue can be one of the following values:
  • LL_RCC_PLLSAI2M_DIV_1
  • LL_RCC_PLLSAI2M_DIV_2
  • LL_RCC_PLLSAI2M_DIV_3
  • LL_RCC_PLLSAI2M_DIV_4
  • LL_RCC_PLLSAI2M_DIV_5
  • LL_RCC_PLLSAI2M_DIV_6
  • LL_RCC_PLLSAI2M_DIV_7
  • LL_RCC_PLLSAI2M_DIV_8
  • LL_RCC_PLLSAI2M_DIV_9
  • LL_RCC_PLLSAI2M_DIV_10
  • LL_RCC_PLLSAI2M_DIV_11
  • LL_RCC_PLLSAI2M_DIV_12
  • LL_RCC_PLLSAI2M_DIV_13
  • LL_RCC_PLLSAI2M_DIV_14
  • LL_RCC_PLLSAI2M_DIV_15
  • LL_RCC_PLLSAI2M_DIV_16

Definition at line 5246 of file stm32l4xx_ll_rcc.h.

5247 {
5248  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
5249 }

◆ LL_RCC_PLLSAI2_GetDIVR()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR ( void  )

Get PLLSAI2 division factor for PLLSAI2DIVR.

Note
Used for LTDC domain clock CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
Return values
Returnedvalue can be one of the following values:
  • LL_RCC_PLLSAI2DIVR_DIV_2
  • LL_RCC_PLLSAI2DIVR_DIV_4
  • LL_RCC_PLLSAI2DIVR_DIV_8
  • LL_RCC_PLLSAI2DIVR_DIV_16

Definition at line 5263 of file stm32l4xx_ll_rcc.h.

5264 {
5265  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
5266 }

◆ LL_RCC_PLLSAI2_GetN()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN ( void  )

Get SAI2PLL multiplication factor for VCO PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN.

Return values
Between8 and 86

Definition at line 5131 of file stm32l4xx_ll_rcc.h.

5132 {
5133  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
5134 }

◆ LL_RCC_PLLSAI2_GetP()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP ( void  )

Get SAI2PLL division factor for PLLSAI2P.

Note
Used for PLLSAI2CLK (SAI1 or SAI2 clock). PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
Return values
Returnedvalue can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_2
  • LL_RCC_PLLSAI2P_DIV_3
  • LL_RCC_PLLSAI2P_DIV_4
  • LL_RCC_PLLSAI2P_DIV_5
  • LL_RCC_PLLSAI2P_DIV_6
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_8
  • LL_RCC_PLLSAI2P_DIV_9
  • LL_RCC_PLLSAI2P_DIV_10
  • LL_RCC_PLLSAI2P_DIV_11
  • LL_RCC_PLLSAI2P_DIV_12
  • LL_RCC_PLLSAI2P_DIV_13
  • LL_RCC_PLLSAI2P_DIV_14
  • LL_RCC_PLLSAI2P_DIV_15
  • LL_RCC_PLLSAI2P_DIV_16
  • LL_RCC_PLLSAI2P_DIV_17
  • LL_RCC_PLLSAI2P_DIV_18
  • LL_RCC_PLLSAI2P_DIV_19
  • LL_RCC_PLLSAI2P_DIV_20
  • LL_RCC_PLLSAI2P_DIV_21
  • LL_RCC_PLLSAI2P_DIV_22
  • LL_RCC_PLLSAI2P_DIV_23
  • LL_RCC_PLLSAI2P_DIV_24
  • LL_RCC_PLLSAI2P_DIV_25
  • LL_RCC_PLLSAI2P_DIV_26
  • LL_RCC_PLLSAI2P_DIV_27
  • LL_RCC_PLLSAI2P_DIV_28
  • LL_RCC_PLLSAI2P_DIV_29
  • LL_RCC_PLLSAI2P_DIV_30
  • LL_RCC_PLLSAI2P_DIV_31
Note
Used for PLLSAI2CLK (SAI1 or SAI2 clock). PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
Return values
Returnedvalue can be one of the following values:
  • LL_RCC_PLLSAI2P_DIV_7
  • LL_RCC_PLLSAI2P_DIV_17

Definition at line 5173 of file stm32l4xx_ll_rcc.h.

5174 {
5175  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
5176 }

◆ LL_RCC_PLLSAI2_GetQ()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ ( void  )

Get division factor for PLLSAI2Q.

Note
Used for PLLDSICLK (DSI clock) PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
Return values
Returnedvalue can be one of the following values:
  • LL_RCC_PLLSAI2Q_DIV_2
  • LL_RCC_PLLSAI2Q_DIV_4
  • LL_RCC_PLLSAI2Q_DIV_6
  • LL_RCC_PLLSAI2Q_DIV_8

Definition at line 5203 of file stm32l4xx_ll_rcc.h.

5204 {
5205  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
5206 }

◆ LL_RCC_PLLSAI2_GetR()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR ( void  )

Get SAI2PLL division factor for PLLSAI2R.

Note
Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
Return values
Returnedvalue can be one of the following values:
  • LL_RCC_PLLSAI2R_DIV_2
  • LL_RCC_PLLSAI2R_DIV_4
  • LL_RCC_PLLSAI2R_DIV_6
  • LL_RCC_PLLSAI2R_DIV_8

Definition at line 5219 of file stm32l4xx_ll_rcc.h.

5220 {
5221  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
5222 }

◆ LL_RCC_PLLSAI2_IsReady()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady ( void  )

Check if PLLSAI2 Ready CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady.

Return values
Stateof bit (1 or 0).

Definition at line 4806 of file stm32l4xx_ll_rcc.h.

4807 {
4808  return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL);
4809 }