STM32L4xx_HAL_Driver  1.14.0
SPI Private Functions

Private functions. More...

Functions

static void SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
 DMA SPI transmit process complete callback. More...
 
static void SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
 DMA SPI receive process complete callback. More...
 
static void SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
 DMA SPI transmit receive process complete callback. More...
 
static void SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
 DMA SPI half transmit process complete callback. More...
 
static void SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
 DMA SPI half receive process complete callback. More...
 
static void SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
 DMA SPI half transmit receive process complete callback. More...
 
static void SPI_DMAError (DMA_HandleTypeDef *hdma)
 DMA SPI communication error callback. More...
 
static void SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
 DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence). More...
 
static void SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
 DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request). More...
 
static void SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
 DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request). More...
 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
 Handle SPI Communication Timeout. More...
 
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
 Handle SPI FIFO Communication Timeout. More...
 
static void SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
 Handle the data 8-bit transmit in Interrupt mode. More...
 
static void SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
 Handle the data 16-bit transmit in Interrupt mode. More...
 
static void SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
 Manage the receive 8-bit in Interrupt context. More...
 
static void SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
 Manage the 16-bit receive in Interrupt context. More...
 
static void SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
 Rx 8-bit handler for Transmit and Receive in Interrupt mode. More...
 
static void SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
 Tx 8-bit handler for Transmit and Receive in Interrupt mode. More...
 
static void SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
 Tx 16-bit handler for Transmit and Receive in Interrupt mode. More...
 
static void SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
 Rx 16-bit handler for Transmit and Receive in Interrupt mode. More...
 
static void SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
 Manage the CRC 8-bit receive in Interrupt context. More...
 
static void SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
 Manage the CRC 16-bit receive in Interrupt context. More...
 
static void SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
 Rx 8-bit handler for Transmit and Receive in Interrupt mode. More...
 
static void SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
 Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. More...
 
static void SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
 Handle abort a Rx transaction. More...
 
static void SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
 Handle abort a Tx or Rx/Tx transaction. More...
 
static void SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
 Handle the end of the RXTX transaction. More...
 
static void SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
 Handle the end of the RX transaction. More...
 
static void SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
 Handle the end of the TX transaction. More...
 
static HAL_StatusTypeDef SPI_EndRxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
 Handle the check of the RX transaction complete. More...
 
static HAL_StatusTypeDef SPI_EndRxTxTransaction (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
 Handle the check of the RXTX or TX transaction complete. More...
 

Detailed Description

Private functions.

Function Documentation

◆ SPI_2linesRxISR_16BIT()

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef hspi)
static

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3537 of file stm32l4xx_hal_spi.c.

3538 {
3539  /* Receive data in 16 Bit mode */
3540  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3541  hspi->pRxBuffPtr += sizeof(uint16_t);
3542  hspi->RxXferCount--;
3543 
3544  if (hspi->RxXferCount == 0U)
3545  {
3546 #if (USE_SPI_CRC != 0U)
3547  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3548  {
3550  return;
3551  }
3552 #endif /* USE_SPI_CRC */
3553 
3554  /* Disable RXNE interrupt */
3555  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3556 
3557  if (hspi->TxXferCount == 0U)
3558  {
3559  SPI_CloseRxTx_ISR(hspi);
3560  }
3561  }
3562 }
SPI_InitTypeDef Init
__IO uint16_t RxXferCount
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
__IO uint16_t TxXferCount
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_2linesRxISR_16BITCRC()

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef hspi)
static

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3571 of file stm32l4xx_hal_spi.c.

3572 {
3573  /* Read 16bit CRC to flush Data Regsiter */
3574  READ_REG(hspi->Instance->DR);
3575 
3576  /* Disable RXNE interrupt */
3577  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3578 
3579  SPI_CloseRxTx_ISR(hspi);
3580 }
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.

◆ SPI_2linesRxISR_8BIT()

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef hspi)
static

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3412 of file stm32l4xx_hal_spi.c.

3413 {
3414  /* Receive data in packing mode */
3415  if (hspi->RxXferCount > 1U)
3416  {
3417  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3418  hspi->pRxBuffPtr += sizeof(uint16_t);
3419  hspi->RxXferCount -= 2U;
3420  if (hspi->RxXferCount == 1U)
3421  {
3422  /* Set RX Fifo threshold according the reception data length: 8bit */
3423  SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3424  }
3425  }
3426  /* Receive data in 8 Bit mode */
3427  else
3428  {
3429  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3430  hspi->pRxBuffPtr++;
3431  hspi->RxXferCount--;
3432  }
3433 
3434  /* Check end of the reception */
3435  if (hspi->RxXferCount == 0U)
3436  {
3437 #if (USE_SPI_CRC != 0U)
3438  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3439  {
3440  SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3442  return;
3443  }
3444 #endif /* USE_SPI_CRC */
3445 
3446  /* Disable RXNE and ERR interrupt */
3447  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3448 
3449  if (hspi->TxXferCount == 0U)
3450  {
3451  SPI_CloseRxTx_ISR(hspi);
3452  }
3453  }
3454 }
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
SPI_InitTypeDef Init
__IO uint16_t RxXferCount
__IO uint16_t TxXferCount
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_2linesRxISR_8BITCRC()

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef hspi)
static

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3463 of file stm32l4xx_hal_spi.c.

3464 {
3465  /* Read 8bit CRC to flush Data Regsiter */
3466  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3467 
3468  hspi->CRCSize--;
3469 
3470  /* Check end of the reception */
3471  if (hspi->CRCSize == 0U)
3472  {
3473  /* Disable RXNE and ERR interrupt */
3474  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3475 
3476  if (hspi->TxXferCount == 0U)
3477  {
3478  SPI_CloseRxTx_ISR(hspi);
3479  }
3480  }
3481 }
__IO uint16_t TxXferCount
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.

◆ SPI_2linesTxISR_16BIT()

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef hspi)
static

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3589 of file stm32l4xx_hal_spi.c.

3590 {
3591  /* Transmit data in 16 Bit mode */
3592  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3593  hspi->pTxBuffPtr += sizeof(uint16_t);
3594  hspi->TxXferCount--;
3595 
3596  /* Enable CRC Transmission */
3597  if (hspi->TxXferCount == 0U)
3598  {
3599 #if (USE_SPI_CRC != 0U)
3600  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3601  {
3602  /* Set CRC Next Bit to send CRC */
3603  SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3604  /* Disable TXE interrupt */
3605  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3606  return;
3607  }
3608 #endif /* USE_SPI_CRC */
3609 
3610  /* Disable TXE interrupt */
3611  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3612 
3613  if (hspi->RxXferCount == 0U)
3614  {
3615  SPI_CloseRxTx_ISR(hspi);
3616  }
3617  }
3618 }
SPI_InitTypeDef Init
__IO uint16_t RxXferCount
__IO uint16_t TxXferCount
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.

◆ SPI_2linesTxISR_8BIT()

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef hspi)
static

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3490 of file stm32l4xx_hal_spi.c.

3491 {
3492  /* Transmit data in packing Bit mode */
3493  if (hspi->TxXferCount >= 2U)
3494  {
3495  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3496  hspi->pTxBuffPtr += sizeof(uint16_t);
3497  hspi->TxXferCount -= 2U;
3498  }
3499  /* Transmit data in 8 Bit mode */
3500  else
3501  {
3502  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3503  hspi->pTxBuffPtr++;
3504  hspi->TxXferCount--;
3505  }
3506 
3507  /* Check the end of the transmission */
3508  if (hspi->TxXferCount == 0U)
3509  {
3510 #if (USE_SPI_CRC != 0U)
3511  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3512  {
3513  /* Set CRC Next Bit to send CRC */
3514  SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3515  /* Disable TXE interrupt */
3516  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3517  return;
3518  }
3519 #endif /* USE_SPI_CRC */
3520 
3521  /* Disable TXE interrupt */
3522  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3523 
3524  if (hspi->RxXferCount == 0U)
3525  {
3526  SPI_CloseRxTx_ISR(hspi);
3527  }
3528  }
3529 }
SPI_InitTypeDef Init
__IO uint16_t RxXferCount
__IO uint16_t TxXferCount
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.

◆ SPI_AbortRx_ISR()

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef hspi)
static

Handle abort a Rx transaction.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 4146 of file stm32l4xx_hal_spi.c.

4147 {
4148  __IO uint32_t count;
4149 
4150  /* Disable SPI Peripheral */
4151  __HAL_SPI_DISABLE(hspi);
4152 
4153  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4154 
4155  /* Disable RXNEIE interrupt */
4156  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4157 
4158  /* Check RXNEIE is disabled */
4159  do
4160  {
4161  if (count == 0U)
4162  {
4163  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4164  break;
4165  }
4166  count--;
4167  }
4168  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4169 
4170  /* Control the BSY flag */
4171  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4172  {
4173  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4174  }
4175 
4176  /* Empty the FRLVL fifo */
4177  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4178  {
4179  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4180  }
4181 
4182  hspi->State = HAL_SPI_STATE_ABORT;
4183 }
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
return HAL_OK
__IO HAL_SPI_StateTypeDef State

◆ SPI_AbortTx_ISR()

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef hspi)
static

Handle abort a Tx or Rx/Tx transaction.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 4191 of file stm32l4xx_hal_spi.c.

4192 {
4193  __IO uint32_t count;
4194 
4195  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4196 
4197  /* Disable TXEIE interrupt */
4198  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4199 
4200  /* Check TXEIE is disabled */
4201  do
4202  {
4203  if (count == 0U)
4204  {
4205  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4206  break;
4207  }
4208  count--;
4209  }
4210  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4211 
4212  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4213  {
4214  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4215  }
4216 
4217  /* Disable SPI Peripheral */
4218  __HAL_SPI_DISABLE(hspi);
4219 
4220  /* Empty the FRLVL fifo */
4221  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4222  {
4223  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4224  }
4225 
4226  /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4227  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4228  {
4229  /* Disable RXNEIE interrupt */
4230  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4231 
4232  /* Check RXNEIE is disabled */
4233  do
4234  {
4235  if (count == 0U)
4236  {
4237  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4238  break;
4239  }
4240  count--;
4241  }
4242  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4243 
4244  /* Control the BSY flag */
4245  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4246  {
4247  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4248  }
4249 
4250  /* Empty the FRLVL fifo */
4251  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4252  {
4253  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4254  }
4255  }
4256  hspi->State = HAL_SPI_STATE_ABORT;
4257 }
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
return HAL_OK
__IO HAL_SPI_StateTypeDef State

◆ SPI_CloseRx_ISR()

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef hspi)
static

Handle the end of the RX transaction.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 4040 of file stm32l4xx_hal_spi.c.

4041 {
4042  /* Disable RXNE and ERR interrupt */
4043  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4044 
4045  /* Check the end of the transaction */
4046  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4047  {
4048  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4049  }
4050  hspi->State = HAL_SPI_STATE_READY;
4051 
4052 #if (USE_SPI_CRC != 0U)
4053  /* Check if CRC error occurred */
4054  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4055  {
4056  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4057  __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4058  /* Call user error callback */
4059 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4060  hspi->ErrorCallback(hspi);
4061 #else
4062  HAL_SPI_ErrorCallback(hspi);
4063 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4064  }
4065  else
4066  {
4067 #endif /* USE_SPI_CRC */
4068  if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4069  {
4070  /* Call user Rx complete callback */
4071 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4072  hspi->RxCpltCallback(hspi);
4073 #else
4074  HAL_SPI_RxCpltCallback(hspi);
4075 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4076  }
4077  else
4078  {
4079  /* Call user error callback */
4080 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4081  hspi->ErrorCallback(hspi);
4082 #else
4083  HAL_SPI_ErrorCallback(hspi);
4084 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4085  }
4086 #if (USE_SPI_CRC != 0U)
4087  }
4088 #endif /* USE_SPI_CRC */
4089 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
return HAL_OK
__IO HAL_SPI_StateTypeDef State
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
void(* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_CloseRxTx_ISR()

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef hspi)
static

Handle the end of the RXTX transaction.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3963 of file stm32l4xx_hal_spi.c.

3964 {
3965  uint32_t tickstart;
3966 
3967  /* Init tickstart for timeout managment*/
3968  tickstart = HAL_GetTick();
3969 
3970  /* Disable ERR interrupt */
3971  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3972 
3973  /* Check the end of the transaction */
3974  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3975  {
3976  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3977  }
3978 
3979 #if (USE_SPI_CRC != 0U)
3980  /* Check if CRC error occurred */
3981  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3982  {
3983  hspi->State = HAL_SPI_STATE_READY;
3984  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3985  __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3986  /* Call user error callback */
3987 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3988  hspi->ErrorCallback(hspi);
3989 #else
3990  HAL_SPI_ErrorCallback(hspi);
3991 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3992  }
3993  else
3994  {
3995 #endif /* USE_SPI_CRC */
3996  if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3997  {
3998  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
3999  {
4000  hspi->State = HAL_SPI_STATE_READY;
4001  /* Call user Rx complete callback */
4002 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4003  hspi->RxCpltCallback(hspi);
4004 #else
4005  HAL_SPI_RxCpltCallback(hspi);
4006 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4007  }
4008  else
4009  {
4010  hspi->State = HAL_SPI_STATE_READY;
4011  /* Call user TxRx complete callback */
4012 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4013  hspi->TxRxCpltCallback(hspi);
4014 #else
4016 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4017  }
4018  }
4019  else
4020  {
4021  hspi->State = HAL_SPI_STATE_READY;
4022  /* Call user error callback */
4023 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4024  hspi->ErrorCallback(hspi);
4025 #else
4026  HAL_SPI_ErrorCallback(hspi);
4027 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4028  }
4029 #if (USE_SPI_CRC != 0U)
4030  }
4031 #endif /* USE_SPI_CRC */
4032 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
void(* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi)
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
return HAL_OK
__IO HAL_SPI_StateTypeDef State
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
void(* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_CloseTx_ISR()

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef hspi)
static

Handle the end of the TX transaction.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 4097 of file stm32l4xx_hal_spi.c.

4098 {
4099  uint32_t tickstart;
4100 
4101  /* Init tickstart for timeout management*/
4102  tickstart = HAL_GetTick();
4103 
4104  /* Disable TXE and ERR interrupt */
4105  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4106 
4107  /* Check the end of the transaction */
4108  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4109  {
4110  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4111  }
4112 
4113  /* Clear overrun flag in 2 Lines communication mode because received is not read */
4114  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4115  {
4116  __HAL_SPI_CLEAR_OVRFLAG(hspi);
4117  }
4118 
4119  hspi->State = HAL_SPI_STATE_READY;
4120  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4121  {
4122  /* Call user error callback */
4123 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4124  hspi->ErrorCallback(hspi);
4125 #else
4126  HAL_SPI_ErrorCallback(hspi);
4127 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4128  }
4129  else
4130  {
4131  /* Call user Rx complete callback */
4132 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4133  hspi->TxCpltCallback(hspi);
4134 #else
4135  HAL_SPI_TxCpltCallback(hspi);
4136 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4137  }
4138 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
SPI_InitTypeDef Init
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
return HAL_OK
__IO HAL_SPI_StateTypeDef State
void(* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_DMAAbortOnError()

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef hdma)
static

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters
hdmaDMA handle.
Return values
None

Definition at line 3259 of file stm32l4xx_hal_spi.c.

3260 {
3261  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3262  hspi->RxXferCount = 0U;
3263  hspi->TxXferCount = 0U;
3264 
3265  /* Call user error callback */
3266 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3267  hspi->ErrorCallback(hspi);
3268 #else
3269  HAL_SPI_ErrorCallback(hspi);
3270 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3271 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
DMA handle Structure definition.
__IO uint16_t RxXferCount
SPI handle Structure definition.
__IO uint16_t TxXferCount

◆ SPI_DMAError()

static void SPI_DMAError ( DMA_HandleTypeDef hdma)
static

DMA SPI communication error callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 3236 of file stm32l4xx_hal_spi.c.

3237 {
3238  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3239 
3240  /* Stop the disable DMA transfer on SPI side */
3241  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3242 
3243  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3244  hspi->State = HAL_SPI_STATE_READY;
3245  /* Call user error callback */
3246 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3247  hspi->ErrorCallback(hspi);
3248 #else
3249  HAL_SPI_ErrorCallback(hspi);
3250 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3251 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
DMA handle Structure definition.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
__IO HAL_SPI_StateTypeDef State
SPI handle Structure definition.

◆ SPI_DMAHalfReceiveCplt()

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef hdma)
static

DMA SPI half receive process complete callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 3200 of file stm32l4xx_hal_spi.c.

3201 {
3202  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3203 
3204  /* Call user Rx half complete callback */
3205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3206  hspi->RxHalfCpltCallback(hspi);
3207 #else
3209 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3210 }
DMA handle Structure definition.
void(* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)
SPI handle Structure definition.
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.

◆ SPI_DMAHalfTransmitCplt()

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef hdma)
static

DMA SPI half transmit process complete callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 3182 of file stm32l4xx_hal_spi.c.

3183 {
3184  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3185 
3186  /* Call user Tx half complete callback */
3187 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3188  hspi->TxHalfCpltCallback(hspi);
3189 #else
3191 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3192 }
DMA handle Structure definition.
SPI handle Structure definition.
void(* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.

◆ SPI_DMAHalfTransmitReceiveCplt()

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef hdma)
static

DMA SPI half transmit receive process complete callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 3218 of file stm32l4xx_hal_spi.c.

3219 {
3220  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3221 
3222  /* Call user TxRx half complete callback */
3223 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3224  hspi->TxRxHalfCpltCallback(hspi);
3225 #else
3227 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3228 }
DMA handle Structure definition.
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
void(* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi)
SPI handle Structure definition.

◆ SPI_DMAReceiveCplt()

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef hdma)
static

DMA SPI receive process complete callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 2998 of file stm32l4xx_hal_spi.c.

2999 {
3000  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3001  uint32_t tickstart;
3002 
3003  /* Init tickstart for timeout management*/
3004  tickstart = HAL_GetTick();
3005 
3006  /* DMA Normal Mode */
3007  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3008  {
3009  /* Disable ERR interrupt */
3010  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3011 
3012 #if (USE_SPI_CRC != 0U)
3013  /* CRC handling */
3014  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3015  {
3016  /* Wait until RXNE flag */
3017  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3018  {
3019  /* Error on the CRC reception */
3020  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3021  }
3022  /* Read CRC */
3023  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3024  {
3025  /* Read 16bit CRC */
3026  READ_REG(hspi->Instance->DR);
3027  }
3028  else
3029  {
3030  /* Read 8bit CRC */
3031  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3032 
3033  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3034  {
3035  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3036  {
3037  /* Error on the CRC reception */
3038  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3039  }
3040  /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3041  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3042  }
3043  }
3044  }
3045 #endif /* USE_SPI_CRC */
3046 
3047  /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3048  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3049 
3050  /* Check the end of the transaction */
3051  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3052  {
3053  hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3054  }
3055 
3056  hspi->RxXferCount = 0U;
3057  hspi->State = HAL_SPI_STATE_READY;
3058 
3059 #if (USE_SPI_CRC != 0U)
3060  /* Check if CRC error occurred */
3061  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3062  {
3063  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3064  __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3065  }
3066 #endif /* USE_SPI_CRC */
3067 
3068  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3069  {
3070  /* Call user error callback */
3071 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3072  hspi->ErrorCallback(hspi);
3073 #else
3074  HAL_SPI_ErrorCallback(hspi);
3075 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3076  return;
3077  }
3078  }
3079  /* Call user Rx complete callback */
3080 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3081  hspi->RxCpltCallback(hspi);
3082 #else
3083  HAL_SPI_RxCpltCallback(hspi);
3084 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3085 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
DMA handle Structure definition.
SPI_InitTypeDef Init
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
DMA_Channel_TypeDef * Instance
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
return HAL_OK
__IO uint16_t RxXferCount
__IO HAL_SPI_StateTypeDef State
SPI handle Structure definition.
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RX transaction complete.
void(* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_DMARxAbortCallback()

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef hdma)
static

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters
hdmaDMA handle.
Return values
None

Definition at line 3347 of file stm32l4xx_hal_spi.c.

3348 {
3349  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3350 
3351  /* Disable SPI Peripheral */
3352  __HAL_SPI_DISABLE(hspi);
3353 
3354  hspi->hdmarx->XferAbortCallback = NULL;
3355 
3356  /* Disable Rx DMA Request */
3357  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3358 
3359  /* Control the BSY flag */
3360  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3361  {
3362  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3363  }
3364 
3365  /* Empty the FRLVL fifo */
3366  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3367  {
3368  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3369  }
3370 
3371  /* Check if an Abort process is still ongoing */
3372  if (hspi->hdmatx != NULL)
3373  {
3374  if (hspi->hdmatx->XferAbortCallback != NULL)
3375  {
3376  return;
3377  }
3378  }
3379 
3380  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3381  hspi->RxXferCount = 0U;
3382  hspi->TxXferCount = 0U;
3383 
3384  /* Check no error during Abort procedure */
3385  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3386  {
3387  /* Reset errorCode */
3388  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3389  }
3390 
3391  /* Clear the Error flags in the SR register */
3392  __HAL_SPI_CLEAR_OVRFLAG(hspi);
3393  __HAL_SPI_CLEAR_FREFLAG(hspi);
3394 
3395  /* Restore hspi->State to Ready */
3396  hspi->State = HAL_SPI_STATE_READY;
3397 
3398  /* Call user Abort complete callback */
3399 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3400  hspi->AbortCpltCallback(hspi);
3401 #else
3403 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3404 }
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
DMA handle Structure definition.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
DMA_HandleTypeDef * hdmatx
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
void(* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi)
return HAL_OK
DMA_HandleTypeDef * hdmarx
__IO uint16_t RxXferCount
__IO HAL_SPI_StateTypeDef State
SPI handle Structure definition.
__IO uint16_t TxXferCount

◆ SPI_DMATransmitCplt()

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef hdma)
static

DMA SPI transmit process complete callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 2941 of file stm32l4xx_hal_spi.c.

2942 {
2943  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2944  uint32_t tickstart;
2945 
2946  /* Init tickstart for timeout management*/
2947  tickstart = HAL_GetTick();
2948 
2949  /* DMA Normal Mode */
2950  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2951  {
2952  /* Disable ERR interrupt */
2953  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2954 
2955  /* Disable Tx DMA Request */
2956  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2957 
2958  /* Check the end of the transaction */
2959  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2960  {
2961  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2962  }
2963 
2964  /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2965  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2966  {
2967  __HAL_SPI_CLEAR_OVRFLAG(hspi);
2968  }
2969 
2970  hspi->TxXferCount = 0U;
2971  hspi->State = HAL_SPI_STATE_READY;
2972 
2973  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2974  {
2975  /* Call user error callback */
2976 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2977  hspi->ErrorCallback(hspi);
2978 #else
2979  HAL_SPI_ErrorCallback(hspi);
2980 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2981  return;
2982  }
2983  }
2984  /* Call user Tx complete callback */
2985 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2986  hspi->TxCpltCallback(hspi);
2987 #else
2988  HAL_SPI_TxCpltCallback(hspi);
2989 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2990 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
DMA handle Structure definition.
SPI_InitTypeDef Init
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
DMA_Channel_TypeDef * Instance
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
return HAL_OK
__IO HAL_SPI_StateTypeDef State
SPI handle Structure definition.
__IO uint16_t TxXferCount
void(* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_DMATransmitReceiveCplt()

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef hdma)
static

DMA SPI transmit receive process complete callback.

Parameters
hdmapointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values
None

Definition at line 3093 of file stm32l4xx_hal_spi.c.

3094 {
3095  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3096  uint32_t tickstart;
3097 
3098  /* Init tickstart for timeout management*/
3099  tickstart = HAL_GetTick();
3100 
3101  /* DMA Normal Mode */
3102  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3103  {
3104  /* Disable ERR interrupt */
3105  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3106 
3107 #if (USE_SPI_CRC != 0U)
3108  /* CRC handling */
3109  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3110  {
3111  if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3112  {
3113  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3114  tickstart) != HAL_OK)
3115  {
3116  /* Error on the CRC reception */
3117  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3118  }
3119  /* Read CRC to Flush DR and RXNE flag */
3120  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3121  }
3122  else
3123  {
3124  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3125  {
3126  /* Error on the CRC reception */
3127  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3128  }
3129  /* Read CRC to Flush DR and RXNE flag */
3130  READ_REG(hspi->Instance->DR);
3131  }
3132  }
3133 #endif /* USE_SPI_CRC */
3134 
3135  /* Check the end of the transaction */
3136  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3137  {
3138  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3139  }
3140 
3141  /* Disable Rx/Tx DMA Request */
3142  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3143 
3144  hspi->TxXferCount = 0U;
3145  hspi->RxXferCount = 0U;
3146  hspi->State = HAL_SPI_STATE_READY;
3147 
3148 #if (USE_SPI_CRC != 0U)
3149  /* Check if CRC error occurred */
3150  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3151  {
3152  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3153  __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3154  }
3155 #endif /* USE_SPI_CRC */
3156 
3157  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3158  {
3159  /* Call user error callback */
3160 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3161  hspi->ErrorCallback(hspi);
3162 #else
3163  HAL_SPI_ErrorCallback(hspi);
3164 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3165  return;
3166  }
3167  }
3168  /* Call user TxRx complete callback */
3169 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3170  hspi->TxRxCpltCallback(hspi);
3171 #else
3173 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3174 }
void(* ErrorCallback)(struct __SPI_HandleTypeDef *hspi)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
SPI error callback.
DMA handle Structure definition.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
void(* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi)
SPI_InitTypeDef Init
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
DMA_Channel_TypeDef * Instance
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
return HAL_OK
__IO uint16_t RxXferCount
__IO HAL_SPI_StateTypeDef State
SPI handle Structure definition.
__IO uint16_t TxXferCount

◆ SPI_DMATxAbortCallback()

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef hdma)
static

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters
hdmaDMA handle.
Return values
None

Definition at line 3281 of file stm32l4xx_hal_spi.c.

3282 {
3283  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3284 
3285  hspi->hdmatx->XferAbortCallback = NULL;
3286 
3287  /* Disable Tx DMA Request */
3288  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3289 
3290  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3291  {
3292  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3293  }
3294 
3295  /* Disable SPI Peripheral */
3296  __HAL_SPI_DISABLE(hspi);
3297 
3298  /* Empty the FRLVL fifo */
3299  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3300  {
3301  hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3302  }
3303 
3304  /* Check if an Abort process is still ongoing */
3305  if (hspi->hdmarx != NULL)
3306  {
3307  if (hspi->hdmarx->XferAbortCallback != NULL)
3308  {
3309  return;
3310  }
3311  }
3312 
3313  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3314  hspi->RxXferCount = 0U;
3315  hspi->TxXferCount = 0U;
3316 
3317  /* Check no error during Abort procedure */
3318  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3319  {
3320  /* Reset errorCode */
3321  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3322  }
3323 
3324  /* Clear the Error flags in the SR register */
3325  __HAL_SPI_CLEAR_OVRFLAG(hspi);
3326  __HAL_SPI_CLEAR_FREFLAG(hspi);
3327 
3328  /* Restore hspi->State to Ready */
3329  hspi->State = HAL_SPI_STATE_READY;
3330 
3331  /* Call user Abort complete callback */
3332 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3333  hspi->AbortCpltCallback(hspi);
3334 #else
3336 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3337 }
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
DMA handle Structure definition.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
DMA_HandleTypeDef * hdmatx
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle the check of the RXTX or TX transaction complete.
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
void(* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi)
return HAL_OK
DMA_HandleTypeDef * hdmarx
__IO uint16_t RxXferCount
__IO HAL_SPI_StateTypeDef State
SPI handle Structure definition.
__IO uint16_t TxXferCount

◆ SPI_EndRxTransaction()

static HAL_StatusTypeDef SPI_EndRxTransaction ( SPI_HandleTypeDef hspi,
uint32_t  Timeout,
uint32_t  Tickstart 
)
static

Handle the check of the RX transaction complete.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
TimeoutTimeout duration
Tickstarttick start value
Return values
HALstatus

Definition at line 3895 of file stm32l4xx_hal_spi.c.

3896 {
3897  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3898  || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3899  {
3900  /* Disable SPI peripheral */
3901  __HAL_SPI_DISABLE(hspi);
3902  }
3903 
3904  /* Control the BSY flag */
3905  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3906  {
3907  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3908  return HAL_TIMEOUT;
3909  }
3910 
3911  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3912  || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3913  {
3914  /* Empty the FRLVL fifo */
3915  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3916  {
3917  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3918  return HAL_TIMEOUT;
3919  }
3920  }
3921  return HAL_OK;
3922 }
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
SPI_InitTypeDef Init
return HAL_OK

◆ SPI_EndRxTxTransaction()

static HAL_StatusTypeDef SPI_EndRxTxTransaction ( SPI_HandleTypeDef hspi,
uint32_t  Timeout,
uint32_t  Tickstart 
)
static

Handle the check of the RXTX or TX transaction complete.

Parameters
hspiSPI handle
TimeoutTimeout duration
Tickstarttick start value
Return values
HALstatus

Definition at line 3931 of file stm32l4xx_hal_spi.c.

3932 {
3933  /* Control if the TX fifo is empty */
3934  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3935  {
3936  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3937  return HAL_TIMEOUT;
3938  }
3939 
3940  /* Control the BSY flag */
3941  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3942  {
3943  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3944  return HAL_TIMEOUT;
3945  }
3946 
3947  /* Control if the RX fifo is empty */
3948  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3949  {
3950  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3951  return HAL_TIMEOUT;
3952  }
3953 
3954  return HAL_OK;
3955 }
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI FIFO Communication Timeout.
return HAL_OK

◆ SPI_RxISR_16BIT()

static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef hspi)
static

Manage the 16-bit receive in Interrupt context.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3699 of file stm32l4xx_hal_spi.c.

3700 {
3701  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3702  hspi->pRxBuffPtr += sizeof(uint16_t);
3703  hspi->RxXferCount--;
3704 
3705 #if (USE_SPI_CRC != 0U)
3706  /* Enable CRC Transmission */
3707  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3708  {
3709  SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3710  }
3711 #endif /* USE_SPI_CRC */
3712 
3713  if (hspi->RxXferCount == 0U)
3714  {
3715 #if (USE_SPI_CRC != 0U)
3716  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3717  {
3718  hspi->RxISR = SPI_RxISR_16BITCRC;
3719  return;
3720  }
3721 #endif /* USE_SPI_CRC */
3722  SPI_CloseRx_ISR(hspi);
3723  }
3724 }
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
SPI_InitTypeDef Init
__IO uint16_t RxXferCount
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_RxISR_16BITCRC()

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef hspi)
static

Manage the CRC 16-bit receive in Interrupt context.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3681 of file stm32l4xx_hal_spi.c.

3682 {
3683  /* Read 16bit CRC to flush Data Register */
3684  READ_REG(hspi->Instance->DR);
3685 
3686  /* Disable RXNE and ERR interrupt */
3687  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3688 
3689  SPI_CloseRx_ISR(hspi);
3690 }
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.

◆ SPI_RxISR_8BIT()

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef hspi)
static

Manage the receive 8-bit in Interrupt context.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3647 of file stm32l4xx_hal_spi.c.

3648 {
3649  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3650  hspi->pRxBuffPtr++;
3651  hspi->RxXferCount--;
3652 
3653 #if (USE_SPI_CRC != 0U)
3654  /* Enable CRC Transmission */
3655  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3656  {
3657  SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3658  }
3659 #endif /* USE_SPI_CRC */
3660 
3661  if (hspi->RxXferCount == 0U)
3662  {
3663 #if (USE_SPI_CRC != 0U)
3664  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3665  {
3666  hspi->RxISR = SPI_RxISR_8BITCRC;
3667  return;
3668  }
3669 #endif /* USE_SPI_CRC */
3670  SPI_CloseRx_ISR(hspi);
3671  }
3672 }
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
SPI_InitTypeDef Init
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
__IO uint16_t RxXferCount
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)

◆ SPI_RxISR_8BITCRC()

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef hspi)
static

Manage the CRC 8-bit receive in Interrupt context.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3627 of file stm32l4xx_hal_spi.c.

3628 {
3629  /* Read 8bit CRC to flush Data Register */
3630  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3631 
3632  hspi->CRCSize--;
3633 
3634  if (hspi->CRCSize == 0U)
3635  {
3636  SPI_CloseRx_ISR(hspi);
3637  }
3638 }
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.

◆ SPI_TxISR_16BIT()

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef hspi)
static

Handle the data 16-bit transmit in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3757 of file stm32l4xx_hal_spi.c.

3758 {
3759  /* Transmit data in 16 Bit mode */
3760  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3761  hspi->pTxBuffPtr += sizeof(uint16_t);
3762  hspi->TxXferCount--;
3763 
3764  if (hspi->TxXferCount == 0U)
3765  {
3766 #if (USE_SPI_CRC != 0U)
3767  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3768  {
3769  /* Enable CRC Transmission */
3770  SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3771  }
3772 #endif /* USE_SPI_CRC */
3773  SPI_CloseTx_ISR(hspi);
3774  }
3775 }
SPI_InitTypeDef Init
__IO uint16_t TxXferCount
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.

◆ SPI_TxISR_8BIT()

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef hspi)
static

Handle the data 8-bit transmit in Interrupt mode.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values
None

Definition at line 3732 of file stm32l4xx_hal_spi.c.

3733 {
3734  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3735  hspi->pTxBuffPtr++;
3736  hspi->TxXferCount--;
3737 
3738  if (hspi->TxXferCount == 0U)
3739  {
3740 #if (USE_SPI_CRC != 0U)
3741  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3742  {
3743  /* Enable CRC Transmission */
3744  SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3745  }
3746 #endif /* USE_SPI_CRC */
3747  SPI_CloseTx_ISR(hspi);
3748  }
3749 }
SPI_InitTypeDef Init
__IO uint16_t TxXferCount
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.

◆ SPI_WaitFifoStateUntilTimeout()

static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout ( SPI_HandleTypeDef hspi,
uint32_t  Fifo,
uint32_t  State,
uint32_t  Timeout,
uint32_t  Tickstart 
)
static

Handle SPI FIFO Communication Timeout.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
FifoFifo to check
StateFifo state to check
TimeoutTimeout duration
Tickstarttick start value
Return values
HALstatus

Definition at line 3839 of file stm32l4xx_hal_spi.c.

3841 {
3842  while ((hspi->Instance->SR & Fifo) != State)
3843  {
3844  if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3845  {
3846  /* Read 8bit CRC to flush Data Register */
3847  READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3848  }
3849 
3850  if (Timeout != HAL_MAX_DELAY)
3851  {
3852  if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3853  {
3854  /* Disable the SPI and reset the CRC: the CRC value should be cleared
3855  on both master and slave sides in order to resynchronize the master
3856  and slave for their respective CRC calculation */
3857 
3858  /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3859  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3860 
3861  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3862  || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3863  {
3864  /* Disable SPI peripheral */
3865  __HAL_SPI_DISABLE(hspi);
3866  }
3867 
3868  /* Reset CRC Calculation */
3869  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3870  {
3871  SPI_RESET_CRC(hspi);
3872  }
3873 
3874  hspi->State = HAL_SPI_STATE_READY;
3875 
3876  /* Process Unlocked */
3877  __HAL_UNLOCK(hspi);
3878 
3879  return HAL_TIMEOUT;
3880  }
3881  }
3882  }
3883 
3884  return HAL_OK;
3885 }
hrtc State
SPI_InitTypeDef Init
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
__HAL_UNLOCK(hrtc)
return HAL_OK
__IO HAL_SPI_StateTypeDef State

◆ SPI_WaitFlagStateUntilTimeout()

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout ( SPI_HandleTypeDef hspi,
uint32_t  Flag,
FlagStatus  State,
uint32_t  Timeout,
uint32_t  Tickstart 
)
static

Handle SPI Communication Timeout.

Parameters
hspipointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
FlagSPI flag to check
Stateflag state to check
TimeoutTimeout duration
Tickstarttick start value
Return values
HALstatus

Definition at line 3787 of file stm32l4xx_hal_spi.c.

3789 {
3790  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3791  {
3792  if (Timeout != HAL_MAX_DELAY)
3793  {
3794  if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3795  {
3796  /* Disable the SPI and reset the CRC: the CRC value should be cleared
3797  on both master and slave sides in order to resynchronize the master
3798  and slave for their respective CRC calculation */
3799 
3800  /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3801  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3802 
3803  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3804  || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3805  {
3806  /* Disable SPI peripheral */
3807  __HAL_SPI_DISABLE(hspi);
3808  }
3809 
3810  /* Reset CRC Calculation */
3811  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3812  {
3813  SPI_RESET_CRC(hspi);
3814  }
3815 
3816  hspi->State = HAL_SPI_STATE_READY;
3817 
3818  /* Process Unlocked */
3819  __HAL_UNLOCK(hspi);
3820 
3821  return HAL_TIMEOUT;
3822  }
3823  }
3824  }
3825 
3826  return HAL_OK;
3827 }
hrtc State
SPI_InitTypeDef Init
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
__HAL_UNLOCK(hrtc)
return HAL_OK
__IO HAL_SPI_StateTypeDef State