STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_dma.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_HAL_DMA_H
22 #define STM32L4xx_HAL_DMA_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Request;
52  uint32_t Direction;
56  uint32_t PeriphInc;
59  uint32_t MemInc;
62  uint32_t PeriphDataAlignment;
65  uint32_t MemDataAlignment;
68  uint32_t Mode;
73  uint32_t Priority;
75 } DMA_InitTypeDef;
76 
80 typedef enum
81 {
82  HAL_DMA_STATE_RESET = 0x00U,
83  HAL_DMA_STATE_READY = 0x01U,
84  HAL_DMA_STATE_BUSY = 0x02U,
85  HAL_DMA_STATE_TIMEOUT = 0x03U,
86 }HAL_DMA_StateTypeDef;
87 
91 typedef enum
92 {
93  HAL_DMA_FULL_TRANSFER = 0x00U,
94  HAL_DMA_HALF_TRANSFER = 0x01U
95 }HAL_DMA_LevelCompleteTypeDef;
96 
97 
101 typedef enum
102 {
103  HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
104  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
105  HAL_DMA_XFER_ERROR_CB_ID = 0x02U,
106  HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
107  HAL_DMA_XFER_ALL_CB_ID = 0x04U
108 }HAL_DMA_CallbackIDTypeDef;
109 
113 typedef struct __DMA_HandleTypeDef
114 {
115  DMA_Channel_TypeDef *Instance;
117  DMA_InitTypeDef Init;
119  HAL_LockTypeDef Lock;
121  __IO HAL_DMA_StateTypeDef State;
123  void *Parent;
125  void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);
127  void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);
129  void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);
131  void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma);
133  __IO uint32_t ErrorCode;
135  DMA_TypeDef *DmaBaseAddress;
137  uint32_t ChannelIndex;
139 #if defined(DMAMUX1)
140  DMAMUX_Channel_TypeDef *DMAmuxChannel;
142  DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus;
144  uint32_t DMAmuxChannelStatusMask;
146  DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen;
148  DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus;
150  uint32_t DMAmuxRequestGenStatusMask;
152 #endif /* DMAMUX1 */
153 
154 }DMA_HandleTypeDef;
159 /* Exported constants --------------------------------------------------------*/
160 
168 #define HAL_DMA_ERROR_NONE 0x00000000U
169 #define HAL_DMA_ERROR_TE 0x00000001U
170 #define HAL_DMA_ERROR_NO_XFER 0x00000004U
171 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U
172 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
173 #define HAL_DMA_ERROR_SYNC 0x00000200U
174 #define HAL_DMA_ERROR_REQGEN 0x00000400U
183 #if !defined (DMAMUX1)
184 
185 #define DMA_REQUEST_0 0U
186 #define DMA_REQUEST_1 1U
187 #define DMA_REQUEST_2 2U
188 #define DMA_REQUEST_3 3U
189 #define DMA_REQUEST_4 4U
190 #define DMA_REQUEST_5 5U
191 #define DMA_REQUEST_6 6U
192 #define DMA_REQUEST_7 7U
193 
194 #endif
195 
196 #if defined(DMAMUX1)
197 
198 #define DMA_REQUEST_MEM2MEM 0U
200 #define DMA_REQUEST_GENERATOR0 1U
201 #define DMA_REQUEST_GENERATOR1 2U
202 #define DMA_REQUEST_GENERATOR2 3U
203 #define DMA_REQUEST_GENERATOR3 4U
205 #define DMA_REQUEST_ADC1 5U
207 #define DMA_REQUEST_DAC1_CH1 6U
208 #define DMA_REQUEST_DAC1_CH2 7U
210 #define DMA_REQUEST_TIM6_UP 8U
211 #define DMA_REQUEST_TIM7_UP 9U
213 #define DMA_REQUEST_SPI1_RX 10U
214 #define DMA_REQUEST_SPI1_TX 11U
215 #define DMA_REQUEST_SPI2_RX 12U
216 #define DMA_REQUEST_SPI2_TX 13U
217 #define DMA_REQUEST_SPI3_RX 14U
218 #define DMA_REQUEST_SPI3_TX 15U
220 #define DMA_REQUEST_I2C1_RX 16U
221 #define DMA_REQUEST_I2C1_TX 17U
222 #define DMA_REQUEST_I2C2_RX 18U
223 #define DMA_REQUEST_I2C2_TX 19U
224 #define DMA_REQUEST_I2C3_RX 20U
225 #define DMA_REQUEST_I2C3_TX 21U
226 #define DMA_REQUEST_I2C4_RX 22U
227 #define DMA_REQUEST_I2C4_TX 23U
229 #define DMA_REQUEST_USART1_RX 24U
230 #define DMA_REQUEST_USART1_TX 25U
231 #define DMA_REQUEST_USART2_RX 26U
232 #define DMA_REQUEST_USART2_TX 27U
233 #define DMA_REQUEST_USART3_RX 28U
234 #define DMA_REQUEST_USART3_TX 29U
236 #define DMA_REQUEST_UART4_RX 30U
237 #define DMA_REQUEST_UART4_TX 31U
238 #define DMA_REQUEST_UART5_RX 32U
239 #define DMA_REQUEST_UART5_TX 33U
241 #define DMA_REQUEST_LPUART1_RX 34U
242 #define DMA_REQUEST_LPUART1_TX 35U
244 #define DMA_REQUEST_SAI1_A 36U
245 #define DMA_REQUEST_SAI1_B 37U
246 #define DMA_REQUEST_SAI2_A 38U
247 #define DMA_REQUEST_SAI2_B 39U
249 #define DMA_REQUEST_OCTOSPI1 40U
250 #define DMA_REQUEST_OCTOSPI2 41U
252 #define DMA_REQUEST_TIM1_CH1 42U
253 #define DMA_REQUEST_TIM1_CH2 43U
254 #define DMA_REQUEST_TIM1_CH3 44U
255 #define DMA_REQUEST_TIM1_CH4 45U
256 #define DMA_REQUEST_TIM1_UP 46U
257 #define DMA_REQUEST_TIM1_TRIG 47U
258 #define DMA_REQUEST_TIM1_COM 48U
260 #define DMA_REQUEST_TIM8_CH1 49U
261 #define DMA_REQUEST_TIM8_CH2 50U
262 #define DMA_REQUEST_TIM8_CH3 51U
263 #define DMA_REQUEST_TIM8_CH4 52U
264 #define DMA_REQUEST_TIM8_UP 53U
265 #define DMA_REQUEST_TIM8_TRIG 54U
266 #define DMA_REQUEST_TIM8_COM 55U
268 #define DMA_REQUEST_TIM2_CH1 56U
269 #define DMA_REQUEST_TIM2_CH2 57U
270 #define DMA_REQUEST_TIM2_CH3 58U
271 #define DMA_REQUEST_TIM2_CH4 59U
272 #define DMA_REQUEST_TIM2_UP 60U
274 #define DMA_REQUEST_TIM3_CH1 61U
275 #define DMA_REQUEST_TIM3_CH2 62U
276 #define DMA_REQUEST_TIM3_CH3 63U
277 #define DMA_REQUEST_TIM3_CH4 64U
278 #define DMA_REQUEST_TIM3_UP 65U
279 #define DMA_REQUEST_TIM3_TRIG 66U
281 #define DMA_REQUEST_TIM4_CH1 67U
282 #define DMA_REQUEST_TIM4_CH2 68U
283 #define DMA_REQUEST_TIM4_CH3 69U
284 #define DMA_REQUEST_TIM4_CH4 70U
285 #define DMA_REQUEST_TIM4_UP 71U
287 #define DMA_REQUEST_TIM5_CH1 72U
288 #define DMA_REQUEST_TIM5_CH2 73U
289 #define DMA_REQUEST_TIM5_CH3 74U
290 #define DMA_REQUEST_TIM5_CH4 75U
291 #define DMA_REQUEST_TIM5_UP 76U
292 #define DMA_REQUEST_TIM5_TRIG 77U
294 #define DMA_REQUEST_TIM15_CH1 78U
295 #define DMA_REQUEST_TIM15_UP 79U
296 #define DMA_REQUEST_TIM15_TRIG 80U
297 #define DMA_REQUEST_TIM15_COM 81U
299 #define DMA_REQUEST_TIM16_CH1 82U
300 #define DMA_REQUEST_TIM16_UP 83U
301 #define DMA_REQUEST_TIM17_CH1 84U
302 #define DMA_REQUEST_TIM17_UP 85U
304 #define DMA_REQUEST_DFSDM1_FLT0 86U
305 #define DMA_REQUEST_DFSDM1_FLT1 87U
306 #define DMA_REQUEST_DFSDM1_FLT2 88U
307 #define DMA_REQUEST_DFSDM1_FLT3 89U
309 #define DMA_REQUEST_DCMI 90U
311 #define DMA_REQUEST_AES_IN 91U
312 #define DMA_REQUEST_AES_OUT 92U
314 #define DMA_REQUEST_HASH_IN 93U
316 #endif /* DMAMUX1 */
317 
325 #define DMA_PERIPH_TO_MEMORY 0x00000000U
326 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR
327 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
335 #define DMA_PINC_ENABLE DMA_CCR_PINC
336 #define DMA_PINC_DISABLE 0x00000000U
344 #define DMA_MINC_ENABLE DMA_CCR_MINC
345 #define DMA_MINC_DISABLE 0x00000000U
353 #define DMA_PDATAALIGN_BYTE 0x00000000U
354 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
355 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
363 #define DMA_MDATAALIGN_BYTE 0x00000000U
364 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
365 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
373 #define DMA_NORMAL 0x00000000U
374 #define DMA_CIRCULAR DMA_CCR_CIRC
382 #define DMA_PRIORITY_LOW 0x00000000U
383 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
384 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1
385 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL
394 #define DMA_IT_TC DMA_CCR_TCIE
395 #define DMA_IT_HT DMA_CCR_HTIE
396 #define DMA_IT_TE DMA_CCR_TEIE
397 
404 #define DMA_FLAG_GL1 DMA_ISR_GIF1
405 #define DMA_FLAG_TC1 DMA_ISR_TCIF1
406 #define DMA_FLAG_HT1 DMA_ISR_HTIF1
407 #define DMA_FLAG_TE1 DMA_ISR_TEIF1
408 #define DMA_FLAG_GL2 DMA_ISR_GIF2
409 #define DMA_FLAG_TC2 DMA_ISR_TCIF2
410 #define DMA_FLAG_HT2 DMA_ISR_HTIF2
411 #define DMA_FLAG_TE2 DMA_ISR_TEIF2
412 #define DMA_FLAG_GL3 DMA_ISR_GIF3
413 #define DMA_FLAG_TC3 DMA_ISR_TCIF3
414 #define DMA_FLAG_HT3 DMA_ISR_HTIF3
415 #define DMA_FLAG_TE3 DMA_ISR_TEIF3
416 #define DMA_FLAG_GL4 DMA_ISR_GIF4
417 #define DMA_FLAG_TC4 DMA_ISR_TCIF4
418 #define DMA_FLAG_HT4 DMA_ISR_HTIF4
419 #define DMA_FLAG_TE4 DMA_ISR_TEIF4
420 #define DMA_FLAG_GL5 DMA_ISR_GIF5
421 #define DMA_FLAG_TC5 DMA_ISR_TCIF5
422 #define DMA_FLAG_HT5 DMA_ISR_HTIF5
423 #define DMA_FLAG_TE5 DMA_ISR_TEIF5
424 #define DMA_FLAG_GL6 DMA_ISR_GIF6
425 #define DMA_FLAG_TC6 DMA_ISR_TCIF6
426 #define DMA_FLAG_HT6 DMA_ISR_HTIF6
427 #define DMA_FLAG_TE6 DMA_ISR_TEIF6
428 #define DMA_FLAG_GL7 DMA_ISR_GIF7
429 #define DMA_FLAG_TC7 DMA_ISR_TCIF7
430 #define DMA_FLAG_HT7 DMA_ISR_HTIF7
431 #define DMA_FLAG_TE7 DMA_ISR_TEIF7
432 
440 /* Exported macros -----------------------------------------------------------*/
449 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
450 
456 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
457 
463 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
464 
465 
466 /* Interrupt & Flag management */
467 
474 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
475 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
476  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
477  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
478  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
479  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
480  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
481  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
482  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
483  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
484  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
485  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
486  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
487  DMA_FLAG_TC7)
488 
494 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
495 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
496  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
497  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
498  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
499  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
500  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
501  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
502  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
503  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
504  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
505  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
506  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
507  DMA_FLAG_HT7)
508 
514 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
515 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
516  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
517  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
518  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
519  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
520  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
521  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
522  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
523  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
524  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
525  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
526  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
527  DMA_FLAG_TE7)
528 
534 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
535 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
536  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
537  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
538  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
539  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
540  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
541  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
542  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
543  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
544  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
545  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
546  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
547  DMA_ISR_GIF7)
548 
561 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
562  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
563 
576 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
577  (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
578 
589 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
590 
601 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
602 
613 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
614 
620 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
621 
626 #if defined(DMAMUX1)
627 /* Include DMA HAL Extension module */
628 #include "stm32l4xx_hal_dma_ex.h"
629 #endif /* DMAMUX1 */
630 
631 /* Exported functions --------------------------------------------------------*/
632 
640 /* Initialization and de-initialization functions *****************************/
641 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
642 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
650 /* IO operation functions *****************************************************/
651 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
652 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
653 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
654 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
655 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
656 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
657 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
658 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
659 
667 /* Peripheral State and Error functions ***************************************/
668 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
669 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
678 /* Private macros ------------------------------------------------------------*/
683 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
684  ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
685  ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
686 
687 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
688 
689 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
690  ((STATE) == DMA_PINC_DISABLE))
691 
692 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
693  ((STATE) == DMA_MINC_DISABLE))
694 
695 #if !defined (DMAMUX1)
696 
697 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
698  ((REQUEST) == DMA_REQUEST_1) || \
699  ((REQUEST) == DMA_REQUEST_2) || \
700  ((REQUEST) == DMA_REQUEST_3) || \
701  ((REQUEST) == DMA_REQUEST_4) || \
702  ((REQUEST) == DMA_REQUEST_5) || \
703  ((REQUEST) == DMA_REQUEST_6) || \
704  ((REQUEST) == DMA_REQUEST_7))
705 #endif
706 
707 #if defined(DMAMUX1)
708 
709 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)
710 
711 #endif /* DMAMUX1 */
712 
713 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
714  ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
715  ((SIZE) == DMA_PDATAALIGN_WORD))
716 
717 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
718  ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
719  ((SIZE) == DMA_MDATAALIGN_WORD ))
720 
721 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
722  ((MODE) == DMA_CIRCULAR))
723 
724 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
725  ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
726  ((PRIORITY) == DMA_PRIORITY_HIGH) || \
727  ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
728 
733 /* Private functions ---------------------------------------------------------*/
734 
743 #ifdef __cplusplus
744 }
745 #endif
746 
747 #endif /* STM32L4xx_HAL_DMA_H */
748 
749 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__DMA_HandleTypeDef::DMAmuxChannelStatusMask
uint32_t DMAmuxChannelStatusMask
Definition: stm32l4xx_hal_dma.h:144
HAL_DMA_RegisterCallback
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
Definition: stm32l4xx_hal_dma.c:901
HAL_DMA_STATE_READY
Definition: stm32l4xx_hal_dma.h:83
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32l4xx_hal_dma.h:131
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition: stm32l4xx_hal_dma.h:80
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Callback ID structure definition.
Definition: stm32l4xx_hal_dma.h:101
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32l4xx_hal_dma.h:113
__DMA_HandleTypeDef::Parent
void * Parent
Definition: stm32l4xx_hal_dma.h:123
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32l4xx_hal_dma.h:125
HAL_DMA_STATE_BUSY
Definition: stm32l4xx_hal_dma.h:84
HAL_DMA_STATE_TIMEOUT
Definition: stm32l4xx_hal_dma.h:85
__DMA_HandleTypeDef::DMAmuxRequestGenStatus
DMAMUX_RequestGenStatus_TypeDef * DMAmuxRequestGenStatus
Definition: stm32l4xx_hal_dma.h:148
HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32l4xx_hal_dma.h:106
__DMA_HandleTypeDef::DMAmuxRequestGen
DMAMUX_RequestGen_TypeDef * DMAmuxRequestGen
Definition: stm32l4xx_hal_dma.h:146
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition.
Definition: stm32l4xx_hal_dma.h:91
HAL_DMA_FULL_TRANSFER
Definition: stm32l4xx_hal_dma.h:93
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32l4xx_hal_dma.h:133
__DMA_HandleTypeDef::Instance
DMA_Channel_TypeDef * Instance
Definition: stm32l4xx_hal_dma.h:115
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32l4xx_hal_dma.h:129
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
Definition: stm32l4xx_hal_dma.c:608
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32l4xx_hal_dma.h:127
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition: stm32l4xx_hal_dma.h:117
__DMA_HandleTypeDef::DmaBaseAddress
DMA_TypeDef * DmaBaseAddress
Definition: stm32l4xx_hal_dma.h:135
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32l4xx_hal_dma.h:119
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
Definition: stm32l4xx_hal_dma.c:473
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32l4xx_hal_dma.h:104
HAL_DMA_GetState
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
Return the DMA handle state.
Definition: stm32l4xx_hal_dma.c:1030
__DMA_HandleTypeDef::ChannelIndex
uint32_t ChannelIndex
Definition: stm32l4xx_hal_dma.h:137
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition: stm32l4xx_hal_dma.h:121
HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32l4xx_hal_dma.h:105
__DMA_HandleTypeDef::DMAmuxChannel
DMAMUX_Channel_TypeDef * DMAmuxChannel
Definition: stm32l4xx_hal_dma.h:140
__DMA_HandleTypeDef::DMAmuxRequestGenStatusMask
uint32_t DMAmuxRequestGenStatusMask
Definition: stm32l4xx_hal_dma.h:150
HAL_DMA_Abort
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
Definition: stm32l4xx_hal_dma.c:546
HAL_DMA_UnRegisterCallback
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
Definition: stm32l4xx_hal_dma.c:952
HAL_DMA_PollForTransfer
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
Definition: stm32l4xx_hal_dma.c:675
HAL_DMA_XFER_ALL_CB_ID
Definition: stm32l4xx_hal_dma.h:107
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32l4xx_hal_def.h:50
HAL_DMA_Start
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
Definition: stm32l4xx_hal_dma.c:430
HAL_DMA_HALF_TRANSFER
Definition: stm32l4xx_hal_dma.h:94
HAL_DMA_STATE_RESET
Definition: stm32l4xx_hal_dma.h:82
stm32l4xx_hal_dma_ex.h
Header file of DMA HAL extension module.
__DMA_HandleTypeDef::DMAmuxChannelStatus
DMAMUX_ChannelStatus_TypeDef * DMAmuxChannelStatus
Definition: stm32l4xx_hal_dma.h:142
HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32l4xx_hal_dma.h:103
HAL_DMA_Init
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the as...
Definition: stm32l4xx_hal_dma.c:153
HAL_DMA_IRQHandler
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
Handle DMA interrupt request.
Definition: stm32l4xx_hal_dma.c:805
HAL_DMA_DeInit
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
Definition: stm32l4xx_hal_dma.c:294
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
Return the DMA error code.
Definition: stm32l4xx_hal_dma.c:1042