180 #if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) 188 static uint32_t
SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
192 static uint32_t
SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
227 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 230 assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
232 assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
236 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 237 tmpreg |= Init.ClockBypass;
239 tmpreg |= (Init.ClockEdge |\
240 Init.ClockPowerSave |\
242 Init.HardwareFlowControl |\
247 MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
280 return (SDMMCx->FIFO);
292 SDMMCx->FIFO = *pWriteData;
324 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 325 SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
327 SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
337 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 346 SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1;
360 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 361 SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL);
363 SDMMCx->POWER = (uint32_t)0x00000000;
380 return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
405 tmpreg |= (uint32_t)(Command->
CmdIndex |\
411 MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
423 return (uint8_t)(SDMMCx->RESPCMD);
446 tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
448 return (*(__IO uint32_t *) tmp);
483 MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
496 return (SDMMCx->DCOUNT);
506 return (SDMMCx->FIFO);
521 assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
524 MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
559 sdmmc_cmdinit.
Argument = (uint32_t)BlockSize;
560 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
561 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
563 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
567 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
583 sdmmc_cmdinit.
Argument = (uint32_t)ReadAdd;
584 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
585 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
587 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
591 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
607 sdmmc_cmdinit.
Argument = (uint32_t)ReadAdd;
608 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
609 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
611 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
615 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
631 sdmmc_cmdinit.
Argument = (uint32_t)WriteAdd;
632 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
633 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
635 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
639 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
655 sdmmc_cmdinit.
Argument = (uint32_t)WriteAdd;
656 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
657 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
659 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
663 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
679 sdmmc_cmdinit.
Argument = (uint32_t)StartAdd;
680 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
681 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
683 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
687 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
703 sdmmc_cmdinit.
Argument = (uint32_t)EndAdd;
704 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
705 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
707 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
711 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
727 sdmmc_cmdinit.
Argument = (uint32_t)StartAdd;
728 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_ERASE_GRP_START;
729 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
731 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
735 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
751 sdmmc_cmdinit.
Argument = (uint32_t)EndAdd;
752 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_ERASE_GRP_END;
753 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
755 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
759 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
776 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_ERASE;
777 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
779 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
800 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
801 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
803 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
805 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 806 __SDMMC_CMDSTOP_ENABLE(SDMMCx);
807 __SDMMC_CMDTRANS_DISABLE(SDMMCx);
813 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
815 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 816 __SDMMC_CMDSTOP_DISABLE(SDMMCx);
834 sdmmc_cmdinit.
Argument = (uint32_t)Addr;
835 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
836 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
838 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
842 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
858 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
859 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_NO;
861 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
885 sdmmc_cmdinit.
Argument = SDMMC_CHECK_PATTERN;
886 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
887 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
889 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
911 sdmmc_cmdinit.
Argument = (uint32_t)Argument;
912 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_APP_CMD;
913 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
915 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
939 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 942 sdmmc_cmdinit.
Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument;
944 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
945 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
947 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
967 sdmmc_cmdinit.
Argument = (uint32_t)BusWidth;
968 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
969 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
971 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
975 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
992 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
993 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
995 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
999 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
1012 uint32_t errorstate;
1016 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_ALL_SEND_CID;
1017 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_LONG;
1019 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1037 uint32_t errorstate;
1041 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SEND_CSD;
1042 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_LONG;
1044 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1062 uint32_t errorstate;
1066 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SET_REL_ADDR;
1067 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1069 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1087 uint32_t errorstate;
1090 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SEND_STATUS;
1091 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1093 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1097 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
1110 uint32_t errorstate;
1113 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SD_APP_STATUS;
1114 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1116 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1120 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
1135 uint32_t errorstate;
1138 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_SEND_OP_COND;
1139 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1141 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1159 uint32_t errorstate;
1164 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_HS_SWITCH;
1165 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1167 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1176 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1186 uint32_t errorstate;
1188 sdmmc_cmdinit.
Argument = 0x00000000;
1189 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_VOLTAGE_SWITCH;
1190 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1192 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1196 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT);
1210 uint32_t errorstate;
1214 sdmmc_cmdinit.
CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
1215 sdmmc_cmdinit.
Response = SDMMC_RESPONSE_SHORT;
1217 sdmmc_cmdinit.
CPSM = SDMMC_CPSM_ENABLE;
1221 errorstate =
SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
1245 register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
1251 return SDMMC_ERROR_TIMEOUT;
1254 }
while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
1257 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
1259 return SDMMC_ERROR_NONE;
1275 register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
1281 return SDMMC_ERROR_TIMEOUT;
1283 sta_reg = SDMMCx->STA;
1284 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1285 }
while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END)) == 0U) ||
1286 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
1288 }
while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
1289 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
1292 if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
1294 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
1296 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
1298 else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
1300 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
1302 return SDMMC_ERROR_CMD_CRC_FAIL;
1310 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
1315 return SDMMC_ERROR_CMD_CRC_FAIL;
1323 return SDMMC_ERROR_NONE;
1325 else if((
response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
1327 return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
1329 else if((
response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
1331 return SDMMC_ERROR_ADDR_MISALIGNED;
1333 else if((
response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
1335 return SDMMC_ERROR_BLOCK_LEN_ERR;
1337 else if((
response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
1339 return SDMMC_ERROR_ERASE_SEQ_ERR;
1341 else if((
response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
1343 return SDMMC_ERROR_BAD_ERASE_PARAM;
1345 else if((
response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
1347 return SDMMC_ERROR_WRITE_PROT_VIOLATION;
1349 else if((
response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
1351 return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
1353 else if((
response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
1355 return SDMMC_ERROR_COM_CRC_FAILED;
1357 else if((
response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
1359 return SDMMC_ERROR_ILLEGAL_CMD;
1361 else if((
response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
1363 return SDMMC_ERROR_CARD_ECC_FAILED;
1367 return SDMMC_ERROR_CC_ERR;
1369 else if((
response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
1371 return SDMMC_ERROR_STREAM_READ_UNDERRUN;
1373 else if((
response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
1375 return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
1377 else if((
response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
1379 return SDMMC_ERROR_CID_CSD_OVERWRITE;
1381 else if((
response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
1383 return SDMMC_ERROR_WP_ERASE_SKIP;
1385 else if((
response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
1387 return SDMMC_ERROR_CARD_ECC_DISABLED;
1389 else if((
response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
1391 return SDMMC_ERROR_ERASE_RESET;
1393 else if((
response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
1395 return SDMMC_ERROR_AKE_SEQ_ERR;
1399 return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
1413 register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
1419 return SDMMC_ERROR_TIMEOUT;
1421 sta_reg = SDMMCx->STA;
1422 }
while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
1423 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
1425 if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
1427 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
1429 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
1431 else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
1433 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
1435 return SDMMC_ERROR_CMD_CRC_FAIL;
1441 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
1444 return SDMMC_ERROR_NONE;
1457 register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
1463 return SDMMC_ERROR_TIMEOUT;
1465 sta_reg = SDMMCx->STA;
1466 }
while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
1467 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
1469 if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
1471 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
1473 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
1478 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
1481 return SDMMC_ERROR_NONE;
1499 register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
1505 return SDMMC_ERROR_TIMEOUT;
1507 sta_reg = SDMMCx->STA;
1508 }
while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
1509 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
1511 if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
1513 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
1515 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
1517 else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
1519 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
1521 return SDMMC_ERROR_CMD_CRC_FAIL;
1531 return SDMMC_ERROR_CMD_CRC_FAIL;
1535 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
1540 if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
1542 *pRCA = (uint16_t) (response_r1 >> 16);
1544 return SDMMC_ERROR_NONE;
1546 else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
1548 return SDMMC_ERROR_ILLEGAL_CMD;
1550 else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
1552 return SDMMC_ERROR_COM_CRC_FAILED;
1556 return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
1570 register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
1576 return SDMMC_ERROR_TIMEOUT;
1578 sta_reg = SDMMCx->STA;
1579 }
while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
1580 ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
1582 if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
1585 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
1587 return SDMMC_ERROR_CMD_RSP_TIMEOUT;
1590 else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
1593 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
1595 return SDMMC_ERROR_CMD_CRC_FAIL;
1602 if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
1605 __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
1608 return SDMMC_ERROR_NONE;
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
Send the Select Deselect command and check the response.
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
Send the Read Single Block command and check the response.
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
Returns number of remaining data bytes to be transferred.
uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx)
Send the command asking the accessed card to send its operating condition register (OCR) ...
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
Send the Operating Condition command and check the response.
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
Send the Start Address Erase command for SD and check the response.
This file contains all the functions prototypes for the HAL module driver.
void HAL_Delay(uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
SDMMC Data Control structure.
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
Send the Status register command and check the response.
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Send CSD command and check the response.
static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
Checks for error conditions for R7 response.
uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
Get SDMMC Power state.
static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
Checks for error conditions for R2 (CID or CSD) response.
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand.
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
Send the Bus Width command and check the response.
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
Get the FIFO data.
static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
Checks for error conditions for R3 (OCR) response.
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
Read data (word) from Rx FIFO in blocking mode (polling)
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
Send the Go Idle State command and check the response.
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
Configure the SDMMC command path according to the specified parameters in SDMMC_CmdInitTypeDef struct...
static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
Checks for error conditions for CMD0.
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
Send the End Address Erase command and check the response.
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
Send the Data Block Lenght command and check the response.
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
Return the response received from the card for the last command.
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
Send the Start Address Erase command and check the response.
HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
Set SDMMC Power state to Power-Cycle.
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Sends host capacity support information and activates the card's initialization process. Send SDMMC_CMD_SEND_OP_COND command.
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
Send the Send SCR command and check the response.
static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
Checks for error conditions for R1 response.
SDMMC Command Control structure.
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the command asking the accessed card to send its operating condition register (OCR) ...
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
Send the Erase command and check the response.
uint32_t WaitForInterrupt
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
Return the command index of last command for which response received.
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
Send the Write Multi Block command and check the response.
static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
Checks for error conditions for R6 (RCA) response.
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
Send the Stop Transfer command and check the response.
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Application command to verify that that the next command is an application specific com-mand...
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
Initializes the SDMMC according to the specified parameters in the SDMMC_InitTypeDef and create the a...
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
Send the Send CSD command and check the response.
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
Set SDMMC Power state to ON.
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
Send the Send CID command and check the response.
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Send EXT_CSD command and check the response.
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
Write data (word) to Tx FIFO in blocking mode (polling)
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Status command and check the response.
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
Send the End Address Erase command for SD and check the response.
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
Send the Write Single Block command and check the response.
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock))
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
Set SDMMC Power state to OFF.
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
Configure the SDMMC data path according to the specified parameters in the SDMMC_DataInitTypeDef.
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
Send the Read Multi Block command and check the response.