STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_ll_sdmmc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_SDMMC_H
22 #define STM32L4xx_LL_SDMMC_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 #if defined(SDMMC1)
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32l4xx_hal_def.h"
32 
41 /* Exported types ------------------------------------------------------------*/
49 typedef struct
50 {
51  uint32_t ClockEdge;
54 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
55  uint32_t ClockBypass;
58 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
59 
60  uint32_t ClockPowerSave;
64  uint32_t BusWide;
67  uint32_t HardwareFlowControl;
70  uint32_t ClockDiv;
73 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
74  uint32_t Transceiver;
76 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
77 
78 }SDMMC_InitTypeDef;
79 
80 
84 typedef struct
85 {
86  uint32_t Argument;
91  uint32_t CmdIndex;
94  uint32_t Response;
97  uint32_t WaitForInterrupt;
101  uint32_t CPSM;
104 }SDMMC_CmdInitTypeDef;
105 
106 
110 typedef struct
111 {
112  uint32_t DataTimeOut;
114  uint32_t DataLength;
116  uint32_t DataBlockSize;
119  uint32_t TransferDir;
123  uint32_t TransferMode;
126  uint32_t DPSM;
129 }SDMMC_DataInitTypeDef;
130 
135 /* Exported constants --------------------------------------------------------*/
139 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U)
140 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U)
141 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U)
142 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U)
143 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U)
144 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U)
145 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U)
146 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U)
147 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U)
149 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U)
150 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U)
151 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U)
152 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U)
154 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U)
155 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U)
156 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U)
157 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U)
158 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U)
159 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U)
160 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U)
161 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U)
162 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U)
163 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U)
164 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U)
166 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U)
167 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U)
168 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U)
169 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U)
170 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U)
171 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U)
172 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U)
173 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U)
174 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U)
179 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U)
180 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U)
181 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U)
182 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U)
183 #define SDMMC_CMD_SET_DSR ((uint8_t)4U)
184 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U)
186 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U)
187 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U)
188 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U)
190 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U)
191 #define SDMMC_CMD_SEND_CID ((uint8_t)10U)
192 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
193 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U)
194 #else
195 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U)
196 #endif
197 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U)
198 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U)
199 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U)
200 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U)
201 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U)
204 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U)
206 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U)
208 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U)
209 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U)
210 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U)
211 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U)
213 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U)
214 #define SDMMC_CMD_PROG_CID ((uint8_t)26U)
215 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U)
216 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U)
217 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U)
218 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U)
219 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U)
220 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U)
221 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U)
223 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U)
225 #define SDMMC_CMD_ERASE ((uint8_t)38U)
226 #define SDMMC_CMD_FAST_IO ((uint8_t)39U)
227 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U)
228 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U)
230 #define SDMMC_CMD_APP_CMD ((uint8_t)55U)
232 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U)
234 #define SDMMC_CMD_NO_CMD ((uint8_t)64U)
240 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U)
242 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U)
243 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U)
245 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U)
247 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U)
248 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U)
249 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U)
250 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U)
256 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
257 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
258 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
259 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
260 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
261 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
262 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
263 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
264 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
265 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
266 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
267 
271 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
272 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
273 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
274 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
275 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
276 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
277 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
278 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
279 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
280 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
281 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
282 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
283 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
284 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
285 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
286 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
287 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
288 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
289 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
290 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
291 
295 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
296 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
297 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
298 
299 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
300 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
301 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
302 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
303 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
304 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
305 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U)
306 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
307 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
308 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
309 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
310 
311 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
312 
313 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
314 
315 #define SDMMC_ALLZERO ((uint32_t)0x00000000U)
316 
317 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
318 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
319 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
320 
321 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
322 
323 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
324 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
325 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
326 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
327 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
328 
329 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
330 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
331 
335 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
336 
337 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
338 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
339 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
340 
344 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
345 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
346 
347 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
348  ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
349 
353 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
354 
357 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
358 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
359 
360 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
361  ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
362 
365 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
366 
370 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
371 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
372 
373 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
374  ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
375 
382 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
383 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
384 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
385 
386 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
387  ((WIDE) == SDMMC_BUS_WIDE_4B) || \
388  ((WIDE) == SDMMC_BUS_WIDE_8B))
389 
393 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
394 
397 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U)
398 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U)
399 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U)
400 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
401 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
402 
403 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
404  ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
405  ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
406  ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
407  ((MODE) == SDMMC_SPEED_MODE_DDR))
408 
412 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
413 
417 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
418 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
419 
420 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
421  ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
422 
429 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
430 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
431 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
432 #else
433 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU)
434 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
435 
439 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
440 
443 #define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U)
444 #define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U)
445 
446 #define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \
447  ((MODE) == SDMMC_TRANSCEIVER_ENABLE))
448 
451 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
452 
456 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
457 
464 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
465 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
466 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
467 
468 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
469  ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
470  ((RESPONSE) == SDMMC_RESPONSE_LONG))
471 
478 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
479 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
480 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
481 
482 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
483  ((WAIT) == SDMMC_WAIT_IT) || \
484  ((WAIT) == SDMMC_WAIT_PEND))
485 
492 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
493 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
494 
495 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
496  ((CPSM) == SDMMC_CPSM_ENABLE))
497 
504 #define SDMMC_RESP1 ((uint32_t)0x00000000U)
505 #define SDMMC_RESP2 ((uint32_t)0x00000004U)
506 #define SDMMC_RESP3 ((uint32_t)0x00000008U)
507 #define SDMMC_RESP4 ((uint32_t)0x0000000CU)
508 
509 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
510  ((RESP) == SDMMC_RESP2) || \
511  ((RESP) == SDMMC_RESP3) || \
512  ((RESP) == SDMMC_RESP4))
513 
514 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
515 
518 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
519 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
520 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
521 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
522 
526 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
527 
531 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
532 
539 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
540 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
541 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
542 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
543 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
544 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
545 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
546 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
547 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
548 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
549 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
550 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
551 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
552 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
553 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
554 
555 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
556  ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
557  ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
558  ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
559  ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
560  ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
561  ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
562  ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
563  ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
564  ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
565  ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
566  ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
567  ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
568  ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
569  ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
570 
577 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
578 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
579 
580 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
581  ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
582 
589 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
590 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
591 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
592 #else
593 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
594 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
595 
596 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
597  ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
598 
605 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
606 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
607 
608 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
609  ((DPSM) == SDMMC_DPSM_ENABLE))
610 
617 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
618 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
619 
620 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
621  ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
622 
629 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
630 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
631 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
632 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
633 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
634 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
635 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
636 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
637 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
638 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
639 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
640 #endif
641 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
642 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
643 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
644 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
645 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
646 #else
647 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
648 #endif
649 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
650 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
651 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
652 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
653 #endif
654 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
655 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
656 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
657 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
658 #else
659 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
660 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
661 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
662 #endif
663 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
664 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
665 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
666 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
667 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
668 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
669 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
670 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
671 
678 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
679 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
680 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
681 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
682 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
683 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
684 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
685 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
686 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
687 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
688 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
689 #endif
690 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
691 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
692 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
693 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
694 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
695 #else
696 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
697 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
698 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
699 #endif
700 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
701 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
702 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
703 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
704 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
705 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
706 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
707 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
708 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
709 #else
710 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
711 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
712 #endif
713 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
714 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
715 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
716 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
717 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
718 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
719 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
720 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
721 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
722 
723 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
724 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
725  SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
726  SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
727  SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
728  SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
729  SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
730  SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
731 
732 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
733  SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
734 
735 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
736  SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
737  SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
738  SDMMC_FLAG_IDMABTC))
739 
740 #else
741 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
742  SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
743  SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
744  SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT))
745 
746 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
747  SDMMC_FLAG_CMDSENT))
748 
749 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
750  SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND))
751 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
752 
761 /* Exported macro ------------------------------------------------------------*/
770 /* ---------------------- SDMMC registers bit mask --------------------------- */
771 /* --- CLKCR Register ---*/
772 /* CLKCR register clear mask */
773 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
774 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
775  SDMMC_CLKCR_WIDBUS |\
776  SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\
777  SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\
778  SDMMC_CLKCR_SELCLKRX))
779 #else
780 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
781  SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
782  SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
783 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
784 
785 /* --- DCTRL Register ---*/
786 /* SDMMC DCTRL Clear Mask */
787 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
788  SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
789 
790 /* --- CMD Register ---*/
791 /* CMD Register clear mask */
792 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
793 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
794  SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
795  SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND))
796 #else
797 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
798  SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
799  SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
800 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
801 
802 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
803 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 110MHz*/
804 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x8A)
805 
806 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 110MHz*/
807 #define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x3)
808 
809 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 110MHz*/
810 #define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
811 
812 /* SDMMC Data Transfer Frequency (25MHz max) */
813 #define SDMMC_TRANSFER_CLK_DIV SDMMC_NSpeed_CLK_DIV
814 #else
815 /* SDMMC Initialization Frequency (400KHz max) */
816 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
817 
818 /* SDMMC Data Transfer Frequency (25MHz max) */
819 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
820 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
821 
831 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
832 
837 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
838 
844 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
845 
851 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
852 
858 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
859 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
860 
898 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
899 
937 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
938 
980 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
981 
982 
1010 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
1011 
1049 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
1050 
1077 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
1078 
1084 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
1085 
1091 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
1092 
1098 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
1099 
1105 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
1106 
1112 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
1113 
1119 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
1120 
1126 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
1127 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
1128 #else
1129 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
1130 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
1131 
1137 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
1138 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
1139 #else
1140 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
1141 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
1142 
1143 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1144 
1149 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
1150 
1156 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
1157 
1163 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
1164 
1170 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
1171 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1172 
1181 /* Exported functions --------------------------------------------------------*/
1186 /* Initialization/de-initialization functions **********************************/
1190 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
1195 /* I/O operation functions *****************************************************/
1199 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
1200 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
1205 /* Peripheral Control functions ************************************************/
1209 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
1210 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1211 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
1212 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
1213 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
1214 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
1215 
1216 /* Command path state machine (CPSM) management functions */
1217 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
1218 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
1219 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
1220 
1221 /* Data path state machine (DPSM) management functions */
1222 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
1223 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
1224 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
1225 
1226 /* SDMMC Cards mode management functions */
1227 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
1228 
1229 /* SDMMC Commands management functions */
1230 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
1231 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
1232 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
1233 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
1234 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
1235 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
1236 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
1237 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
1238 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
1239 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
1240 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
1241 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
1242 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
1243 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
1244 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1245 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1246 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
1247 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
1248 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
1249 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1250 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
1251 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1252 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
1253 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1254 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
1255 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1256 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1257 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1258 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1259 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1260 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1261 
1285 #endif /* SDMMC1 */
1286 
1287 #ifdef __cplusplus
1288 }
1289 #endif
1290 
1291 #endif /* STM32L4xx_LL_SDMMC_H */
1292 
1293 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SDMMC_CmdBlockLength
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
Send the Data Block Lenght command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:553
SDMMC_CmdOperCond
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
Send the Operating Condition command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:875
SDMMC_CmdSendEXTCSD
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Send EXT_CSD command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:1207
SDMMC_DataInitTypeDef::DataBlockSize
uint32_t DataBlockSize
Definition: stm32l4xx_ll_sdmmc.h:116
SDMMC_CmdInitTypeDef::Argument
uint32_t Argument
Definition: stm32l4xx_ll_sdmmc.h:86
SDMMC_CmdSelDesel
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
Send the Select Deselect command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:828
SDMMC_GetDataCounter
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
Returns number of remaining data bytes to be transferred.
Definition: stm32l4xx_ll_sdmmc.c:494
SDMMC_CmdVoltageSwitch
uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx)
Send the command asking the accessed card to send its operating condition register (OCR) ...
Definition: stm32l4xx_ll_sdmmc.c:1183
SDMMC_CmdInitTypeDef::CmdIndex
uint32_t CmdIndex
Definition: stm32l4xx_ll_sdmmc.h:91
SDMMC_CmdReadSingleBlock
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
Send the Read Single Block command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:577
SDMMC_CmdWriteMultiBlock
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
Send the Write Multi Block command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:649
SDMMC_CmdOpCondition
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Sends host capacity support information and activates the card&#39;s initialization process. Send SDMMC_CMD_SEND_OP_COND command.
Definition: stm32l4xx_ll_sdmmc.c:1132
SDMMC_CmdInitTypeDef::CPSM
uint32_t CPSM
Definition: stm32l4xx_ll_sdmmc.h:101
SDMMC_DataInitTypeDef
SDMMC Data Control structure.
Definition: stm32l4xx_ll_sdmmc.h:110
SDMMC_CmdErase
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
Send the Erase command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:769
SDMMC_CmdSendStatus
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Status command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:1084
SDMMC_CmdSwitch
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand.
Definition: stm32l4xx_ll_sdmmc.c:1156
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
SDMMC_DataInitTypeDef::DPSM
uint32_t DPSM
Definition: stm32l4xx_ll_sdmmc.h:126
SDMMC_GetPowerState
uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
Get SDMMC Power state.
Definition: stm32l4xx_ll_sdmmc.c:378
SDMMC_CmdSDEraseEndAdd
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
Send the End Address Erase command for SD and check the response.
Definition: stm32l4xx_ll_sdmmc.c:697
SDMMC_CmdSendCSD
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Send CSD command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:1034
SDMMC_CmdStatusRegister
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
Send the Status register command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:1107
__WWDG_HandleTypeDef::Init
WWDG_InitTypeDef Init
Definition: stm32l4xx_hal_wwdg.h:71
SDMMC_GetFIFOCount
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
Get the FIFO data.
Definition: stm32l4xx_ll_sdmmc.c:504
SDMMC_ReadFIFO
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
Read data (word) from Rx FIFO in blocking mode (polling)
Definition: stm32l4xx_ll_sdmmc.c:277
SDMMC_CmdSetRelAdd
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
Send the Send CSD command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:1059
SDMMC_SendCommand
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
Configure the SDMMC command path according to the specified parameters in SDMMC_CmdInitTypeDef struct...
Definition: stm32l4xx_ll_sdmmc.c:391
SDMMC_CmdSendCID
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
Send the Send CID command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:1009
SDMMC_DataInitTypeDef::DataLength
uint32_t DataLength
Definition: stm32l4xx_ll_sdmmc.h:114
SDMMC_GetResponse
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
Return the response received from the card for the last command.
Definition: stm32l4xx_ll_sdmmc.c:438
SDMMC_PowerState_Cycle
HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
Set SDMMC Power state to Power-Cycle.
Definition: stm32l4xx_ll_sdmmc.c:343
SDMMC_CmdInitTypeDef
SDMMC Command Control structure.
Definition: stm32l4xx_ll_sdmmc.h:84
SDMMC_CmdWriteSingleBlock
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
Send the Write Single Block command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:625
SDMMC_CmdStopTransfer
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
Send the Stop Transfer command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:793
SDMMC_CmdBusWidth
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
Send the Bus Width command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:962
SDMMC_CmdSendSCR
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
Send the Send SCR command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:985
SDMMC_DataInitTypeDef::DataTimeOut
uint32_t DataTimeOut
Definition: stm32l4xx_ll_sdmmc.h:112
SDMMC_CmdInitTypeDef::WaitForInterrupt
uint32_t WaitForInterrupt
Definition: stm32l4xx_ll_sdmmc.h:97
SDMMC_CmdInitTypeDef::Response
uint32_t Response
Definition: stm32l4xx_ll_sdmmc.h:94
SDMMC_GetCommandResponse
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
Return the command index of last command for which response received.
Definition: stm32l4xx_ll_sdmmc.c:421
SDMMC_CmdAppOperCommand
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the command asking the accessed card to send its operating condition register (OCR) ...
Definition: stm32l4xx_ll_sdmmc.c:934
SDMMC_CmdGoIdleState
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
Send the Go Idle State command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:852
SDMMC_CmdEraseEndAdd
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
Send the End Address Erase command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:745
SDMMC_CmdAppCommand
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
Send the Application command to verify that that the next command is an application specific com-mand...
Definition: stm32l4xx_ll_sdmmc.c:906
SDMMC_Init
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
Initializes the SDMMC according to the specified parameters in the SDMMC_InitTypeDef and create the a...
Definition: stm32l4xx_ll_sdmmc.c:220
SDMMC_CmdReadMultiBlock
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
Send the Read Multi Block command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:601
SDMMC_DataInitTypeDef::TransferDir
uint32_t TransferDir
Definition: stm32l4xx_ll_sdmmc.h:119
SDMMC_CmdEraseStartAdd
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
Send the Start Address Erase command and check the response.
Definition: stm32l4xx_ll_sdmmc.c:721
SDMMC_PowerState_ON
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
Set SDMMC Power state to ON.
Definition: stm32l4xx_ll_sdmmc.c:321
SDMMC_SetSDMMCReadWaitMode
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
Definition: stm32l4xx_ll_sdmmc.c:518
SDMMC_DataInitTypeDef::TransferMode
uint32_t TransferMode
Definition: stm32l4xx_ll_sdmmc.h:123
SDMMC_WriteFIFO
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
Write data (word) to Tx FIFO in blocking mode (polling)
Definition: stm32l4xx_ll_sdmmc.c:289
SDMMC_CmdSDEraseStartAdd
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
Send the Start Address Erase command for SD and check the response.
Definition: stm32l4xx_ll_sdmmc.c:673
SDMMC_PowerState_OFF
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
Set SDMMC Power state to OFF.
Definition: stm32l4xx_ll_sdmmc.c:357
SDMMC_ConfigData
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
Configure the SDMMC data path according to the specified parameters in the SDMMC_DataInitTypeDef.
Definition: stm32l4xx_ll_sdmmc.c:459