33 #ifndef __STM32L4xx_LL_UTILS_H 34 #define __STM32L4xx_LL_UTILS_H 41 #include "stm32l4xx.h" 60 #define LL_MAX_DELAY 0xFFFFFFFFU 65 #define UID_BASE_ADDRESS UID_BASE 70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE 75 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE 153 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U 154 #define LL_UTILS_HSEBYPASS_ON 0x00000001U 162 #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U 163 #define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U 164 #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U 165 #define LL_UTILS_PACKAGETYPE_BGA132 0x00000003U 166 #define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 0x00000004U 167 #define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U 168 #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU 169 #define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU 170 #define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU 171 #define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU 172 #define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU 173 #define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000010U 174 #define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U 175 #define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U 176 #define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U 177 #define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U 178 #define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U 204 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
213 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
222 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
233 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
260 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
279 __STATIC_INLINE
void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
282 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL);
284 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
285 SysTick_CTRL_ENABLE_Msk;
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL...
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
Get Word1 of the unique device identifier (UID based on 96 bits)
ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with MSI as clock source of the PLL.
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
Get Word0 of the unique device identifier (UID based on 96 bits)
UTILS PLL structure definition.
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
void LL_mDelay(uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
Get Word2 of the unique device identifier (UID based on 96 bits)
UTILS System, AHB and APB buses clock configuration structure definition.
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.
void LL_Init1msTick(uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
Get Flash memory size.
__STATIC_INLINE uint32_t LL_GetPackageType(void)
Get Package type.