SYSTEM

System Configuration functions. More...

Functions
void	LL_SetSystemCoreClock (uint32_t HCLKFrequency)
	This function sets directly SystemCoreClock CMSIS variable. More...
ErrorStatus	LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	This function configures system clock with MSI as clock source of the PLL. More...
ErrorStatus	LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	This function configures system clock at maximum frequency with HSI as clock source of the PLL. More...
ErrorStatus	LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	This function configures system clock with HSE as clock source of the PLL. More...

Detailed Description

System Configuration functions.

===============================================================================
          ##### System Configuration functions #####
===============================================================================
   [..]
        System, AHB and APB buses clocks configuration

        (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
            120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others.

Function Documentation

LL_PLL_ConfigSystemClock_HSE()

ErrorStatus LL_PLL_ConfigSystemClock_HSE	(	uint32_t	HSEFrequency,
		uint32_t	HSEBypass,
		LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock with HSE as clock source of the PLL.

Note

The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.

Function is based on the following formula:

• PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
• PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
• PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
• PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)

Parameters

HSEFrequency	Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass	This parameter can be one of the following values: LL_UTILS_HSEBYPASS_ON LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 507 of file stm32l4xx_ll_utils.c.

{
  ErrorStatus status;
  uint32_t pllfreq;
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
  uint32_t hpre = 0U;  /* Set default value */
#endif

  /* Check the parameters */
  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));

  /* Check if one of the PLL is enabled */
  if(UTILS_PLL_IsBusy() == SUCCESS)
  {
    /* Calculate the new PLL output frequency */
    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);

    /* Enable HSE if not enabled */
    if(LL_RCC_HSE_IsReady() != 1U)
    {
      /* Check if need to enable HSE bypass feature or not */
      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
      {
        LL_RCC_HSE_EnableBypass();
      }
      else
      {
        LL_RCC_HSE_DisableBypass();
      }

      /* Enable HSE */
      LL_RCC_HSE_Enable();
      while (LL_RCC_HSE_IsReady() != 1U)
      {
        /* Wait for HSE ready */
      }
    }

    /* Configure PLL */
    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
                                UTILS_PLLInitStruct->PLLR);

#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
    /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
    if(pllfreq > 80000000U)
    {
      hpre = UTILS_ClkInitStruct->AHBCLKDivider;
      if(hpre == LL_RCC_SYSCLK_DIV_1)
      {
        UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
      }
    }
#endif
    /* Enable PLL and switch system clock to PLL */
    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);

#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
    /* Apply definitive AHB prescaler value if necessary */
    if((status == SUCCESS) && (hpre != 0U))
    {
      UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
      LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
    }
#endif
  }
  else
  {
    /* Current PLL configuration cannot be modified */
    status = ERROR;
  }

  return status;
}

LL_PLL_ConfigSystemClock_HSI()

ErrorStatus LL_PLL_ConfigSystemClock_HSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note

The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.

Function is based on the following formula:

• PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
• PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
• PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
• PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR)

Parameters

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 426 of file stm32l4xx_ll_utils.c.

{
  ErrorStatus status;
  uint32_t pllfreq;
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
  uint32_t hpre = 0U;  /* Set default value */
#endif

  /* Check if one of the PLL is enabled */
  if(UTILS_PLL_IsBusy() == SUCCESS)
  {
    /* Calculate the new PLL output frequency */
    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);

    /* Enable HSI if not enabled */
    if(LL_RCC_HSI_IsReady() != 1U)
    {
      LL_RCC_HSI_Enable();
      while (LL_RCC_HSI_IsReady() != 1U)
      {
        /* Wait for HSI ready */
      }
    }

    /* Configure PLL */
    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
                                UTILS_PLLInitStruct->PLLR);

#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
    /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
    if(pllfreq > 80000000U)
    {
      hpre = UTILS_ClkInitStruct->AHBCLKDivider;
      if(hpre == LL_RCC_SYSCLK_DIV_1)
      {
        UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
      }
    }
#endif
    /* Enable PLL and switch system clock to PLL */
    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);

#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
    /* Apply definitive AHB prescaler value if necessary */
    if((status == SUCCESS) && (hpre != 0U))
    {
      UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
      LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
    }
#endif
  }
  else
  {
    /* Current PLL configuration cannot be modified */
    status = ERROR;
  }

  return status;
}

LL_PLL_ConfigSystemClock_MSI()

ErrorStatus LL_PLL_ConfigSystemClock_MSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock with MSI as clock source of the PLL.

Note

The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.

Function is based on the following formula:

• PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
• PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
• PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
• PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)

Parameters

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 300 of file stm32l4xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;
  uint32_t pllfreq, msi_range;
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
  uint32_t hpre = 0U;  /* Set default value */
#endif

  /* Check if one of the PLL is enabled */
  if(UTILS_PLL_IsBusy() == SUCCESS)
  {
    /* Get the current MSI range */
    if(LL_RCC_MSI_IsEnabledRangeSelect() != 0U)
    {
      msi_range =  LL_RCC_MSI_GetRange();
      switch (msi_range)
      {
        case LL_RCC_MSIRANGE_0:     /* MSI = 100 KHz  */
        case LL_RCC_MSIRANGE_1:     /* MSI = 200 KHz  */
        case LL_RCC_MSIRANGE_2:     /* MSI = 400 KHz  */
        case LL_RCC_MSIRANGE_3:     /* MSI = 800 KHz  */
        case LL_RCC_MSIRANGE_4:     /* MSI = 1 MHz    */
        case LL_RCC_MSIRANGE_5:     /* MSI = 2 MHz    */
          /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
          status = ERROR;
          break;

        case LL_RCC_MSIRANGE_6:     /* MSI = 4 MHz    */
        case LL_RCC_MSIRANGE_7:     /* MSI = 8 MHz    */
        case LL_RCC_MSIRANGE_8:     /* MSI = 16 MHz   */
        case LL_RCC_MSIRANGE_9:     /* MSI = 24 MHz   */
        case LL_RCC_MSIRANGE_10:    /* MSI = 32 MHz   */
        case LL_RCC_MSIRANGE_11:    /* MSI = 48 MHz   */
        default:
          break;
      }
    }
    else
    {
      msi_range = LL_RCC_MSI_GetRangeAfterStandby();
      switch (msi_range)
      {
        case LL_RCC_MSISRANGE_4:    /* MSI = 1 MHz    */
        case LL_RCC_MSISRANGE_5:    /* MSI = 2 MHz    */
          /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/
          status = ERROR;
          break;

        case LL_RCC_MSISRANGE_7:    /* MSI = 8 MHz    */
        case LL_RCC_MSISRANGE_6:    /* MSI = 4 MHz    */
        default:
          break;
      }
    }

    /* Main PLL configuration and activation */
    if(status != ERROR)
    {
      /* Calculate the new PLL output frequency */
      pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),
                                            UTILS_PLLInitStruct);

      /* Enable MSI if not enabled */
      if(LL_RCC_MSI_IsReady() != 1U)
      {
        LL_RCC_MSI_Enable();
        while ((LL_RCC_MSI_IsReady() != 1U))
        {
          /* Wait for MSI ready */
        }
      }

      /* Configure PLL */
      LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
                                  UTILS_PLLInitStruct->PLLR);

#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
      /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
      if(pllfreq > 80000000U)
      {
        hpre = UTILS_ClkInitStruct->AHBCLKDivider;
        if(hpre == LL_RCC_SYSCLK_DIV_1)
        {
          UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
        }
      }
#endif
      /* Enable PLL and switch system clock to PLL */
      status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);

#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
      /* Apply definitive AHB prescaler value if necessary */
      if((status == SUCCESS) && (hpre != 0U))
      {
        UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
        LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
      }
#endif
    }
  }
  else
  {
    /* Current PLL configuration cannot be modified */
    status = ERROR;
  }

  return status;
}

LL_SetSystemCoreClock()

void LL_SetSystemCoreClock

(

uint32_t

HCLKFrequency

)

This function sets directly SystemCoreClock CMSIS variable.

Note

Variable can be calculated also through SystemCoreClockUpdate function.

Parameters

HCLKFrequency

HCLK frequency in Hz (can be calculated thanks to RCC helper macro)

Return values

None

Definition at line 278 of file stm32l4xx_ll_utils.c.

{
  /* HCLK clock frequency */
  SystemCoreClock = HCLKFrequency;
}