STM32L4xx_HAL_Driver  1.14.0

Modules

 LPTIM Private Macros
 
 LPTIM Exported Init structure
 
 LPTIM Exported Constants
 
 LPTIM Exported Macros
 
 LPTIM Exported Functions
 
 LPTIM Private Functions
 

Functions

void LL_LPTIM_Disable (LPTIM_TypeDef *LPTIMx)
 Disable the LPTIM instance CR ENABLE LL_LPTIM_Disable. More...
 

Detailed Description

Function Documentation

◆ LL_LPTIM_Disable()

void LL_LPTIM_Disable ( LPTIM_TypeDef *  LPTIMx)

Disable the LPTIM instance CR ENABLE LL_LPTIM_Disable.

Parameters
LPTIMxLow-Power Timer instance
Note
The following sequence is required to solve LPTIM disable HW limitation. Please check Errata Sheet ES0335 for more details under "MCU may remain stuck in LPTIM interrupt when entering Stop mode" section.
Return values
None

Definition at line 199 of file stm32l4xx_ll_lptim.c.

200 {
201  LL_RCC_ClocksTypeDef rcc_clock;
202  uint32_t tmpclksource = 0;
203  uint32_t tmpIER;
204  uint32_t tmpCFGR;
205  uint32_t tmpCMP;
206  uint32_t tmpARR;
207  uint32_t tmpOR;
208 #if defined(LPTIM_RCR_REP)
209  uint32_t tmpRCR;
210 #endif
211 
212  /* Check the parameters */
213  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
214 
215  __disable_irq();
216 
217  /********** Save LPTIM Config *********/
218  /* Save LPTIM source clock */
219  switch ((uint32_t)LPTIMx)
220  {
221  case LPTIM1_BASE:
222  tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
223  break;
224 #if defined(LPTIM2)
225  case LPTIM2_BASE:
226  tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
227  break;
228 #endif /* LPTIM2 */
229  default:
230  break;
231  }
232 
233  /* Save LPTIM configuration registers */
234  tmpIER = LPTIMx->IER;
235  tmpCFGR = LPTIMx->CFGR;
236  tmpCMP = LPTIMx->CMP;
237  tmpARR = LPTIMx->ARR;
238  tmpOR = LPTIMx->OR;
239 #if defined(LPTIM_RCR_REP)
240  tmpRCR = LPTIMx->RCR;
241 #endif
242 
243  /************* Reset LPTIM ************/
244  (void)LL_LPTIM_DeInit(LPTIMx);
245 
246  /********* Restore LPTIM Config *******/
247  LL_RCC_GetSystemClocksFreq(&rcc_clock);
248 
249 #if defined(LPTIM_RCR_REP)
250  if ((tmpCMP != 0UL) || (tmpARR != 0UL) || (tmpRCR != 0UL))
251 #else
252  if ((tmpCMP != 0UL) || (tmpARR != 0UL))
253 #endif
254  {
255  /* Force LPTIM source kernel clock from APB */
256  switch ((uint32_t)LPTIMx)
257  {
258  case LPTIM1_BASE:
259  LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
260  break;
261 #if defined(LPTIM2)
262  case LPTIM2_BASE:
263  LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
264  break;
265 #endif /* LPTIM2 */
266  default:
267  break;
268  }
269 
270  if (tmpCMP != 0UL)
271  {
272  /* Restore CMP and ARR registers (LPTIM should be enabled first) */
273  LPTIMx->CR |= LPTIM_CR_ENABLE;
274  LPTIMx->CMP = tmpCMP;
275 
276  /* Polling on CMP write ok status after above restore operation */
277  do
278  {
279  rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
280  } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
281 
282  LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
283  }
284 
285  if (tmpARR != 0UL)
286  {
287  LPTIMx->CR |= LPTIM_CR_ENABLE;
288  LPTIMx->ARR = tmpARR;
289 
290  LL_RCC_GetSystemClocksFreq(&rcc_clock);
291  /* Polling on ARR write ok status after above restore operation */
292  do
293  {
294  rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
295  } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
296 
297  LL_LPTIM_ClearFlag_ARROK(LPTIMx);
298  }
299 
300 #if defined(LPTIM_RCR_REP)
301  if (tmpRCR != 0UL)
302  {
303  LPTIMx->CR |= LPTIM_CR_ENABLE;
304  LPTIMx->RCR = tmpRCR;
305 
306  LL_RCC_GetSystemClocksFreq(&rcc_clock);
307  /* Polling on RCR write ok status after above restore operation */
308  do
309  {
310  rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
311  } while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
312 
313  LL_LPTIM_ClearFlag_REPOK(LPTIMx);
314  }
315 #endif
316 
317  /* Restore LPTIM source kernel clock */
318  LL_RCC_SetLPTIMClockSource(tmpclksource);
319  }
320 
321  /* Restore configuration registers (LPTIM should be disabled first) */
322  LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
323  LPTIMx->IER = tmpIER;
324  LPTIMx->CFGR = tmpCFGR;
325  LPTIMx->OR = tmpOR;
326 
327  __enable_irq();
328 }
__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
Clear the autoreload register update interrupt flag (ARROKCF). ICR ARROKCF LL_LPTIM_ClearFlag_ARROK...
RCC Clocks Frequency Structure.
__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
Clear the compare register update interrupt flag (CMPOKCF). ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK.
__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
Configure LPTIMx clock source CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource.
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks...
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfu...
__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
Clear the repetition register update interrupt flag (REPOKCF). ICR REPOKCF LL_LPTIM_ClearFlag_REPOK...
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfu...
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
Set LPTIMx registers to their reset values.
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx)
Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfu...
__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
Get LPTIMx clock source CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource.
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock))