STM32L4xx_HAL_Driver  1.14.0
Functions
Input and Output functions
STM32L4xx_HAL_Driver » NAND » NAND Exported Functions

Input Output and memory control functions. More...

Functions

HAL_StatusTypeDef HAL_NAND_Reset (NAND_HandleTypeDef *hnand)
 NAND memory reset. More...
 
HAL_StatusTypeDef HAL_NAND_Read_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
 Read Page(s) from NAND memory block (8-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Write_Page_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
 Write Page(s) to NAND memory block (8-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
 Read Spare area(s) from NAND memory (8-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
 Write Spare area(s) to NAND memory (8-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Read_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
 Read Page(s) from NAND memory block (16-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Write_Page_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
 Write Page(s) to NAND memory block (16-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
 Read Spare area(s) from NAND memory (16-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
 Write Spare area(s) to NAND memory (16-bits addressing) More...
 
HAL_StatusTypeDef HAL_NAND_Erase_Block (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
 NAND memory Block erase. More...
 
uint32_t HAL_NAND_Address_Inc (NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
 Increment the NAND memory address. More...
 
HAL_StatusTypeDef HAL_NAND_Read_ID (NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
 Read the NAND memory electronic signature. More...
 
HAL_StatusTypeDef HAL_NAND_ConfigDevice (NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
 Configure the device: Enter the physical parameters of the device. More...
 

Detailed Description

Input Output and memory control functions. 

  ==============================================================================
                    ##### NAND Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NAND
    memory

Function Documentation

◆ HAL_NAND_Address_Inc()

uint32_t HAL_NAND_Address_Inc ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress 
)

Increment the NAND memory address.

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
Return values
Thenew status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 1630 of file stm32l4xx_hal_nand.c.

1631 {
1632  uint32_t status = NAND_VALID_ADDRESS;
1633 
1634  /* Increment page address */
1635  pAddress->Page++;
1636 
1637  /* Check NAND address is valid */
1638  if (pAddress->Page == hnand->Config.BlockSize)
1639  {
1640  pAddress->Page = 0;
1641  pAddress->Block++;
1642 
1643  if (pAddress->Block == hnand->Config.PlaneSize)
1644  {
1645  pAddress->Block = 0;
1646  pAddress->Plane++;
1647 
1648  if (pAddress->Plane == (hnand->Config.PlaneNbr))
1649  {
1650  status = NAND_INVALID_ADDRESS;
1651  }
1652  }
1653  }
1654 
1655  return (status);
1656 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_AddressTypeDef::Plane
uint16_t Plane
Definition: stm32l4xx_hal_nand.h:80
NAND_AddressTypeDef::Block
uint16_t Block
Definition: stm32l4xx_hal_nand.h:82
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PlaneSize
uint32_t PlaneSize
Definition: stm32l4xx_hal_nand.h:102
NAND_DeviceConfigTypeDef::PlaneNbr
uint32_t PlaneNbr
Definition: stm32l4xx_hal_nand.h:100
NAND_AddressTypeDef::Page
uint16_t Page
Definition: stm32l4xx_hal_nand.h:78

◆ HAL_NAND_ConfigDevice()

HAL_StatusTypeDef HAL_NAND_ConfigDevice ( NAND_HandleTypeDef *  hnand,
NAND_DeviceConfigTypeDef *  pDeviceConfig 
)

Configure the device: Enter the physical parameters of the device.

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pDeviceConfigpointer to NAND_DeviceConfigTypeDef structure
Return values
HALstatus

Definition at line 406 of file stm32l4xx_hal_nand.c.

407 {
408  hnand->Config.PageSize = pDeviceConfig->PageSize;
409  hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
410  hnand->Config.BlockSize = pDeviceConfig->BlockSize;
411  hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
412  hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
413  hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
414  hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
415 
416  return HAL_OK;
417 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
NAND_DeviceConfigTypeDef::PlaneSize
uint32_t PlaneSize
Definition: stm32l4xx_hal_nand.h:102
NAND_DeviceConfigTypeDef::PlaneNbr
uint32_t PlaneNbr
Definition: stm32l4xx_hal_nand.h:100
NAND_DeviceConfigTypeDef::ExtraCommandEnable
FunctionalState ExtraCommandEnable
Definition: stm32l4xx_hal_nand.h:104
NAND_DeviceConfigTypeDef::SpareAreaSize
uint32_t SpareAreaSize
Definition: stm32l4xx_hal_nand.h:93

◆ HAL_NAND_Erase_Block()

HAL_StatusTypeDef HAL_NAND_Erase_Block ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress 
)

NAND memory Block erase.

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
Return values
HALstatus

Definition at line 1580 of file stm32l4xx_hal_nand.c.

1581 {
1582  uint32_t DeviceAddress = 0;
1583 
1584  /* Process Locked */
1585  __HAL_LOCK(hnand);
1586 
1587  /* Check the NAND controller state */
1588  if(hnand->State == HAL_NAND_STATE_BUSY)
1589  {
1590  return HAL_BUSY;
1591  }
1592 
1593  /* Identify the device address */
1594  DeviceAddress = NAND_DEVICE;
1595 
1596  /* Update the NAND controller state */
1597  hnand->State = HAL_NAND_STATE_BUSY;
1598 
1599  /* Send Erase block command sequence */
1600  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
1601  __DSB();
1602  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1603  __DSB();
1604  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1605  __DSB();
1606  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1607  __DSB();
1608 
1609  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
1610  __DSB();
1611 
1612  /* Update the NAND controller state */
1613  hnand->State = HAL_NAND_STATE_READY;
1614 
1615  /* Process unlocked */
1616  __HAL_UNLOCK(hnand);
1617 
1618  return HAL_OK;
1619 }
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885

◆ HAL_NAND_Read_ID()

HAL_StatusTypeDef HAL_NAND_Read_ID ( NAND_HandleTypeDef *  hnand,
NAND_IDTypeDef *  pNAND_ID 
)

Read the NAND memory electronic signature.

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pNAND_IDNAND ID structure
Return values
HALstatus

Definition at line 302 of file stm32l4xx_hal_nand.c.

303 {
304  __IO uint32_t data = 0;
305  __IO uint32_t data1 = 0;
306  uint32_t deviceAddress = 0;
307 
308  /* Process Locked */
309  __HAL_LOCK(hnand);
310 
311  /* Check the NAND controller state */
312  if(hnand->State == HAL_NAND_STATE_BUSY)
313  {
314  return HAL_BUSY;
315  }
316 
317  /* Identify the device address */
318  deviceAddress = NAND_DEVICE;
319 
320  /* Update the NAND controller state */
321  hnand->State = HAL_NAND_STATE_BUSY;
322 
323  /* Send Read ID command sequence */
324  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
325  __DSB();
326  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
327  __DSB();
328 
329  /* Read the electronic signature from NAND flash */
330  if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
331  {
332  data = *(__IO uint32_t *)deviceAddress;
333 
334  /* Return the data read */
335  pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
336  pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
337  pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
338  pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
339  }
340  else
341  {
342  data = *(__IO uint32_t *)deviceAddress;
343  data1 = *((__IO uint32_t *)deviceAddress + 4);
344 
345  /* Return the data read */
346  pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
347  pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
348  pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
349  pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
350  }
351 
352  /* Update the NAND controller state */
353  hnand->State = HAL_NAND_STATE_READY;
354 
355  /* Process unlocked */
356  __HAL_UNLOCK(hnand);
357 
358  return HAL_OK;
359 }
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_IDTypeDef::Third_Id
uint8_t Third_Id
Definition: stm32l4xx_hal_nand.h:68
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
NAND_HandleTypeDef::Init
FMC_NAND_InitTypeDef Init
Definition: stm32l4xx_hal_nand.h:119
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
FMC_NAND_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32l4xx_ll_fmc.h:291
NAND_IDTypeDef::Fourth_Id
uint8_t Fourth_Id
Definition: stm32l4xx_hal_nand.h:70
NAND_IDTypeDef::Device_Id
uint8_t Device_Id
Definition: stm32l4xx_hal_nand.h:66
NAND_IDTypeDef::Maker_Id
uint8_t Maker_Id
Definition: stm32l4xx_hal_nand.h:64

◆ HAL_NAND_Read_Page_16b()

HAL_StatusTypeDef HAL_NAND_Read_Page_16b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint16_t *  pBuffer,
uint32_t  NumPageToRead 
)

Read Page(s) from NAND memory block (16-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to destination read buffer. pBuffer should be 16bits aligned
NumPageToReadnumber of pages to read from block
Return values
HALstatus

Definition at line 572 of file stm32l4xx_hal_nand.c.

573 {
574  __IO uint32_t index = 0;
575  uint32_t tickstart = 0;
576  uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
577 
578  /* Process Locked */
579  __HAL_LOCK(hnand);
580 
581  /* Check the NAND controller state */
582  if (hnand->State == HAL_NAND_STATE_BUSY)
583  {
584  return HAL_BUSY;
585  }
586 
587  /* Identify the device address */
588  deviceAddress = NAND_DEVICE;
589 
590  /* Update the NAND controller state */
591  hnand->State = HAL_NAND_STATE_BUSY;
592 
593  /* NAND raw address calculation */
594  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
595 
596  /* Page(s) read loop */
597  while ((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
598  {
599  /* update the buffer size */
600  size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
601 
602  /* Send read page command sequence */
603  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
604  __DSB();
605 
606  /* Cards with page size <= 512 bytes */
607  if ((hnand->Config.PageSize) <= 512)
608  {
609  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
610  {
611  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
612  __DSB();
613  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
614  __DSB();
615  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
616  __DSB();
617  }
618  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
619  {
620  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
621  __DSB();
622  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
623  __DSB();
624  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
625  __DSB();
626  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
627  __DSB();
628  }
629  }
630  else /* (hnand->Config.PageSize) > 512 */
631  {
632  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
633  {
634  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
635  __DSB();
636  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
637  __DSB();
638  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
639  __DSB();
640  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
641  __DSB();
642  }
643  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
644  {
645  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
646  __DSB();
647  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
648  __DSB();
649  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
650  __DSB();
651  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
652  __DSB();
653  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
654  __DSB();
655  }
656  }
657 
658  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
659  __DSB();
660 
661  if (hnand->Config.ExtraCommandEnable == ENABLE)
662  {
663  /* Get tick */
664  tickstart = HAL_GetTick();
665 
666  /* Read status until NAND is ready */
667  while (HAL_NAND_Read_Status(hnand) != NAND_READY)
668  {
669  if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
670  {
671  return HAL_TIMEOUT;
672  }
673  }
674 
675  /* Go back to read mode */
676  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
677  __DSB();
678  }
679 
680  /* Get Data into Buffer */
681  for (; index < size; index++)
682  {
683  *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
684  }
685 
686  /* Increment read pages number */
687  numPagesRead++;
688 
689  /* Decrement pages to read */
690  NumPageToRead--;
691 
692  /* Increment the NAND address */
693  nandAddress = (uint32_t)(nandAddress + 1);
694  }
695 
696  /* Update the NAND controller state */
697  hnand->State = HAL_NAND_STATE_READY;
698 
699  /* Process unlocked */
700  __HAL_UNLOCK(hnand);
701 
702  return HAL_OK;
703 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797
NAND_DeviceConfigTypeDef::ExtraCommandEnable
FunctionalState ExtraCommandEnable
Definition: stm32l4xx_hal_nand.h:104

◆ HAL_NAND_Read_Page_8b()

HAL_StatusTypeDef HAL_NAND_Read_Page_8b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint8_t *  pBuffer,
uint32_t  NumPageToRead 
)

Read Page(s) from NAND memory block (8-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to destination read buffer
NumPageToReadnumber of pages to read from block
Return values
HALstatus

Definition at line 429 of file stm32l4xx_hal_nand.c.

430 {
431  __IO uint32_t index = 0;
432  uint32_t tickstart = 0U;
433  uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
434 
435  /* Process Locked */
436  __HAL_LOCK(hnand);
437 
438  /* Check the NAND controller state */
439  if(hnand->State == HAL_NAND_STATE_BUSY)
440  {
441  return HAL_BUSY;
442  }
443 
444  /* Identify the device address */
445  deviceAddress = NAND_DEVICE;
446 
447  /* Update the NAND controller state */
448  hnand->State = HAL_NAND_STATE_BUSY;
449 
450  /* NAND raw address calculation */
451  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
452 
453  /* Page(s) read loop */
454  while ((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
455  {
456  /* update the buffer size */
457  size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
458 
459  /* Send read page command sequence */
460  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
461  __DSB();
462 
463  /* Cards with page size <= 512 bytes */
464  if ((hnand->Config.PageSize) <= 512)
465  {
466  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
467  {
468  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
469  __DSB();
470  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
471  __DSB();
472  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
473  __DSB();
474  }
475  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
476  {
477  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
478  __DSB();
479  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
480  __DSB();
481  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
482  __DSB();
483  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
484  __DSB();
485  }
486  }
487  else /* (hnand->Config.PageSize) > 512 */
488  {
489  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
490  {
491  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
492  __DSB();
493  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
494  __DSB();
495  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
496  __DSB();
497  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
498  __DSB();
499  }
500  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
501  {
502  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
503  __DSB();
504  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
505  __DSB();
506  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
507  __DSB();
508  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
509  __DSB();
510  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
511  __DSB();
512  }
513  }
514 
515  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
516  __DSB();
517 
518 
519  if (hnand->Config.ExtraCommandEnable == ENABLE)
520  {
521  /* Get tick */
522  tickstart = HAL_GetTick();
523 
524  /* Read status until NAND is ready */
525  while (HAL_NAND_Read_Status(hnand) != NAND_READY)
526  {
527  if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
528  {
529  return HAL_TIMEOUT;
530  }
531  }
532 
533  /* Go back to read mode */
534  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
535  __DSB();
536  }
537 
538  /* Get Data into Buffer */
539  for(; index < size; index++)
540  {
541  *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
542  }
543 
544  /* Increment read pages number */
545  numPagesRead++;
546 
547  /* Decrement pages to read */
548  NumPageToRead--;
549 
550  /* Increment the NAND address */
551  nandAddress = (uint32_t)(nandAddress + 1);
552  }
553 
554  /* Update the NAND controller state */
555  hnand->State = HAL_NAND_STATE_READY;
556 
557  /* Process unlocked */
558  __HAL_UNLOCK(hnand);
559 
560  return HAL_OK;
561 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797
NAND_DeviceConfigTypeDef::ExtraCommandEnable
FunctionalState ExtraCommandEnable
Definition: stm32l4xx_hal_nand.h:104

◆ HAL_NAND_Read_SpareArea_16b()

HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint16_t *  pBuffer,
uint32_t  NumSpareAreaToRead 
)

Read Spare area(s) from NAND memory (16-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to source buffer to write. pBuffer should be 16bits aligned.
NumSpareAreaToReadNumber of spare area to read
Return values
HALstatus

Definition at line 1139 of file stm32l4xx_hal_nand.c.

1140 {
1141  __IO uint32_t index = 0;
1142  uint32_t tickstart = 0U;
1143  uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
1144 
1145  /* Process Locked */
1146  __HAL_LOCK(hnand);
1147 
1148  /* Check the NAND controller state */
1149  if(hnand->State == HAL_NAND_STATE_BUSY)
1150  {
1151  return HAL_BUSY;
1152  }
1153 
1154  /* Identify the device address */
1155  deviceAddress = NAND_DEVICE;
1156 
1157  /* Update the NAND controller state */
1158  hnand->State = HAL_NAND_STATE_BUSY;
1159 
1160  /* NAND raw address calculation */
1161  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1162 
1163  /* Column in page address */
1164  columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
1165 
1166  /* Spare area(s) read loop */
1167  while ((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1168  {
1169  /* update the buffer size */
1170  size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
1171 
1172  /* Cards with page size <= 512 bytes */
1173  if ((hnand->Config.PageSize) <= 512)
1174  {
1175  /* Send read spare area command sequence */
1176  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1177  __DSB();
1178 
1179  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1180  {
1181  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1182  __DSB();
1183  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1184  __DSB();
1185  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1186  __DSB();
1187  }
1188  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1189  {
1190  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1191  __DSB();
1192  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1193  __DSB();
1194  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1195  __DSB();
1196  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1197  __DSB();
1198  }
1199  }
1200  else /* (hnand->Config.PageSize) > 512 */
1201  {
1202  /* Send read spare area command sequence */
1203  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1204  __DSB();
1205 
1206  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1207  {
1208  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1209  __DSB();
1210  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1211  __DSB();
1212  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1213  __DSB();
1214  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1215  __DSB();
1216  }
1217  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1218  {
1219  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1220  __DSB();
1221  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1222  __DSB();
1223  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1224  __DSB();
1225  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1226  __DSB();
1227  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1228  __DSB();
1229  }
1230  }
1231 
1232  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1233  __DSB();
1234 
1235  if (hnand->Config.ExtraCommandEnable == ENABLE)
1236  {
1237  /* Get tick */
1238  tickstart = HAL_GetTick();
1239 
1240  /* Read status until NAND is ready */
1241  while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1242  {
1243  if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1244  {
1245  return HAL_TIMEOUT;
1246  }
1247  }
1248 
1249  /* Go back to read mode */
1250  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
1251  __DSB();
1252  }
1253 
1254  /* Get Data into Buffer */
1255  for ( ;index < size; index++)
1256  {
1257  *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
1258  }
1259 
1260  /* Increment read spare areas number */
1261  numSpareAreaRead++;
1262 
1263  /* Decrement spare areas to read */
1264  NumSpareAreaToRead--;
1265 
1266  /* Increment the NAND address */
1267  nandAddress = (uint32_t)(nandAddress + 1);
1268  }
1269 
1270  /* Update the NAND controller state */
1271  hnand->State = HAL_NAND_STATE_READY;
1272 
1273  /* Process unlocked */
1274  __HAL_UNLOCK(hnand);
1275 
1276  return HAL_OK;
1277 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797
NAND_DeviceConfigTypeDef::ExtraCommandEnable
FunctionalState ExtraCommandEnable
Definition: stm32l4xx_hal_nand.h:104
NAND_DeviceConfigTypeDef::SpareAreaSize
uint32_t SpareAreaSize
Definition: stm32l4xx_hal_nand.h:93

◆ HAL_NAND_Read_SpareArea_8b()

HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint8_t *  pBuffer,
uint32_t  NumSpareAreaToRead 
)

Read Spare area(s) from NAND memory (8-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to source buffer to write
NumSpareAreaToReadNumber of spare area to read
Return values
HALstatus

Definition at line 990 of file stm32l4xx_hal_nand.c.

991 {
992  __IO uint32_t index = 0;
993  uint32_t tickstart = 0U;
994  uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
995 
996  /* Process Locked */
997  __HAL_LOCK(hnand);
998 
999  /* Check the NAND controller state */
1000  if (hnand->State == HAL_NAND_STATE_BUSY)
1001  {
1002  return HAL_BUSY;
1003  }
1004 
1005  /* Identify the device address */
1006  deviceAddress = NAND_DEVICE;
1007 
1008  /* Update the NAND controller state */
1009  hnand->State = HAL_NAND_STATE_BUSY;
1010 
1011  /* NAND raw address calculation */
1012  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1013 
1014  /* Column in page address */
1015  columnAddress = COLUMN_ADDRESS(hnand);
1016 
1017  /* Spare area(s) read loop */
1018  while ((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1019  {
1020  /* update the buffer size */
1021  size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
1022 
1023  /* Cards with page size <= 512 bytes */
1024  if ((hnand->Config.PageSize) <= 512)
1025  {
1026  /* Send read spare area command sequence */
1027  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1028  __DSB();
1029 
1030  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1031  {
1032  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1033  __DSB();
1034  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1035  __DSB();
1036  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1037  __DSB();
1038  }
1039  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1040  {
1041  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1042  __DSB();
1043  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1044  __DSB();
1045  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1046  __DSB();
1047  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1048  __DSB();
1049  }
1050  }
1051  else /* (hnand->Config.PageSize) > 512 */
1052  {
1053  /* Send read spare area command sequence */
1054  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1055  __DSB();
1056 
1057  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1058  {
1059  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1060  __DSB();
1061  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1062  __DSB();
1063  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1064  __DSB();
1065  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1066  __DSB();
1067  }
1068  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1069  {
1070  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1071  __DSB();
1072  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1073  __DSB();
1074  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1075  __DSB();
1076  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1077  __DSB();
1078  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1079  __DSB();
1080  }
1081  }
1082 
1083  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1084  __DSB();
1085 
1086  if (hnand->Config.ExtraCommandEnable == ENABLE)
1087  {
1088  /* Get tick */
1089  tickstart = HAL_GetTick();
1090 
1091  /* Read status until NAND is ready */
1092  while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1093  {
1094  if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1095  {
1096  return HAL_TIMEOUT;
1097  }
1098  }
1099 
1100  /* Go back to read mode */
1101  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
1102  __DSB();
1103  }
1104 
1105  /* Get Data into Buffer */
1106  for (; index < size; index++)
1107  {
1108  *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
1109  }
1110 
1111  /* Increment read spare areas number */
1112  numSpareAreaRead++;
1113 
1114  /* Decrement spare areas to read */
1115  NumSpareAreaToRead--;
1116 
1117  /* Increment the NAND address */
1118  nandAddress = (uint32_t)(nandAddress + 1);
1119  }
1120 
1121  /* Update the NAND controller state */
1122  hnand->State = HAL_NAND_STATE_READY;
1123 
1124  /* Process unlocked */
1125  __HAL_UNLOCK(hnand);
1126 
1127  return HAL_OK;
1128 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797
NAND_DeviceConfigTypeDef::ExtraCommandEnable
FunctionalState ExtraCommandEnable
Definition: stm32l4xx_hal_nand.h:104
NAND_DeviceConfigTypeDef::SpareAreaSize
uint32_t SpareAreaSize
Definition: stm32l4xx_hal_nand.h:93

◆ HAL_NAND_Reset()

HAL_StatusTypeDef HAL_NAND_Reset ( NAND_HandleTypeDef *  hnand)

NAND memory reset.

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
Return values
HALstatus

Definition at line 367 of file stm32l4xx_hal_nand.c.

368 {
369  uint32_t deviceAddress = 0;
370 
371  /* Process Locked */
372  __HAL_LOCK(hnand);
373 
374  /* Check the NAND controller state */
375  if(hnand->State == HAL_NAND_STATE_BUSY)
376  {
377  return HAL_BUSY;
378  }
379 
380  /* Identify the device address */
381  deviceAddress = NAND_DEVICE;
382 
383  /* Update the NAND controller state */
384  hnand->State = HAL_NAND_STATE_BUSY;
385 
386  /* Send NAND reset command */
387  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
388 
389  /* Update the NAND controller state */
390  hnand->State = HAL_NAND_STATE_READY;
391 
392  /* Process unlocked */
393  __HAL_UNLOCK(hnand);
394 
395  return HAL_OK;
396 
397 }
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885

◆ HAL_NAND_Write_Page_16b()

HAL_StatusTypeDef HAL_NAND_Write_Page_16b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint16_t *  pBuffer,
uint32_t  NumPageToWrite 
)

Write Page(s) to NAND memory block (16-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to source buffer to write. pBuffer should be 16bits aligned
NumPageToWritenumber of pages to write to block
Return values
HALstatus

Definition at line 852 of file stm32l4xx_hal_nand.c.

853 {
854  __IO uint32_t index = 0;
855  uint32_t tickstart = 0;
856  uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
857 
858  /* Process Locked */
859  __HAL_LOCK(hnand);
860 
861  /* Check the NAND controller state */
862  if (hnand->State == HAL_NAND_STATE_BUSY)
863  {
864  return HAL_BUSY;
865  }
866 
867  /* Identify the device address */
868  deviceAddress = NAND_DEVICE;
869 
870  /* Update the NAND controller state */
871  hnand->State = HAL_NAND_STATE_BUSY;
872 
873  /* NAND raw address calculation */
874  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
875 
876  /* Page(s) write loop */
877  while ((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
878  {
879  /* update the buffer size */
880  size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
881 
882  /* Send write page command sequence */
883  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
884  __DSB();
885  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
886  __DSB();
887 
888  /* Cards with page size <= 512 bytes */
889  if ((hnand->Config.PageSize) <= 512)
890  {
891  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
892  {
893  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
894  __DSB();
895  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
896  __DSB();
897  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
898  __DSB();
899  }
900  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
901  {
902  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
903  __DSB();
904  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
905  __DSB();
906  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
907  __DSB();
908  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
909  __DSB();
910  }
911  }
912  else /* (hnand->Config.PageSize) > 512 */
913  {
914  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
915  {
916  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
917  __DSB();
918  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
919  __DSB();
920  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
921  __DSB();
922  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
923  __DSB();
924  }
925  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
926  {
927  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
928  __DSB();
929  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
930  __DSB();
931  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
932  __DSB();
933  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
934  __DSB();
935  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
936  __DSB();
937  }
938  }
939 
940  /* Write data to memory */
941  for(; index < size; index++)
942  {
943  *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
944  __DSB();
945  }
946 
947  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
948  __DSB();
949 
950  /* Get tick */
951  tickstart = HAL_GetTick();
952 
953  /* Read status until NAND is ready */
954  while(HAL_NAND_Read_Status(hnand) != NAND_READY)
955  {
956  if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
957  {
958  return HAL_TIMEOUT;
959  }
960  }
961 
962  /* Increment written pages number */
963  numPagesWritten++;
964 
965  /* Decrement pages to write */
966  NumPageToWrite--;
967 
968  /* Increment the NAND address */
969  nandAddress = (uint32_t)(nandAddress + 1);
970  }
971 
972  /* Update the NAND controller state */
973  hnand->State = HAL_NAND_STATE_READY;
974 
975  /* Process unlocked */
976  __HAL_UNLOCK(hnand);
977 
978  return HAL_OK;
979 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797

◆ HAL_NAND_Write_Page_8b()

HAL_StatusTypeDef HAL_NAND_Write_Page_8b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint8_t *  pBuffer,
uint32_t  NumPageToWrite 
)

Write Page(s) to NAND memory block (8-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to source buffer to write
NumPageToWritenumber of pages to write to block
Return values
HALstatus

Definition at line 714 of file stm32l4xx_hal_nand.c.

715 {
716  __IO uint32_t index = 0;
717  uint32_t tickstart = 0;
718  uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
719 
720  /* Process Locked */
721  __HAL_LOCK(hnand);
722 
723  /* Check the NAND controller state */
724  if(hnand->State == HAL_NAND_STATE_BUSY)
725  {
726  return HAL_BUSY;
727  }
728 
729  /* Identify the device address */
730  deviceAddress = NAND_DEVICE;
731 
732  /* Update the NAND controller state */
733  hnand->State = HAL_NAND_STATE_BUSY;
734 
735  /* NAND raw address calculation */
736  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
737 
738  /* Page(s) write loop */
739  while ((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
740  {
741  /* update the buffer size */
742  size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
743 
744  /* Send write page command sequence */
745  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
746  __DSB();
747  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
748  __DSB();
749 
750  /* Cards with page size <= 512 bytes */
751  if ((hnand->Config.PageSize) <= 512)
752  {
753  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
754  {
755  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
756  __DSB();
757  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
758  __DSB();
759  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
760  __DSB();
761  }
762  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
763  {
764  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
765  __DSB();
766  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
767  __DSB();
768  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
769  __DSB();
770  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
771  __DSB();
772  }
773  }
774  else /* (hnand->Config.PageSize) > 512 */
775  {
776  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
777  {
778  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
779  __DSB();
780  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
781  __DSB();
782  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
783  __DSB();
784  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
785  __DSB();
786  }
787  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
788  {
789  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
790  __DSB();
791  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
792  __DSB();
793  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
794  __DSB();
795  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
796  __DSB();
797  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
798  __DSB();
799  }
800  }
801 
802  /* Write data to memory */
803  for (; index < size; index++)
804  {
805  *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
806  __DSB();
807  }
808 
809  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
810  __DSB();
811 
812  /* Get tick */
813  tickstart = HAL_GetTick();
814 
815  /* Read status until NAND is ready */
816  while (HAL_NAND_Read_Status(hnand) != NAND_READY)
817  {
818  if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
819  {
820  return HAL_TIMEOUT;
821  }
822  }
823 
824  /* Increment written pages number */
825  numPagesWritten++;
826 
827  /* Decrement pages to write */
828  NumPageToWrite--;
829 
830  /* Increment the NAND address */
831  nandAddress = (uint32_t)(nandAddress + 1);
832  }
833 
834  /* Update the NAND controller state */
835  hnand->State = HAL_NAND_STATE_READY;
836 
837  /* Process unlocked */
838  __HAL_UNLOCK(hnand);
839 
840  return HAL_OK;
841 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797

◆ HAL_NAND_Write_SpareArea_16b()

HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint16_t *  pBuffer,
uint32_t  NumSpareAreaTowrite 
)

Write Spare area(s) to NAND memory (16-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to source buffer to write. pBuffer should be 16bits aligned.
NumSpareAreaTowritenumber of spare areas to write to block
Return values
HALstatus

Definition at line 1435 of file stm32l4xx_hal_nand.c.

1436 {
1437  __IO uint32_t index = 0;
1438  uint32_t tickstart = 0;
1439  uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0;
1440 
1441  /* Process Locked */
1442  __HAL_LOCK(hnand);
1443 
1444  /* Check the NAND controller state */
1445  if (hnand->State == HAL_NAND_STATE_BUSY)
1446  {
1447  return HAL_BUSY;
1448  }
1449 
1450  /* Identify the device address */
1451  deviceAddress = NAND_DEVICE;
1452 
1453  /* Update the FMC_NAND controller state */
1454  hnand->State = HAL_NAND_STATE_BUSY;
1455 
1456  /* NAND raw address calculation */
1457  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1458 
1459  /* Column in page address */
1460  columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
1461 
1462  /* Spare area(s) write loop */
1463  while ((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1464  {
1465  /* update the buffer size */
1466  size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
1467 
1468  /* Cards with page size <= 512 bytes */
1469  if ((hnand->Config.PageSize) <= 512)
1470  {
1471  /* Send write Spare area command sequence */
1472  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1473  __DSB();
1474  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1475  __DSB();
1476 
1477  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1478  {
1479  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1480  __DSB();
1481  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1482  __DSB();
1483  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1484  __DSB();
1485  }
1486  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1487  {
1488  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1489  __DSB();
1490  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1491  __DSB();
1492  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1493  __DSB();
1494  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1495  __DSB();
1496  }
1497  }
1498  else /* (hnand->Config.PageSize) > 512 */
1499  {
1500  /* Send write Spare area command sequence */
1501  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1502  __DSB();
1503  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1504  __DSB();
1505 
1506  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1507  {
1508  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1509  __DSB();
1510  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1511  __DSB();
1512  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1513  __DSB();
1514  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1515  __DSB();
1516  }
1517  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1518  {
1519  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1520  __DSB();
1521  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1522  __DSB();
1523  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1524  __DSB();
1525  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1526  __DSB();
1527  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1528  __DSB();
1529  }
1530  }
1531 
1532  /* Write data to memory */
1533  for (; index < size; index++)
1534  {
1535  *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
1536  __DSB();
1537  }
1538 
1539  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1540  __DSB();
1541 
1542  /* Get tick */
1543  tickstart = HAL_GetTick();
1544 
1545  /* Read status until NAND is ready */
1546  while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1547  {
1548  if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1549  {
1550  return HAL_TIMEOUT;
1551  }
1552  }
1553 
1554  /* Increment written spare areas number */
1555  numSpareAreaWritten++;
1556 
1557  /* Decrement spare areas to write */
1558  NumSpareAreaTowrite--;
1559 
1560  /* Increment the NAND address */
1561  nandAddress = (uint32_t)(nandAddress + 1);
1562  }
1563 
1564  /* Update the NAND controller state */
1565  hnand->State = HAL_NAND_STATE_READY;
1566 
1567  /* Process unlocked */
1568  __HAL_UNLOCK(hnand);
1569 
1570  return HAL_OK;
1571 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797
NAND_DeviceConfigTypeDef::SpareAreaSize
uint32_t SpareAreaSize
Definition: stm32l4xx_hal_nand.h:93

◆ HAL_NAND_Write_SpareArea_8b()

HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b ( NAND_HandleTypeDef *  hnand,
NAND_AddressTypeDef *  pAddress,
uint8_t *  pBuffer,
uint32_t  NumSpareAreaTowrite 
)

Write Spare area(s) to NAND memory (8-bits addressing)

Parameters
hnandpointer to a NAND_HandleTypeDef structure that contains the configuration information for NAND module.
pAddresspointer to NAND address structure
pBufferpointer to source buffer to write
NumSpareAreaTowritenumber of spare areas to write to block
Return values
HALstatus

Definition at line 1288 of file stm32l4xx_hal_nand.c.

1289 {
1290  __IO uint32_t index = 0;
1291  uint32_t tickstart = 0;
1292  uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0;
1293 
1294  /* Process Locked */
1295  __HAL_LOCK(hnand);
1296 
1297  /* Check the NAND controller state */
1298  if(hnand->State == HAL_NAND_STATE_BUSY)
1299  {
1300  return HAL_BUSY;
1301  }
1302 
1303  /* Identify the device address */
1304  deviceAddress = NAND_DEVICE;
1305 
1306  /* Update the FMC_NAND controller state */
1307  hnand->State = HAL_NAND_STATE_BUSY;
1308 
1309  /* Page address calculation */
1310  nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1311 
1312  /* Column in page address */
1313  columnAddress = COLUMN_ADDRESS(hnand);
1314 
1315  /* Spare area(s) write loop */
1316  while ((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1317  {
1318  /* update the buffer size */
1319  size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
1320 
1321  /* Cards with page size <= 512 bytes */
1322  if ((hnand->Config.PageSize) <= 512)
1323  {
1324  /* Send write Spare area command sequence */
1325  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1326  __DSB();
1327  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1328  __DSB();
1329 
1330  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1331  {
1332  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1333  __DSB();
1334  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1335  __DSB();
1336  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1337  __DSB();
1338  }
1339  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1340  {
1341  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
1342  __DSB();
1343  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1344  __DSB();
1345  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1346  __DSB();
1347  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1348  __DSB();
1349  }
1350  }
1351  else /* (hnand->Config.PageSize) > 512 */
1352  {
1353  /* Send write Spare area command sequence */
1354  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1355  __DSB();
1356  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1357  __DSB();
1358 
1359  if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535)
1360  {
1361  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1362  __DSB();
1363  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1364  __DSB();
1365  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1366  __DSB();
1367  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1368  __DSB();
1369  }
1370  else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1371  {
1372  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1373  __DSB();
1374  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1375  __DSB();
1376  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1377  __DSB();
1378  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1379  __DSB();
1380  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1381  __DSB();
1382  }
1383  }
1384 
1385  /* Write data to memory */
1386  for(; index < size; index++)
1387  {
1388  *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
1389  __DSB();
1390  }
1391 
1392  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1393  __DSB();
1394 
1395  /* Get tick */
1396  tickstart = HAL_GetTick();
1397 
1398  /* Read status until NAND is ready */
1399  while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1400  {
1401  if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1402  {
1403  return HAL_TIMEOUT;
1404  }
1405  }
1406 
1407  /* Increment written spare areas number */
1408  numSpareAreaWritten++;
1409 
1410  /* Decrement spare areas to write */
1411  NumSpareAreaTowrite--;
1412 
1413  /* Increment the NAND address */
1414  nandAddress = (uint32_t)(nandAddress + 1);
1415  }
1416 
1417  /* Update the NAND controller state */
1418  hnand->State = HAL_NAND_STATE_READY;
1419 
1420  /* Process unlocked */
1421  __HAL_UNLOCK(hnand);
1422 
1423  return HAL_OK;
1424 }
NAND_DeviceConfigTypeDef::BlockSize
uint32_t BlockSize
Definition: stm32l4xx_hal_nand.h:96
NAND_HandleTypeDef::State
__IO HAL_NAND_StateTypeDef State
Definition: stm32l4xx_hal_nand.h:123
NAND_DeviceConfigTypeDef::BlockNbr
uint32_t BlockNbr
Definition: stm32l4xx_hal_nand.h:98
NAND_HandleTypeDef::Config
NAND_DeviceConfigTypeDef Config
Definition: stm32l4xx_hal_nand.h:125
NAND_DeviceConfigTypeDef::PageSize
uint32_t PageSize
Definition: stm32l4xx_hal_nand.h:90
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
__HAL_UNLOCK
__HAL_UNLOCK(hrtc)
__HAL_LOCK
__HAL_LOCK(hrtc)
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
HAL_NAND_Read_Status
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
NAND memory read status.
Definition: stm32l4xx_hal_nand.c:1797
NAND_DeviceConfigTypeDef::SpareAreaSize
uint32_t SpareAreaSize
Definition: stm32l4xx_hal_nand.h:93