STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_adc.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_HAL_ADC_H
22 #define STM32L4xx_HAL_ADC_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
31 /* Include low level driver */
32 #include "stm32l4xx_ll_adc.h"
33 
42 /* Exported types ------------------------------------------------------------*/
50 typedef struct
51 {
52  uint32_t Ratio;
55  uint32_t RightBitShift;
58  uint32_t TriggeredMode;
61  uint32_t OversamplingStopReset;
69 } ADC_OversamplingTypeDef;
70 
87 typedef struct
88 {
89  uint32_t ClockPrescaler;
100  uint32_t Resolution;
103  uint32_t DataAlign;
107  uint32_t ScanConvMode;
115  uint32_t EOCSelection;
118  FunctionalState LowPowerAutoWait;
130  FunctionalState ContinuousConvMode;
134  uint32_t NbrOfConversion;
140  FunctionalState DiscontinuousConvMode;
146  uint32_t NbrOfDiscConversion;
150  uint32_t ExternalTrigConv;
155  uint32_t ExternalTrigConvEdge;
159  FunctionalState DMAContinuousRequests;
164  uint32_t Overrun;
175  FunctionalState OversamplingMode;
179  ADC_OversamplingTypeDef Oversampling;
182 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
183  uint32_t DFSDMConfig;
187 #endif
188 } ADC_InitTypeDef;
189 
201 typedef struct
202 {
203  uint32_t Channel;
207  uint32_t Rank;
212  uint32_t SamplingTime;
223  uint32_t SingleDiff;
235  uint32_t OffsetNumber;
239  uint32_t Offset;
246 } ADC_ChannelConfTypeDef;
247 
254 typedef struct
255 {
256  uint32_t WatchdogNumber;
261  uint32_t WatchdogMode;
266  uint32_t Channel;
271  FunctionalState ITMode;
274  uint32_t HighThreshold;
284  uint32_t LowThreshold;
293 } ADC_AnalogWDGConfTypeDef;
294 
299 typedef struct
300 {
301  uint32_t ContextQueue;
305  uint32_t ChannelCount;
306 } ADC_InjectionConfigTypeDef;
307 
320 /* States of ADC global scope */
321 #define HAL_ADC_STATE_RESET (0x00000000UL)
322 #define HAL_ADC_STATE_READY (0x00000001UL)
323 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL)
324 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL)
326 /* States of ADC errors */
327 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL)
328 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL)
329 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL)
331 /* States of ADC group regular */
332 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL)
334 #define HAL_ADC_STATE_REG_EOC (0x00000200UL)
335 #define HAL_ADC_STATE_REG_OVR (0x00000400UL)
336 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL)
338 /* States of ADC group injected */
339 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL)
341 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL)
342 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL)
344 /* States of ADC analog watchdogs */
345 #define HAL_ADC_STATE_AWD1 (0x00010000UL)
346 #define HAL_ADC_STATE_AWD2 (0x00020000UL)
347 #define HAL_ADC_STATE_AWD3 (0x00040000UL)
349 /* States of ADC multi-mode */
350 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL)
359 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
360 typedef struct __ADC_HandleTypeDef
361 #else
362 typedef struct
363 #endif
364 {
365  ADC_TypeDef *Instance;
366  ADC_InitTypeDef Init;
367  DMA_HandleTypeDef *DMA_Handle;
368  HAL_LockTypeDef Lock;
369  __IO uint32_t State;
370  __IO uint32_t ErrorCode;
371  ADC_InjectionConfigTypeDef InjectionConfig ;
372 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
373  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);
374  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);
375  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);
376  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);
377  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);
378  void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc);
379  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);
380  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);
381  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);
382  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);
383  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);
384 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
385 } ADC_HandleTypeDef;
386 
387 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
388 
391 typedef enum
392 {
393  HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U,
394  HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U,
395  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U,
396  HAL_ADC_ERROR_CB_ID = 0x03U,
397  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,
398  HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U,
399  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U,
400  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U,
401  HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U,
402  HAL_ADC_MSPINIT_CB_ID = 0x09U,
403  HAL_ADC_MSPDEINIT_CB_ID = 0x0AU
404 } HAL_ADC_CallbackIDTypeDef;
405 
409 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc);
411 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
412 
418 /* Exported constants --------------------------------------------------------*/
419 
427 #define HAL_ADC_ERROR_NONE (0x00U)
428 #define HAL_ADC_ERROR_INTERNAL (0x01U)
430 #define HAL_ADC_ERROR_OVR (0x02U)
431 #define HAL_ADC_ERROR_DMA (0x04U)
432 #define HAL_ADC_ERROR_JQOVF (0x08U)
433 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
434 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U)
435 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
436 
443 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1)
444 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2)
445 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4)
447 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1)
448 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2)
449 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4)
450 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6)
451 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8)
452 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10)
453 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12)
454 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16)
455 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32)
456 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64)
457 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128)
458 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256)
466 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B)
467 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B)
468 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B)
469 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B)
477 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)
478 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT)
486 #define ADC_SCAN_DISABLE (0x00000000UL)
487 #define ADC_SCAN_ENABLE (0x00000001UL)
495 /* ADC group regular trigger sources for all ADC instances */
496 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE)
497 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
498 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
499 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
500 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
501 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
502 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
503 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
504 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
505 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
506 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
507 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
508 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
509 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
510 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
511 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
512 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
520 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL)
521 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING)
522 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING)
523 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING)
531 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC)
532 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS)
540 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED)
541 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN)
549 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1)
550 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2)
551 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3)
552 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4)
553 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5)
554 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6)
555 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7)
556 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8)
557 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9)
558 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10)
559 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11)
560 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12)
561 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13)
562 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14)
563 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15)
564 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16)
572 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5)
573 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5)
574 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5)
575 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5)
576 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5)
577 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5)
578 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5)
579 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5)
580 #if defined(ADC_SMPR1_SMPPLUS)
581 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5)
582 #endif
583 
590 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
591 /* all ADC instances (refer to Reference Manual). */
592 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0)
593 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1)
594 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2)
595 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3)
596 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4)
597 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5)
598 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6)
599 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7)
600 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8)
601 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9)
602 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10)
603 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11)
604 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12)
605 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13)
606 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14)
607 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15)
608 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16)
609 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17)
610 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18)
611 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT)
612 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR)
613 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT)
614 #if defined(ADC1) && !defined(ADC2)
615 #define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1)
616 #define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2)
617 #elif defined(ADC2)
618 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2)
619 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2)
620 #if defined(ADC3)
621 #define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3)
622 #define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3)
623 #endif
624 #endif
625 
632 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1)
633 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2)
634 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3)
642 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL)
643 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)
644 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)
645 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
646 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN)
647 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN)
648 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)
656 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2)
657 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4)
658 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8)
659 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16)
660 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32)
661 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64)
662 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128)
663 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256)
671 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
672 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
673 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
674 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
675 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
676 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
677 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
678 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
679 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
687 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT)
688 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT)
696 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED)
697 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED)
706 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP)
707 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1)
708 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2)
709 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3)
710 #define ADC_OVR_EVENT (ADC_FLAG_OVR)
711 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF)
715 #define ADC_AWD_EVENT ADC_AWD1_EVENT
720 #define ADC_IT_RDY ADC_IER_ADRDYIE
721 #define ADC_IT_EOSMP ADC_IER_EOSMPIE
722 #define ADC_IT_EOC ADC_IER_EOCIE
723 #define ADC_IT_EOS ADC_IER_EOSIE
724 #define ADC_IT_OVR ADC_IER_OVRIE
725 #define ADC_IT_JEOC ADC_IER_JEOCIE
726 #define ADC_IT_JEOS ADC_IER_JEOSIE
727 #define ADC_IT_AWD1 ADC_IER_AWD1IE
728 #define ADC_IT_AWD2 ADC_IER_AWD2IE
729 #define ADC_IT_AWD3 ADC_IER_AWD3IE
730 #define ADC_IT_JQOVF ADC_IER_JQOVFIE
732 #define ADC_IT_AWD ADC_IT_AWD1
741 #define ADC_FLAG_RDY ADC_ISR_ADRDY
742 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP
743 #define ADC_FLAG_EOC ADC_ISR_EOC
744 #define ADC_FLAG_EOS ADC_ISR_EOS
745 #define ADC_FLAG_OVR ADC_ISR_OVR
746 #define ADC_FLAG_JEOC ADC_ISR_JEOC
747 #define ADC_FLAG_JEOS ADC_ISR_JEOS
748 #define ADC_FLAG_AWD1 ADC_ISR_AWD1
749 #define ADC_FLAG_AWD2 ADC_ISR_AWD2
750 #define ADC_FLAG_AWD3 ADC_ISR_AWD3
751 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF
753 #define ADC_FLAG_AWD ADC_FLAG_AWD1
755 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
756  ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
757  ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)
759 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
760 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
761  ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
762  ADC_FLAG_JQOVF)
772 /* Private macro -------------------------------------------------------------*/
773 
777 /* Macro reserved for internal HAL driver usage, not intended to be used in */
778 /* code of final user. */
779 
785 #define ADC_GET_RESOLUTION(__HANDLE__) \
786  (LL_ADC_GetResolution((__HANDLE__)->Instance))
787 
793 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
794 
800 #define ADC_IS_ENABLE(__HANDLE__) \
801  (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
802  ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
803  ) ? SET : RESET)
804 
810 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
811  (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
812 
820 #define ADC_STATE_CLR_SET MODIFY_REG
821 
828 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
829  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
830 
836 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
837 
838 
844 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
845 
846 
852 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
853  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
854  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
855  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
856  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
857  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
858  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
859  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
860  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
861  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
862  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
863  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
864  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
865  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
866  ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
867 
873 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
874  ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
875  ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
876  ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
877 
883 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
884  ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
885 
891 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
892  ((__ALIGN__) == ADC_DATAALIGN_LEFT) )
893 
899 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
900  ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
901 
907 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
908  ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
909  ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
910  ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
911 
918 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
919  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
920  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
921  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
922  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
923  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
924  ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
925  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
926  ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
927  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
928  ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
929  ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
930  ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
931  ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
932  ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
933  ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
934  ((__REGTRIG__) == ADC_SOFTWARE_START) )
935 
941 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
942  ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
943 
949 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
950  ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
951 
957 #if defined(ADC_SMPR1_SMPPLUS)
958 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
959  ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
960  ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
961  ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
962  ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
963  ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
964  ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
965  ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
966  ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
967 #else
968 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
969  ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
970  ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
971  ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
972  ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
973  ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
974  ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
975  ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
976 #endif
977 
983 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
984  ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
985  ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
986  ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
987  ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
988  ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
989  ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
990  ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
991  ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
992  ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
993  ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
994  ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
995  ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
996  ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
997  ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
998  ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
999 
1005 /* Private constants ---------------------------------------------------------*/
1006 
1011 /* Fixed timeout values for ADC conversion (including sampling time) */
1012 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
1013 /* Maximum conversion time is 12.5 + Maximum sampling time */
1014 /* or 12.5 + 640.5 = 653 ADC clock cycles */
1015 /* Minimum ADC Clock frequency is 0.14 MHz */
1016 /* Maximum conversion time is */
1017 /* 653 / 0.14 MHz = 4.66 ms */
1018 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL)
1020 /* Delay for temperature sensor stabilization time. */
1021 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
1022 /* Unit: us */
1023 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
1024 
1029 /* Exported macro ------------------------------------------------------------*/
1030 
1034 /* Macro for internal HAL driver usage, and possibly can be used into code of */
1035 /* final user. */
1036 
1045 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1046 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1047  do{ \
1048  (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
1049  (__HANDLE__)->MspInitCallback = NULL; \
1050  (__HANDLE__)->MspDeInitCallback = NULL; \
1051  } while(0)
1052 #else
1053 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1054  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
1055 #endif
1056 
1075 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1076  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
1077 
1096 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
1097  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
1098 
1116 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
1117  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
1118 
1137 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
1138  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
1139 
1158 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
1159 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1160  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
1161 
1219 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1220  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
1221 
1271 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1272  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
1273 
1332 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1333  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
1334 
1407 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1408  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
1409 
1444 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1445  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
1446 
1447 #if defined(ADC_MULTIMODE_SUPPORT)
1448 
1461 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1462  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
1463 #endif
1464 
1475 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
1476  __LL_ADC_COMMON_INSTANCE((__ADCx__))
1477 
1495 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1496  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
1497 
1511 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1512  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
1513 
1532 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1533  __ADC_RESOLUTION_CURRENT__,\
1534  __ADC_RESOLUTION_TARGET__) \
1535  __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
1536  (__ADC_RESOLUTION_CURRENT__), \
1537  (__ADC_RESOLUTION_TARGET__))
1538 
1555 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1556  __ADC_DATA__,\
1557  __ADC_RESOLUTION__) \
1558  __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
1559  (__ADC_DATA__), \
1560  (__ADC_RESOLUTION__))
1561 
1587 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1588  __ADC_RESOLUTION__) \
1589  __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
1590  (__ADC_RESOLUTION__))
1591 
1637 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1638  __TEMPSENSOR_ADC_DATA__,\
1639  __ADC_RESOLUTION__) \
1640  __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
1641  (__TEMPSENSOR_ADC_DATA__), \
1642  (__ADC_RESOLUTION__))
1643 
1688 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1689  __TEMPSENSOR_TYP_CALX_V__,\
1690  __TEMPSENSOR_CALX_TEMP__,\
1691  __VREFANALOG_VOLTAGE__,\
1692  __TEMPSENSOR_ADC_DATA__,\
1693  __ADC_RESOLUTION__) \
1694  __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
1695  (__TEMPSENSOR_TYP_CALX_V__), \
1696  (__TEMPSENSOR_CALX_TEMP__), \
1697  (__VREFANALOG_VOLTAGE__), \
1698  (__TEMPSENSOR_ADC_DATA__), \
1699  (__ADC_RESOLUTION__))
1700 
1709 /* Include ADC HAL Extended module */
1710 #include "stm32l4xx_hal_adc_ex.h"
1711 
1712 /* Exported functions --------------------------------------------------------*/
1721 /* Initialization and de-initialization functions ****************************/
1722 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
1723 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
1724 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
1725 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
1726 
1727 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1728 /* Callbacks Register/UnRegister functions ***********************************/
1729 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
1730  pADC_CallbackTypeDef pCallback);
1731 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
1732 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1733 
1741 /* IO operation functions *****************************************************/
1742 
1743 /* Blocking mode: Polling */
1744 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
1745 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
1746 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
1747 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
1748 
1749 /* Non-blocking mode: Interruption */
1750 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
1751 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
1752 
1753 /* Non-blocking mode: DMA */
1754 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
1755 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
1756 
1757 /* ADC retrieve conversion value intended to be used with polling or interruption */
1758 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
1759 
1760 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
1761 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
1762 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
1763 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
1764 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
1765 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
1774 /* Peripheral Control functions ***********************************************/
1775 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
1776 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
1777 
1782 /* Peripheral State functions *************************************************/
1786 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
1787 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
1788 
1797 /* Private functions -----------------------------------------------------------*/
1801 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
1802 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
1803 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
1804 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
1805 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
1806 void ADC_DMAError(DMA_HandleTypeDef *hdma);
1807 
1820 #ifdef __cplusplus
1821 }
1822 #endif
1823 
1824 
1825 #endif /* STM32L4xx_HAL_ADC_H */
1826 
1827 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_ADC_Stop_IT
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode)...
Definition: stm32l4xx_hal_adc.c:1935
ADC_ChannelConfTypeDef::OffsetNumber
uint32_t OffsetNumber
Definition: stm32l4xx_hal_adc.h:235
ADC_InitTypeDef::Oversampling
ADC_OversamplingTypeDef Oversampling
Definition: stm32l4xx_hal_adc.h:179
ADC_ChannelConfTypeDef::Channel
uint32_t Channel
Definition: stm32l4xx_hal_adc.h:203
ADC_ChannelConfTypeDef::SamplingTime
uint32_t SamplingTime
Definition: stm32l4xx_hal_adc.h:212
HAL_ADC_CONVERSION_COMPLETE_CB_ID
Definition: stm32l4xx_hal_adc.h:393
HAL_ADC_PollForConversion
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
Definition: stm32l4xx_hal_adc.c:1404
HAL_ADC_AnalogWDGConfig
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configure the analog watchdog.
Definition: stm32l4xx_hal_adc.c:2941
ADC_InitTypeDef::ExternalTrigConv
uint32_t ExternalTrigConv
Definition: stm32l4xx_hal_adc.h:150
ADC_OversamplingTypeDef::OversamplingStopReset
uint32_t OversamplingStopReset
Definition: stm32l4xx_hal_adc.h:61
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32l4xx_hal_dma.h:113
HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID
Definition: stm32l4xx_hal_adc.h:400
HAL_ADC_IRQHandler
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
Handle ADC interrupt request.
Definition: stm32l4xx_hal_adc.c:2231
ADC_InitTypeDef::Overrun
uint32_t Overrun
Definition: stm32l4xx_hal_adc.h:164
stm32l4xx_ll_adc.h
Header file of ADC LL module.
ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group.
Definition: stm32l4xx_hal_adc.h:201
HAL_ADC_CallbackIDTypeDef
HAL_ADC_CallbackIDTypeDef
HAL ADC Callback ID enumeration definition.
Definition: stm32l4xx_hal_adc.h:391
ADC_AnalogWDGConfTypeDef::ITMode
FunctionalState ITMode
Definition: stm32l4xx_hal_adc.h:271
HAL_ADC_Init
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
Initialize the ADC peripheral and regular group according to parameters specified in structure "ADC_I...
Definition: stm32l4xx_hal_adc.c:402
ADC_InjectionConfigTypeDef
ADC group injected contexts queue configuration.
Definition: stm32l4xx_hal_adc.h:299
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID
Definition: stm32l4xx_hal_adc.h:397
ADC_DMAConvCplt
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
Definition: stm32l4xx_hal_adc.c:3492
endif::Init
ADC_InitTypeDef Init
Definition: stm32l4xx_hal_adc.h:366
HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID
Definition: stm32l4xx_hal_adc.h:398
HAL_ADC_ErrorCallback
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
ADC error callback in non-blocking mode (ADC conversion with interruption or transfer by DMA)...
Definition: stm32l4xx_hal_adc.c:2653
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_ADC_DeInit
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the...
Definition: stm32l4xx_hal_adc.c:707
HAL_ADC_MspInit
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
Initialize the ADC MSP.
Definition: stm32l4xx_hal_adc.c:909
ADC_DMAError
void ADC_DMAError(DMA_HandleTypeDef *hdma)
DMA error callback.
Definition: stm32l4xx_hal_adc.c:3588
ADC_InitTypeDef::ExternalTrigConvEdge
uint32_t ExternalTrigConvEdge
Definition: stm32l4xx_hal_adc.h:155
ADC_Enable
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
Enable the selected ADC.
Definition: stm32l4xx_hal_adc.c:3367
ADC_InitTypeDef::OversamplingMode
FunctionalState OversamplingMode
Definition: stm32l4xx_hal_adc.h:175
ADC_InjectionConfigTypeDef::ChannelCount
uint32_t ChannelCount
Definition: stm32l4xx_hal_adc.h:305
ADC_InitTypeDef::NbrOfDiscConversion
uint32_t NbrOfDiscConversion
Definition: stm32l4xx_hal_adc.h:146
ADC_InitTypeDef::DiscontinuousConvMode
FunctionalState DiscontinuousConvMode
Definition: stm32l4xx_hal_adc.h:140
ADC_AnalogWDGConfTypeDef::Channel
uint32_t Channel
Definition: stm32l4xx_hal_adc.h:266
ADC_AnalogWDGConfTypeDef::WatchdogNumber
uint32_t WatchdogNumber
Definition: stm32l4xx_hal_adc.h:256
ADC_InitTypeDef::Resolution
uint32_t Resolution
Definition: stm32l4xx_hal_adc.h:100
ADC_AnalogWDGConfTypeDef::HighThreshold
uint32_t HighThreshold
Definition: stm32l4xx_hal_adc.h:274
HAL_ADC_Start_DMA
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enable ADC, start conversion of regular group and transfer result through DMA.
Definition: stm32l4xx_hal_adc.c:1988
endif::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32l4xx_hal_adc.h:370
ADC_HandleTypeDef
struct __ADC_HandleTypeDef else typedef struct endif ADC_HandleTypeDef
ADC handle Structure definition.
HAL_ADC_Start
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group.
Definition: stm32l4xx_hal_adc.c:1215
HAL_ADC_Stop_DMA
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode)...
Definition: stm32l4xx_hal_adc.c:2129
ADC_InitTypeDef
Structure definition of ADC instance and ADC group regular.
Definition: stm32l4xx_hal_adc.h:87
ADC_AnalogWDGConfTypeDef::WatchdogMode
uint32_t WatchdogMode
Definition: stm32l4xx_hal_adc.h:261
ADC_ChannelConfTypeDef::Offset
uint32_t Offset
Definition: stm32l4xx_hal_adc.h:239
ADC_AnalogWDGConfTypeDef::LowThreshold
uint32_t LowThreshold
Definition: stm32l4xx_hal_adc.h:284
HAL_ADC_ConvCpltCallback
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
Conversion complete callback in non-blocking mode.
Definition: stm32l4xx_hal_adc.c:2601
ADC_DMAHalfConvCplt
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
Definition: stm32l4xx_hal_adc.c:3570
HAL_ADC_GetError
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
Return the ADC error code.
Definition: stm32l4xx_hal_adc.c:3207
endif::DMA_Handle
DMA_HandleTypeDef * DMA_Handle
Definition: stm32l4xx_hal_adc.h:367
ADC_ChannelConfTypeDef::Rank
uint32_t Rank
Definition: stm32l4xx_hal_adc.h:207
pADC_CallbackTypeDef
void(* pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc)
HAL ADC Callback pointer definition.
Definition: stm32l4xx_hal_adc.h:409
ADC_AnalogWDGConfTypeDef
Structure definition of ADC analog watchdog.
Definition: stm32l4xx_hal_adc.h:254
ADC_InitTypeDef::DMAContinuousRequests
FunctionalState DMAContinuousRequests
Definition: stm32l4xx_hal_adc.h:159
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID
Definition: stm32l4xx_hal_adc.h:395
ADC_ChannelConfTypeDef::SingleDiff
uint32_t SingleDiff
Definition: stm32l4xx_hal_adc.h:223
endif::State
__IO uint32_t State
Definition: stm32l4xx_hal_adc.h:369
stm32l4xx_hal_adc_ex.h
Header file of ADC HAL extended module.
ADC_OversamplingTypeDef
ADC group regular oversampling structure definition.
Definition: stm32l4xx_hal_adc.h:50
ADC_InitTypeDef::DataAlign
uint32_t DataAlign
Definition: stm32l4xx_hal_adc.h:103
ADC_InitTypeDef::ContinuousConvMode
FunctionalState ContinuousConvMode
Definition: stm32l4xx_hal_adc.h:130
HAL_ADC_Stop
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode)...
Definition: stm32l4xx_hal_adc.c:1350
ADC_InitTypeDef::NbrOfConversion
uint32_t NbrOfConversion
Definition: stm32l4xx_hal_adc.h:134
HAL_ADC_MSPINIT_CB_ID
Definition: stm32l4xx_hal_adc.h:402
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32l4xx_hal_def.h:50
HAL_ADC_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_adc.h:403
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID
Definition: stm32l4xx_hal_adc.h:399
HAL_ADC_RegisterCallback
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
Register a User ADC Callback To be used instead of the weak predefined callback.
Definition: stm32l4xx_hal_adc.c:960
ADC_OversamplingTypeDef::Ratio
uint32_t Ratio
Definition: stm32l4xx_hal_adc.h:52
ADC_ConversionStop
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
Stop ADC conversion.
Definition: stm32l4xx_hal_adc.c:3237
ADC_InitTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32l4xx_hal_adc.h:89
ADC_Disable
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
Disable the selected ADC.
Definition: stm32l4xx_hal_adc.c:3434
HAL_ADC_GetValue
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
Definition: stm32l4xx_hal_adc.c:2214
HAL_ADC_ConfigChannel
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configure a channel to be assigned to ADC group regular.
Definition: stm32l4xx_hal_adc.c:2699
endif::InjectionConfig
ADC_InjectionConfigTypeDef InjectionConfig
Definition: stm32l4xx_hal_adc.h:371
HAL_ADC_GetState
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
Return the ADC handle state.
Definition: stm32l4xx_hal_adc.c:3193
HAL_ADC_ConvHalfCpltCallback
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non-blocking mode.
Definition: stm32l4xx_hal_adc.c:2616
HAL_ADC_CONVERSION_HALF_CB_ID
Definition: stm32l4xx_hal_adc.h:394
ADC_InitTypeDef::EOCSelection
uint32_t EOCSelection
Definition: stm32l4xx_hal_adc.h:115
ADC_InitTypeDef::LowPowerAutoWait
FunctionalState LowPowerAutoWait
Definition: stm32l4xx_hal_adc.h:118
endif
ADC handle Structure definition.
Definition: stm32l4xx_hal_adc.h:360
ADC_OversamplingTypeDef::RightBitShift
uint32_t RightBitShift
Definition: stm32l4xx_hal_adc.h:55
HAL_ADC_UnRegisterCallback
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
Unregister a ADC Callback ADC callback is redirected to the weak predefined callback.
Definition: stm32l4xx_hal_adc.c:1084
HAL_ADC_LevelOutOfWindowCallback
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
Analog watchdog 1 callback in non-blocking mode.
Definition: stm32l4xx_hal_adc.c:2631
HAL_ADC_PollForEvent
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for ADC event.
Definition: stm32l4xx_hal_adc.c:1583
endif::Instance
ADC_TypeDef * Instance
Definition: stm32l4xx_hal_adc.h:365
ADC_OversamplingTypeDef::TriggeredMode
uint32_t TriggeredMode
Definition: stm32l4xx_hal_adc.h:58
ADC_InitTypeDef::DFSDMConfig
uint32_t DFSDMConfig
Definition: stm32l4xx_hal_adc.h:183
HAL_ADC_END_OF_SAMPLING_CB_ID
Definition: stm32l4xx_hal_adc.h:401
HAL_ADC_Start_IT
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
Enable ADC, start conversion of regular group with interruption.
Definition: stm32l4xx_hal_adc.c:1728
HAL_ADC_MspDeInit
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
DeInitialize the ADC MSP.
Definition: stm32l4xx_hal_adc.c:926
ADC_InitTypeDef::ScanConvMode
uint32_t ScanConvMode
Definition: stm32l4xx_hal_adc.h:107
ADC_InjectionConfigTypeDef::ContextQueue
uint32_t ContextQueue
Definition: stm32l4xx_hal_adc.h:301
HAL_ADC_ERROR_CB_ID
Definition: stm32l4xx_hal_adc.h:396
else
else
Definition: stm32l4xx_ll_lpuart.h:1488
endif::Lock
HAL_LockTypeDef Lock
Definition: stm32l4xx_hal_adc.h:368