STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_dsi.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_HAL_DSI_H
22 #define STM32L4xx_HAL_DSI_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
31 #if defined(DSI)
32 
42 /* Exported types ------------------------------------------------------------*/
46 typedef struct
47 {
48  uint32_t AutomaticClockLaneControl;
51  uint32_t TXEscapeCkdiv;
54  uint32_t NumberOfLanes;
57 } DSI_InitTypeDef;
58 
62 typedef struct
63 {
64  uint32_t PLLNDIV;
67  uint32_t PLLIDF;
70  uint32_t PLLODF;
73 } DSI_PLLInitTypeDef;
74 
78 typedef struct
79 {
80  uint32_t VirtualChannelID;
82  uint32_t ColorCoding;
85  uint32_t LooselyPacked;
89  uint32_t Mode;
92  uint32_t PacketSize;
94  uint32_t NumberOfChunks;
96  uint32_t NullPacketSize;
98  uint32_t HSPolarity;
101  uint32_t VSPolarity;
104  uint32_t DEPolarity;
107  uint32_t HorizontalSyncActive;
109  uint32_t HorizontalBackPorch;
111  uint32_t HorizontalLine;
113  uint32_t VerticalSyncActive;
115  uint32_t VerticalBackPorch;
117  uint32_t VerticalFrontPorch;
119  uint32_t VerticalActive;
121  uint32_t LPCommandEnable;
124  uint32_t LPLargestPacketSize;
127  uint32_t LPVACTLargestPacketSize;
130  uint32_t LPHorizontalFrontPorchEnable;
133  uint32_t LPHorizontalBackPorchEnable;
136  uint32_t LPVerticalActiveEnable;
139  uint32_t LPVerticalFrontPorchEnable;
142  uint32_t LPVerticalBackPorchEnable;
145  uint32_t LPVerticalSyncActiveEnable;
148  uint32_t FrameBTAAcknowledgeEnable;
151 } DSI_VidCfgTypeDef;
152 
156 typedef struct
157 {
158  uint32_t VirtualChannelID;
160  uint32_t ColorCoding;
163  uint32_t CommandSize;
166  uint32_t TearingEffectSource;
169  uint32_t TearingEffectPolarity;
172  uint32_t HSPolarity;
175  uint32_t VSPolarity;
178  uint32_t DEPolarity;
181  uint32_t VSyncPol;
184  uint32_t AutomaticRefresh;
187  uint32_t TEAcknowledgeRequest;
190 } DSI_CmdCfgTypeDef;
191 
195 typedef struct
196 {
197  uint32_t LPGenShortWriteNoP;
200  uint32_t LPGenShortWriteOneP;
203  uint32_t LPGenShortWriteTwoP;
206  uint32_t LPGenShortReadNoP;
209  uint32_t LPGenShortReadOneP;
212  uint32_t LPGenShortReadTwoP;
215  uint32_t LPGenLongWrite;
218  uint32_t LPDcsShortWriteNoP;
221  uint32_t LPDcsShortWriteOneP;
224  uint32_t LPDcsShortReadNoP;
227  uint32_t LPDcsLongWrite;
230  uint32_t LPMaxReadPacket;
233  uint32_t AcknowledgeRequest;
236 } DSI_LPCmdTypeDef;
237 
241 typedef struct
242 {
243  uint32_t ClockLaneHS2LPTime;
246  uint32_t ClockLaneLP2HSTime;
249  uint32_t DataLaneHS2LPTime;
252  uint32_t DataLaneLP2HSTime;
255  uint32_t DataLaneMaxReadTime;
257  uint32_t StopWaitTime;
260 } DSI_PHY_TimerTypeDef;
261 
265 typedef struct
266 {
267  uint32_t TimeoutCkdiv;
269  uint32_t HighSpeedTransmissionTimeout;
271  uint32_t LowPowerReceptionTimeout;
273  uint32_t HighSpeedReadTimeout;
275  uint32_t LowPowerReadTimeout;
277  uint32_t HighSpeedWriteTimeout;
279  uint32_t HighSpeedWritePrespMode;
282  uint32_t LowPowerWriteTimeout;
284  uint32_t BTATimeout;
286 } DSI_HOST_TimeoutTypeDef;
287 
291 typedef enum
292 {
293  HAL_DSI_STATE_RESET = 0x00U,
294  HAL_DSI_STATE_READY = 0x01U,
295  HAL_DSI_STATE_ERROR = 0x02U,
296  HAL_DSI_STATE_BUSY = 0x03U,
297  HAL_DSI_STATE_TIMEOUT = 0x04U
298 } HAL_DSI_StateTypeDef;
299 
303 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
304 typedef struct __DSI_HandleTypeDef
305 #else
306 typedef struct
307 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
308 {
309  DSI_TypeDef *Instance;
310  DSI_InitTypeDef Init;
311  HAL_LockTypeDef Lock;
312  __IO HAL_DSI_StateTypeDef State;
313  __IO uint32_t ErrorCode;
314  uint32_t ErrorMsk;
316 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
317  void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);
318  void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);
319  void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);
321  void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);
322  void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);
324 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
325 
326 } DSI_HandleTypeDef;
327 
328 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
329 
332 typedef enum
333 {
334  HAL_DSI_MSPINIT_CB_ID = 0x00U,
335  HAL_DSI_MSPDEINIT_CB_ID = 0x01U,
337  HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U,
338  HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U,
339  HAL_DSI_ERROR_CB_ID = 0x04U
341 } HAL_DSI_CallbackIDTypeDef;
342 
346 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);
348 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
349 
350 /* Exported constants --------------------------------------------------------*/
357 #define DSI_ENTER_IDLE_MODE 0x39U
358 #define DSI_ENTER_INVERT_MODE 0x21U
359 #define DSI_ENTER_NORMAL_MODE 0x13U
360 #define DSI_ENTER_PARTIAL_MODE 0x12U
361 #define DSI_ENTER_SLEEP_MODE 0x10U
362 #define DSI_EXIT_IDLE_MODE 0x38U
363 #define DSI_EXIT_INVERT_MODE 0x20U
364 #define DSI_EXIT_SLEEP_MODE 0x11U
365 #define DSI_GET_3D_CONTROL 0x3FU
366 #define DSI_GET_ADDRESS_MODE 0x0BU
367 #define DSI_GET_BLUE_CHANNEL 0x08U
368 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
369 #define DSI_GET_DISPLAY_MODE 0x0DU
370 #define DSI_GET_GREEN_CHANNEL 0x07U
371 #define DSI_GET_PIXEL_FORMAT 0x0CU
372 #define DSI_GET_POWER_MODE 0x0AU
373 #define DSI_GET_RED_CHANNEL 0x06U
374 #define DSI_GET_SCANLINE 0x45U
375 #define DSI_GET_SIGNAL_MODE 0x0EU
376 #define DSI_NOP 0x00U
377 #define DSI_READ_DDB_CONTINUE 0xA8U
378 #define DSI_READ_DDB_START 0xA1U
379 #define DSI_READ_MEMORY_CONTINUE 0x3EU
380 #define DSI_READ_MEMORY_START 0x2EU
381 #define DSI_SET_3D_CONTROL 0x3DU
382 #define DSI_SET_ADDRESS_MODE 0x36U
383 #define DSI_SET_COLUMN_ADDRESS 0x2AU
384 #define DSI_SET_DISPLAY_OFF 0x28U
385 #define DSI_SET_DISPLAY_ON 0x29U
386 #define DSI_SET_GAMMA_CURVE 0x26U
387 #define DSI_SET_PAGE_ADDRESS 0x2BU
388 #define DSI_SET_PARTIAL_COLUMNS 0x31U
389 #define DSI_SET_PARTIAL_ROWS 0x30U
390 #define DSI_SET_PIXEL_FORMAT 0x3AU
391 #define DSI_SET_SCROLL_AREA 0x33U
392 #define DSI_SET_SCROLL_START 0x37U
393 #define DSI_SET_TEAR_OFF 0x34U
394 #define DSI_SET_TEAR_ON 0x35U
395 #define DSI_SET_TEAR_SCANLINE 0x44U
396 #define DSI_SET_VSYNC_TIMING 0x40U
397 #define DSI_SOFT_RESET 0x01U
398 #define DSI_WRITE_LUT 0x2DU
399 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
400 #define DSI_WRITE_MEMORY_START 0x2CU
401 
408 #define DSI_VID_MODE_NB_PULSES 0U
409 #define DSI_VID_MODE_NB_EVENTS 1U
410 #define DSI_VID_MODE_BURST 2U
411 
418 #define DSI_COLOR_MODE_FULL 0x00000000U
419 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
420 
427 #define DSI_DISPLAY_ON 0x00000000U
428 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
429 
436 #define DSI_LP_COMMAND_DISABLE 0x00000000U
437 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
438 
445 #define DSI_LP_HFP_DISABLE 0x00000000U
446 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
447 
454 #define DSI_LP_HBP_DISABLE 0x00000000U
455 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
456 
463 #define DSI_LP_VACT_DISABLE 0x00000000U
464 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
465 
472 #define DSI_LP_VFP_DISABLE 0x00000000U
473 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
474 
481 #define DSI_LP_VBP_DISABLE 0x00000000U
482 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
483 
490 #define DSI_LP_VSYNC_DISABLE 0x00000000U
491 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
492 
499 #define DSI_FBTAA_DISABLE 0x00000000U
500 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
501 
508 #define DSI_TE_DSILINK 0x00000000U
509 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
510 
517 #define DSI_TE_RISING_EDGE 0x00000000U
518 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
519 
526 #define DSI_VSYNC_FALLING 0x00000000U
527 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
528 
535 #define DSI_AR_DISABLE 0x00000000U
536 #define DSI_AR_ENABLE DSI_WCFGR_AR
537 
544 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
545 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
546 
553 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
554 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
555 
562 #define DSI_LP_GSW0P_DISABLE 0x00000000U
563 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
564 
571 #define DSI_LP_GSW1P_DISABLE 0x00000000U
572 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
573 
580 #define DSI_LP_GSW2P_DISABLE 0x00000000U
581 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
582 
589 #define DSI_LP_GSR0P_DISABLE 0x00000000U
590 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
591 
598 #define DSI_LP_GSR1P_DISABLE 0x00000000U
599 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
600 
607 #define DSI_LP_GSR2P_DISABLE 0x00000000U
608 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
609 
616 #define DSI_LP_GLW_DISABLE 0x00000000U
617 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
618 
625 #define DSI_LP_DSW0P_DISABLE 0x00000000U
626 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
627 
634 #define DSI_LP_DSW1P_DISABLE 0x00000000U
635 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
636 
643 #define DSI_LP_DSR0P_DISABLE 0x00000000U
644 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
645 
652 #define DSI_LP_DLW_DISABLE 0x00000000U
653 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
654 
661 #define DSI_LP_MRDP_DISABLE 0x00000000U
662 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
663 
670 #define DSI_HS_PM_DISABLE 0x00000000U
671 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
672 
680 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
681 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
682 
689 #define DSI_ONE_DATA_LANE 0U
690 #define DSI_TWO_DATA_LANES 1U
691 
698 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
699 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
700 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
701 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
702 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
703 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
704  DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
705  DSI_FLOW_CONTROL_EOTP_TX)
706 
713 #define DSI_RGB565 0x00000000U
714 #define DSI_RGB666 0x00000003U
715 #define DSI_RGB888 0x00000005U
716 
723 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
724 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
725 
732 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
733 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
734 
741 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
742 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
743 
750 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
751 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
752 
759 #define DSI_PLL_IN_DIV1 0x00000001U
760 #define DSI_PLL_IN_DIV2 0x00000002U
761 #define DSI_PLL_IN_DIV3 0x00000003U
762 #define DSI_PLL_IN_DIV4 0x00000004U
763 #define DSI_PLL_IN_DIV5 0x00000005U
764 #define DSI_PLL_IN_DIV6 0x00000006U
765 #define DSI_PLL_IN_DIV7 0x00000007U
766 
773 #define DSI_PLL_OUT_DIV1 0x00000000U
774 #define DSI_PLL_OUT_DIV2 0x00000001U
775 #define DSI_PLL_OUT_DIV4 0x00000002U
776 #define DSI_PLL_OUT_DIV8 0x00000003U
777 
784 #define DSI_FLAG_TE DSI_WISR_TEIF
785 #define DSI_FLAG_ER DSI_WISR_ERIF
786 #define DSI_FLAG_BUSY DSI_WISR_BUSY
787 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
788 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
789 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
790 #define DSI_FLAG_RRS DSI_WISR_RRS
791 #define DSI_FLAG_RR DSI_WISR_RRIF
792 
799 #define DSI_IT_TE DSI_WIER_TEIE
800 #define DSI_IT_ER DSI_WIER_ERIE
801 #define DSI_IT_PLLL DSI_WIER_PLLLIE
802 #define DSI_IT_PLLU DSI_WIER_PLLUIE
803 #define DSI_IT_RR DSI_WIER_RRIE
804 
811 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U
812 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U
813 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U
814 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U
815 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U
823 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U
824 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U
832 #define DSI_DCS_SHORT_PKT_READ 0x00000006U
833 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U
834 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U
835 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U
843 #define HAL_DSI_ERROR_NONE 0U
844 #define HAL_DSI_ERROR_ACK 0x00000001U
845 #define HAL_DSI_ERROR_PHY 0x00000002U
846 #define HAL_DSI_ERROR_TX 0x00000004U
847 #define HAL_DSI_ERROR_RX 0x00000008U
848 #define HAL_DSI_ERROR_ECC 0x00000010U
849 #define HAL_DSI_ERROR_CRC 0x00000020U
850 #define HAL_DSI_ERROR_PSE 0x00000040U
851 #define HAL_DSI_ERROR_EOT 0x00000080U
852 #define HAL_DSI_ERROR_OVF 0x00000100U
853 #define HAL_DSI_ERROR_GEN 0x00000200U
854 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
855 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U
856 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
857 
864 #define DSI_CLOCK_LANE 0x00000000U
865 #define DSI_DATA_LANES 0x00000001U
866 
873 #define DSI_SLEW_RATE_HSTX 0x00000000U
874 #define DSI_SLEW_RATE_LPTX 0x00000001U
875 #define DSI_HS_DELAY 0x00000002U
876 
883 #define DSI_SWAP_LANE_PINS 0x00000000U
884 #define DSI_INVERT_HS_SIGNAL 0x00000001U
885 
892 #define DSI_CLK_LANE 0x00000000U
893 #define DSI_DATA_LANE0 0x00000001U
894 #define DSI_DATA_LANE1 0x00000002U
895 
902 #define DSI_TCLK_POST 0x00000000U
903 #define DSI_TLPX_CLK 0x00000001U
904 #define DSI_THS_EXIT 0x00000002U
905 #define DSI_TLPX_DATA 0x00000003U
906 #define DSI_THS_ZERO 0x00000004U
907 #define DSI_THS_TRAIL 0x00000005U
908 #define DSI_THS_PREPARE 0x00000006U
909 #define DSI_TCLK_ZERO 0x00000007U
910 #define DSI_TCLK_PREPARE 0x00000008U
911 
919 /* Exported macros -----------------------------------------------------------*/
929 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
930 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
931  (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
932  (__HANDLE__)->MspInitCallback = NULL; \
933  (__HANDLE__)->MspDeInitCallback = NULL; \
934  } while(0)
935 #else
936 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
937 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
938 
944 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
945  __IO uint32_t tmpreg = 0x00U; \
946  SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
947  /* Delay after an DSI Host enabling */ \
948  tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
949  UNUSED(tmpreg); \
950  } while(0U)
951 
957 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
958  __IO uint32_t tmpreg = 0x00U; \
959  CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
960  /* Delay after an DSI Host disabling */ \
961  tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
962  UNUSED(tmpreg); \
963  } while(0U)
964 
970 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
971  __IO uint32_t tmpreg = 0x00U; \
972  SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
973  /* Delay after an DSI warpper enabling */ \
974  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
975  UNUSED(tmpreg); \
976  } while(0U)
977 
983 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
984  __IO uint32_t tmpreg = 0x00U; \
985  CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
986  /* Delay after an DSI warpper disabling*/ \
987  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
988  UNUSED(tmpreg); \
989  } while(0U)
990 
996 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
997  __IO uint32_t tmpreg = 0x00U; \
998  SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
999  /* Delay after an DSI PLL enabling */ \
1000  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1001  UNUSED(tmpreg); \
1002  } while(0U)
1003 
1009 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
1010  __IO uint32_t tmpreg = 0x00U; \
1011  CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1012  /* Delay after an DSI PLL disabling */ \
1013  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1014  UNUSED(tmpreg); \
1015  } while(0U)
1016 
1022 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
1023  __IO uint32_t tmpreg = 0x00U; \
1024  SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1025  /* Delay after an DSI regulator enabling */ \
1026  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1027  UNUSED(tmpreg); \
1028  } while(0U)
1029 
1035 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
1036  __IO uint32_t tmpreg = 0x00U; \
1037  CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1038  /* Delay after an DSI regulator disabling */ \
1039  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1040  UNUSED(tmpreg); \
1041  } while(0U)
1042 
1058 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1059 
1072 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1073 
1086 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
1087 
1100 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1101 
1114 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1115 
1120 /* Exported functions --------------------------------------------------------*/
1124 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1125 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1126 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1127 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1128 
1129 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1130 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1131 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1132 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1133 
1134 /* Callbacks Register/UnRegister functions ***********************************/
1135 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
1136 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
1137  pDSI_CallbackTypeDef pCallback);
1138 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
1139 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
1140 
1141 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1142 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1143 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1144 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1145 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1146 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1147 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1148 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1149 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1150 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1151 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1152 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1153 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1154  uint32_t ChannelID,
1155  uint32_t Mode,
1156  uint32_t Param1,
1157  uint32_t Param2);
1158 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1159  uint32_t ChannelID,
1160  uint32_t Mode,
1161  uint32_t NbParams,
1162  uint32_t Param1,
1163  uint8_t *ParametersTable);
1164 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1165  uint32_t ChannelNbr,
1166  uint8_t *Array,
1167  uint32_t Size,
1168  uint32_t Mode,
1169  uint32_t DCSCmd,
1170  uint8_t *ParametersTable);
1171 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1172 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1173 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1174 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1175 
1176 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1177 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1178 
1179 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
1180  uint32_t Value);
1181 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1182 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1183 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
1184  FunctionalState State);
1185 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
1186  uint32_t Value);
1187 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1188 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1189 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1190 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1191 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1192 
1193 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1194 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1195 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1200 /* Private types -------------------------------------------------------------*/
1209 /* Private defines -----------------------------------------------------------*/
1218 /* Private variables ---------------------------------------------------------*/
1227 /* Private constants ---------------------------------------------------------*/
1231 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U)
1236 /* Private macros ------------------------------------------------------------*/
1237 
1240 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1241 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1242  ((IDF) == DSI_PLL_IN_DIV2) || \
1243  ((IDF) == DSI_PLL_IN_DIV3) || \
1244  ((IDF) == DSI_PLL_IN_DIV4) || \
1245  ((IDF) == DSI_PLL_IN_DIV5) || \
1246  ((IDF) == DSI_PLL_IN_DIV6) || \
1247  ((IDF) == DSI_PLL_IN_DIV7))
1248 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1249  ((ODF) == DSI_PLL_OUT_DIV2) || \
1250  ((ODF) == DSI_PLL_OUT_DIV4) || \
1251  ((ODF) == DSI_PLL_OUT_DIV8))
1252 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1253 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1254 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1255 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1256 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1257 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1258 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1259 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1260 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1261  ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1262  ((VideoModeType) == DSI_VID_MODE_BURST))
1263 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1264 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1265 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1266 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1267 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1268 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1269 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1270 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1271 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1272 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1273 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1274 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1275 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1276 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1277 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1278 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1279 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1280 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1281 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1282 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1283 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1284 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1285 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1286 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1287 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1288 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1289 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1290 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1291 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1292  ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1293  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1294  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1295  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1296 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1297  ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1298 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1299  ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1300  ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1301  ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1302 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1303 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1304 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1305 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1306 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1307  ((Timing) == DSI_TLPX_CLK ) || \
1308  ((Timing) == DSI_THS_EXIT ) || \
1309  ((Timing) == DSI_TLPX_DATA ) || \
1310  ((Timing) == DSI_THS_ZERO ) || \
1311  ((Timing) == DSI_THS_TRAIL ) || \
1312  ((Timing) == DSI_THS_PREPARE ) || \
1313  ((Timing) == DSI_TCLK_ZERO ) || \
1314  ((Timing) == DSI_TCLK_PREPARE))
1315 
1320 /* Private functions prototypes ----------------------------------------------*/
1329 /* Private functions ---------------------------------------------------------*/
1345 #endif /* DSI */
1346 
1347 #ifdef __cplusplus
1348 }
1349 #endif
1350 
1351 #endif /* STM32L4xx_HAL_DSI_H */
1352 
1353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
endif::ErrorMsk
uint32_t ErrorMsk
Definition: stm32l4xx_hal_dsi.h:314
HAL_DSI_ForceRXLowPower
HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
Force LP Receiver in Low-Power Mode.
Definition: stm32l4xx_hal_dsi.c:2575
DSI_PLLInitTypeDef
DSI PLL Clock structure definition.
Definition: stm32l4xx_hal_dsi.h:62
DSI_HOST_TimeoutTypeDef::HighSpeedReadTimeout
uint32_t HighSpeedReadTimeout
Definition: stm32l4xx_hal_dsi.h:273
DSI_PHY_TimerTypeDef::StopWaitTime
uint32_t StopWaitTime
Definition: stm32l4xx_hal_dsi.h:257
HAL_DSI_SetPullDown
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
Enable a pull-down on the lanes to prevent from floating states when unused.
Definition: stm32l4xx_hal_dsi.c:2625
DSI_VidCfgTypeDef::VerticalFrontPorch
uint32_t VerticalFrontPorch
Definition: stm32l4xx_hal_dsi.h:117
HAL_DSI_UnRegisterCallback
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
Unregister a DSI Callback DSI callabck is redirected to the weak predefined callback.
Definition: stm32l4xx_hal_dsi.c:712
DSI_CmdCfgTypeDef::VSyncPol
uint32_t VSyncPol
Definition: stm32l4xx_hal_dsi.h:181
DSI_CmdCfgTypeDef
DSI Adapted command mode configuration.
Definition: stm32l4xx_hal_dsi.h:156
DSI_CmdCfgTypeDef::TearingEffectPolarity
uint32_t TearingEffectPolarity
Definition: stm32l4xx_hal_dsi.h:169
HAL_DSI_ConfigErrorMonitor
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
Enable the error monitor flags.
Definition: stm32l4xx_hal_dsi.c:496
DSI_PHY_TimerTypeDef::DataLaneMaxReadTime
uint32_t DataLaneMaxReadTime
Definition: stm32l4xx_hal_dsi.h:255
DSI_VidCfgTypeDef::LPVerticalFrontPorchEnable
uint32_t LPVerticalFrontPorchEnable
Definition: stm32l4xx_hal_dsi.h:139
State
hrtc State
Definition: stm32l4xx_hal_rtc_ex.c:800
HAL_DSI_DeInit
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
De-initializes the DSI peripheral registers to their default reset values.
Definition: stm32l4xx_hal_dsi.c:438
HAL_DSI_Refresh
HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
Refresh the display in command mode.
Definition: stm32l4xx_hal_dsi.c:1498
HAL_DSI_MSPINIT_CB_ID
Definition: stm32l4xx_hal_dsi.h:334
DSI_HOST_TimeoutTypeDef
DSI HOST Timeouts definition.
Definition: stm32l4xx_hal_dsi.h:265
HAL_DSI_EnterULPMData
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running (only data lanes are in ULPM) ...
Definition: stm32l4xx_hal_dsi.c:1800
HAL_DSI_EndOfRefreshCallback
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
End of Refresh DSI callback.
Definition: stm32l4xx_hal_dsi.c:945
DSI_HOST_TimeoutTypeDef::LowPowerReadTimeout
uint32_t LowPowerReadTimeout
Definition: stm32l4xx_hal_dsi.h:275
DSI_LPCmdTypeDef::LPGenShortReadTwoP
uint32_t LPGenShortReadTwoP
Definition: stm32l4xx_hal_dsi.h:212
HAL_DSI_STATE_READY
Definition: stm32l4xx_hal_dsi.h:294
DSI_LPCmdTypeDef::LPDcsShortWriteNoP
uint32_t LPDcsShortWriteNoP
Definition: stm32l4xx_hal_dsi.h:218
DSI_VidCfgTypeDef::FrameBTAAcknowledgeEnable
uint32_t FrameBTAAcknowledgeEnable
Definition: stm32l4xx_hal_dsi.h:148
DSI_VidCfgTypeDef::DEPolarity
uint32_t DEPolarity
Definition: stm32l4xx_hal_dsi.h:104
HAL_DSI_ConfigHostTimeouts
HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
Configure the DSI HOST timeout parameters.
Definition: stm32l4xx_hal_dsi.c:1399
HAL_DSI_STATE_RESET
Definition: stm32l4xx_hal_dsi.h:293
DSI_PLLInitTypeDef::PLLNDIV
uint32_t PLLNDIV
Definition: stm32l4xx_hal_dsi.h:64
HAL_DSI_ExitULPMData
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running (only data lanes are in ULPM) ...
Definition: stm32l4xx_hal_dsi.c:1863
HAL_DSI_ForceTXStopMode
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
Force the Clock/Data Lane in TX Stop Mode.
Definition: stm32l4xx_hal_dsi.c:2533
DSI_PLLInitTypeDef::PLLIDF
uint32_t PLLIDF
Definition: stm32l4xx_hal_dsi.h:67
HAL_DSI_ErrorCallback
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
Operation Error DSI callback.
Definition: stm32l4xx_hal_dsi.c:960
DSI_InitTypeDef::AutomaticClockLaneControl
uint32_t AutomaticClockLaneControl
Definition: stm32l4xx_hal_dsi.h:48
HAL_DSI_GetError
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
Return the DSI error code.
Definition: stm32l4xx_hal_dsi.c:2705
HAL_DSI_CallbackIDTypeDef
HAL_DSI_CallbackIDTypeDef
HAL DSI Callback ID enumeration definition.
Definition: stm32l4xx_hal_dsi.h:332
DSI_VidCfgTypeDef::VerticalSyncActive
uint32_t VerticalSyncActive
Definition: stm32l4xx_hal_dsi.h:113
HAL_DSI_TEARING_EFFECT_CB_ID
Definition: stm32l4xx_hal_dsi.h:337
endif::Init
DSI_InitTypeDef Init
Definition: stm32l4xx_hal_dsi.h:310
DSI_VidCfgTypeDef::HSPolarity
uint32_t HSPolarity
Definition: stm32l4xx_hal_dsi.h:98
DSI_CmdCfgTypeDef::VSPolarity
uint32_t VSPolarity
Definition: stm32l4xx_hal_dsi.h:175
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_DSI_PatternGeneratorStop
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
Stop test pattern generation.
Definition: stm32l4xx_hal_dsi.c:2130
DSI_VidCfgTypeDef::LPHorizontalBackPorchEnable
uint32_t LPHorizontalBackPorchEnable
Definition: stm32l4xx_hal_dsi.h:133
HAL_DSI_STATE_ERROR
Definition: stm32l4xx_hal_dsi.h:295
DSI_VidCfgTypeDef
DSI Video mode configuration.
Definition: stm32l4xx_hal_dsi.h:78
HAL_DSI_Start
HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
Start the DSI module.
Definition: stm32l4xx_hal_dsi.c:1452
DSI_CmdCfgTypeDef::ColorCoding
uint32_t ColorCoding
Definition: stm32l4xx_hal_dsi.h:160
HAL_DSI_MspInit
void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
Initializes the DSI MSP.
Definition: stm32l4xx_hal_dsi.c:579
HAL_DSI_Shutdown
HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
Control the display shutdown in Video mode.
Definition: stm32l4xx_hal_dsi.c:1546
HAL_DSI_ENDOF_REFRESH_CB_ID
Definition: stm32l4xx_hal_dsi.h:338
DSI_InitTypeDef::TXEscapeCkdiv
uint32_t TXEscapeCkdiv
Definition: stm32l4xx_hal_dsi.h:51
DSI_HOST_TimeoutTypeDef::LowPowerWriteTimeout
uint32_t LowPowerWriteTimeout
Definition: stm32l4xx_hal_dsi.h:282
DSI_LPCmdTypeDef::LPDcsLongWrite
uint32_t LPDcsLongWrite
Definition: stm32l4xx_hal_dsi.h:227
DSI_VidCfgTypeDef::LPCommandEnable
uint32_t LPCommandEnable
Definition: stm32l4xx_hal_dsi.h:121
endif::Instance
DSI_TypeDef * Instance
Definition: stm32l4xx_hal_dsi.h:309
DSI_LPCmdTypeDef::LPGenShortReadNoP
uint32_t LPGenShortReadNoP
Definition: stm32l4xx_hal_dsi.h:206
DSI_VidCfgTypeDef::Mode
uint32_t Mode
Definition: stm32l4xx_hal_dsi.h:89
DSI_VidCfgTypeDef::LooselyPacked
uint32_t LooselyPacked
Definition: stm32l4xx_hal_dsi.h:85
DSI_VidCfgTypeDef::NullPacketSize
uint32_t NullPacketSize
Definition: stm32l4xx_hal_dsi.h:96
DSI_LPCmdTypeDef::LPGenShortReadOneP
uint32_t LPGenShortReadOneP
Definition: stm32l4xx_hal_dsi.h:209
HAL_DSI_StateTypeDef
HAL_DSI_StateTypeDef
DSI States Structure definition.
Definition: stm32l4xx_hal_dsi.h:291
DSI_LPCmdTypeDef::LPGenShortWriteNoP
uint32_t LPGenShortWriteNoP
Definition: stm32l4xx_hal_dsi.h:197
DSI_VidCfgTypeDef::LPHorizontalFrontPorchEnable
uint32_t LPHorizontalFrontPorchEnable
Definition: stm32l4xx_hal_dsi.h:130
HAL_DSI_ExitULPM
HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off (both data and clock lanes are in ...
Definition: stm32l4xx_hal_dsi.c:2004
HAL_DSI_SetSDD
HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
Activate an additional current path on all lanes to meet the SDDTx parameter defined in the MIPI D-PH...
Definition: stm32l4xx_hal_dsi.c:2270
DSI_LPCmdTypeDef
DSI command transmission mode configuration.
Definition: stm32l4xx_hal_dsi.h:195
DSI_LPCmdTypeDef::LPDcsShortReadNoP
uint32_t LPDcsShortReadNoP
Definition: stm32l4xx_hal_dsi.h:224
DSI_HOST_TimeoutTypeDef::BTATimeout
uint32_t BTATimeout
Definition: stm32l4xx_hal_dsi.h:284
DSI_HOST_TimeoutTypeDef::TimeoutCkdiv
uint32_t TimeoutCkdiv
Definition: stm32l4xx_hal_dsi.h:267
HAL_DSI_SetSlewRateAndDelayTuning
HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
Set Slew-Rate And Delay Tuning.
Definition: stm32l4xx_hal_dsi.c:2155
DSI_PHY_TimerTypeDef
DSI PHY Timings definition.
Definition: stm32l4xx_hal_dsi.h:241
DSI_VidCfgTypeDef::NumberOfChunks
uint32_t NumberOfChunks
Definition: stm32l4xx_hal_dsi.h:94
DSI_CmdCfgTypeDef::HSPolarity
uint32_t HSPolarity
Definition: stm32l4xx_hal_dsi.h:172
DSI_CmdCfgTypeDef::VirtualChannelID
uint32_t VirtualChannelID
Definition: stm32l4xx_hal_dsi.h:158
HAL_DSI_IRQHandler
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
Handles DSI interrupt request.
Definition: stm32l4xx_hal_dsi.c:809
DSI_VidCfgTypeDef::LPVACTLargestPacketSize
uint32_t LPVACTLargestPacketSize
Definition: stm32l4xx_hal_dsi.h:127
HAL_DSI_ConfigCommand
HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
Configure command transmission mode: High-speed or Low-power and enable/disable acknowledge request a...
Definition: stm32l4xx_hal_dsi.c:1264
DSI_LPCmdTypeDef::LPGenLongWrite
uint32_t LPGenLongWrite
Definition: stm32l4xx_hal_dsi.h:215
DSI_VidCfgTypeDef::HorizontalBackPorch
uint32_t HorizontalBackPorch
Definition: stm32l4xx_hal_dsi.h:109
HAL_DSI_STATE_BUSY
Definition: stm32l4xx_hal_dsi.h:296
HAL_DSI_TearingEffectCallback
void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
Tearing Effect DSI callback.
Definition: stm32l4xx_hal_dsi.c:930
HAL_DSI_Read
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, uint8_t *ParametersTable)
Read command (DCS or generic)
Definition: stm32l4xx_hal_dsi.c:1699
HAL_DSI_ConfigVideoMode
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
Select video mode and configure the corresponding parameters.
Definition: stm32l4xx_hal_dsi.c:1043
DSI_HOST_TimeoutTypeDef::HighSpeedWriteTimeout
uint32_t HighSpeedWriteTimeout
Definition: stm32l4xx_hal_dsi.h:277
DSI_LPCmdTypeDef::LPDcsShortWriteOneP
uint32_t LPDcsShortWriteOneP
Definition: stm32l4xx_hal_dsi.h:221
HAL_DSI_ConfigAdaptedCommandMode
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
Select adapted command mode and configure the corresponding parameters.
Definition: stm32l4xx_hal_dsi.c:1193
DSI_CmdCfgTypeDef::TearingEffectSource
uint32_t TearingEffectSource
Definition: stm32l4xx_hal_dsi.h:166
DSI_VidCfgTypeDef::LPVerticalBackPorchEnable
uint32_t LPVerticalBackPorchEnable
Definition: stm32l4xx_hal_dsi.h:142
DSI_VidCfgTypeDef::ColorCoding
uint32_t ColorCoding
Definition: stm32l4xx_hal_dsi.h:82
DSI_VidCfgTypeDef::LPVerticalSyncActiveEnable
uint32_t LPVerticalSyncActiveEnable
Definition: stm32l4xx_hal_dsi.h:145
HAL_DSI_PatternGeneratorStart
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
Start test pattern generation.
Definition: stm32l4xx_hal_dsi.c:2106
HAL_DSI_Init
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
Initializes the DSI according to the specified parameters in the DSI_InitTypeDef and create the assoc...
Definition: stm32l4xx_hal_dsi.c:303
endif::State
__IO HAL_DSI_StateTypeDef State
Definition: stm32l4xx_hal_dsi.h:312
DSI_InitTypeDef
DSI Init Structure definition.
Definition: stm32l4xx_hal_dsi.h:46
DSI_PHY_TimerTypeDef::ClockLaneHS2LPTime
uint32_t ClockLaneHS2LPTime
Definition: stm32l4xx_hal_dsi.h:243
pDSI_CallbackTypeDef
void(* pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi)
HAL DSI Callback pointer definition.
Definition: stm32l4xx_hal_dsi.h:346
DSI_PHY_TimerTypeDef::DataLaneHS2LPTime
uint32_t DataLaneHS2LPTime
Definition: stm32l4xx_hal_dsi.h:249
HAL_DSI_GetState
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
Return the DSI state.
Definition: stm32l4xx_hal_dsi.c:2694
DSI_CmdCfgTypeDef::TEAcknowledgeRequest
uint32_t TEAcknowledgeRequest
Definition: stm32l4xx_hal_dsi.h:187
HAL_DSI_ConfigPhyTimer
HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
Configure the DSI PHY timer parameters.
Definition: stm32l4xx_hal_dsi.c:1353
DSI_VidCfgTypeDef::HorizontalLine
uint32_t HorizontalLine
Definition: stm32l4xx_hal_dsi.h:111
DSI_LPCmdTypeDef::LPGenShortWriteOneP
uint32_t LPGenShortWriteOneP
Definition: stm32l4xx_hal_dsi.h:200
DSI_VidCfgTypeDef::HorizontalSyncActive
uint32_t HorizontalSyncActive
Definition: stm32l4xx_hal_dsi.h:107
DSI_PHY_TimerTypeDef::DataLaneLP2HSTime
uint32_t DataLaneLP2HSTime
Definition: stm32l4xx_hal_dsi.h:252
DSI_VidCfgTypeDef::LPVerticalActiveEnable
uint32_t LPVerticalActiveEnable
Definition: stm32l4xx_hal_dsi.h:136
DSI_LPCmdTypeDef::AcknowledgeRequest
uint32_t AcknowledgeRequest
Definition: stm32l4xx_hal_dsi.h:233
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32l4xx_hal_def.h:50
DSI_HOST_TimeoutTypeDef::HighSpeedWritePrespMode
uint32_t HighSpeedWritePrespMode
Definition: stm32l4xx_hal_dsi.h:279
HAL_DSI_Stop
HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
Stop the DSI module.
Definition: stm32l4xx_hal_dsi.c:1475
HAL_DSI_SetContentionDetectionOff
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
Switch off the contention detection on data lanes.
Definition: stm32l4xx_hal_dsi.c:2650
DSI_VidCfgTypeDef::VSPolarity
uint32_t VSPolarity
Definition: stm32l4xx_hal_dsi.h:101
HAL_DSI_SetPHYTimings
HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
Set custom timing for the PHY.
Definition: stm32l4xx_hal_dsi.c:2386
DSI_HOST_TimeoutTypeDef::LowPowerReceptionTimeout
uint32_t LowPowerReceptionTimeout
Definition: stm32l4xx_hal_dsi.h:271
HAL_DSI_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_dsi.h:335
HAL_DSI_STATE_TIMEOUT
Definition: stm32l4xx_hal_dsi.h:297
endif
ADC handle Structure definition.
Definition: stm32l4xx_hal_adc.h:360
DSI_VidCfgTypeDef::LPLargestPacketSize
uint32_t LPLargestPacketSize
Definition: stm32l4xx_hal_dsi.h:124
DSI_VidCfgTypeDef::VerticalActive
uint32_t VerticalActive
Definition: stm32l4xx_hal_dsi.h:119
HAL_DSI_MspDeInit
void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
De-initializes the DSI MSP.
Definition: stm32l4xx_hal_dsi.c:594
HAL_DSI_RegisterCallback
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback)
Register a User DSI Callback To be used instead of the weak predefined callback.
Definition: stm32l4xx_hal_dsi.c:618
DSI_VidCfgTypeDef::PacketSize
uint32_t PacketSize
Definition: stm32l4xx_hal_dsi.h:92
DSI_VidCfgTypeDef::VerticalBackPorch
uint32_t VerticalBackPorch
Definition: stm32l4xx_hal_dsi.h:115
DSI_HandleTypeDef
struct __DSI_HandleTypeDef else typedef struct endif DSI_HandleTypeDef
DSI Handle Structure definition.
DSI_LPCmdTypeDef::LPGenShortWriteTwoP
uint32_t LPGenShortWriteTwoP
Definition: stm32l4xx_hal_dsi.h:203
HAL_DSI_ERROR_CB_ID
Definition: stm32l4xx_hal_dsi.h:339
DSI_VidCfgTypeDef::VirtualChannelID
uint32_t VirtualChannelID
Definition: stm32l4xx_hal_dsi.h:80
DSI_PHY_TimerTypeDef::ClockLaneLP2HSTime
uint32_t ClockLaneLP2HSTime
Definition: stm32l4xx_hal_dsi.h:246
DSI_LPCmdTypeDef::LPMaxReadPacket
uint32_t LPMaxReadPacket
Definition: stm32l4xx_hal_dsi.h:230
HAL_DSI_ColorMode
HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
Controls the display color mode in Video mode.
Definition: stm32l4xx_hal_dsi.c:1520
DSI_HOST_TimeoutTypeDef::HighSpeedTransmissionTimeout
uint32_t HighSpeedTransmissionTimeout
Definition: stm32l4xx_hal_dsi.h:269
HAL_DSI_SetLanePinsConfiguration
HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
Custom lane pins configuration.
Definition: stm32l4xx_hal_dsi.c:2299
HAL_DSI_ForceDataLanesInRX
HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
Force Data Lanes in RX Mode after a BTA.
Definition: stm32l4xx_hal_dsi.c:2600
DSI_CmdCfgTypeDef::DEPolarity
uint32_t DEPolarity
Definition: stm32l4xx_hal_dsi.h:178
HAL_DSI_ShortWrite
HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t Param1, uint32_t Param2)
write short DCS or short Generic command
Definition: stm32l4xx_hal_dsi.c:1577
HAL_DSI_SetGenericVCID
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
Configure the Generic interface read-back Virtual Channel ID.
Definition: stm32l4xx_hal_dsi.c:1020
DSI_InitTypeDef::NumberOfLanes
uint32_t NumberOfLanes
Definition: stm32l4xx_hal_dsi.h:54
DSI_CmdCfgTypeDef::CommandSize
uint32_t CommandSize
Definition: stm32l4xx_hal_dsi.h:163
HAL_DSI_ConfigFlowControl
HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
Configure the flow control parameters.
Definition: stm32l4xx_hal_dsi.c:1327
HAL_DSI_EnterULPM
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off (both data and clock lanes are in...
Definition: stm32l4xx_hal_dsi.c:1932
else
else
Definition: stm32l4xx_ll_lpuart.h:1488
HAL_DSI_LongWrite
HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t NbParams, uint32_t Param1, uint8_t *ParametersTable)
write long DCS or long Generic command
Definition: stm32l4xx_hal_dsi.c:1612
DSI_CmdCfgTypeDef::AutomaticRefresh
uint32_t AutomaticRefresh
Definition: stm32l4xx_hal_dsi.h:184
DSI_PLLInitTypeDef::PLLODF
uint32_t PLLODF
Definition: stm32l4xx_hal_dsi.h:70
HAL_DSI_SetLowPowerRXFilter
HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
Low-Power Reception Filter Tuning.
Definition: stm32l4xx_hal_dsi.c:2247