NOR SRAM Initialization/de-initialization functions

Functions
HAL_StatusTypeDef	FMC_NORSRAM_Init (FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
	Initialize the FMC_NORSRAM device according to the specified control parameters in the FMC_NORSRAM_InitTypeDef. More...
HAL_StatusTypeDef	FMC_NORSRAM_Timing_Init (FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
	Initialize the FMC_NORSRAM Timing according to the specified parameters in the FMC_NORSRAM_TimingTypeDef. More...
HAL_StatusTypeDef	FMC_NORSRAM_Extended_Timing_Init (FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
	Initialize the FMC_NORSRAM Extended mode Timing according to the specified parameters in the FMC_NORSRAM_TimingTypeDef. More...
HAL_StatusTypeDef	FMC_NORSRAM_DeInit (FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
	DeInitialize the FMC_NORSRAM peripheral. More...

Detailed Description

Function Documentation

FMC_NORSRAM_DeInit()

HAL_StatusTypeDef FMC_NORSRAM_DeInit	(	FMC_NORSRAM_TypeDef *	Device,
		FMC_NORSRAM_EXTENDED_TypeDef *	ExDevice,
		uint32_t	Bank
	)

DeInitialize the FMC_NORSRAM peripheral.

Parameters

Device	Pointer to NORSRAM device instance
ExDevice	Pointer to NORSRAM extended mode device instance
Bank	NORSRAM bank number

Return values

HAL

status

Definition at line 320 of file stm32l4xx_ll_fmc.c.

{
  /* Check the parameters */
  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  assert_param(IS_FMC_NORSRAM_BANK(Bank));

  /* Disable the FMC_NORSRAM device */
  __FMC_NORSRAM_DISABLE(Device, Bank);

  /* De-initialize the FMC_NORSRAM device */
  /* FMC_NORSRAM_BANK1 */
  if (Bank == FMC_NORSRAM_BANK1)
  {
    Device->BTCR[Bank] = 0x000030DBU;
  }
  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
  else
  {
    Device->BTCR[Bank] = 0x000030D2U;
  }

  Device->BTCR[Bank + 1] = 0x0FFFFFFFU;
  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;

  return HAL_OK;
}

FMC_NORSRAM_Extended_Timing_Init()

HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init	(	FMC_NORSRAM_EXTENDED_TypeDef *	Device,
		FMC_NORSRAM_TimingTypeDef *	Timing,
		uint32_t	Bank,
		uint32_t	ExtendedMode
	)

Initialize the FMC_NORSRAM Extended mode Timing according to the specified parameters in the FMC_NORSRAM_TimingTypeDef.

Parameters

Device	Pointer to NORSRAM device instance
Timing	Pointer to NORSRAM Timing structure
Bank	NORSRAM bank number
ExtendedMode	FMC Extended Mode This parameter can be one of the following values: FMC_EXTENDED_MODE_DISABLE FMC_EXTENDED_MODE_ENABLE

Return values

HAL

status

Definition at line 410 of file stm32l4xx_ll_fmc.c.

{
  /* Check the parameters */
  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));

  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
  {
    /* Check the parameters */
    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
#if defined(FMC_BTRx_DATAHLD)
    assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
#endif /* FMC_BTRx_DATAHLD */
    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
    assert_param(IS_FMC_NORSRAM_BANK(Bank));

    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                              |
                          ((Timing->AddressHoldTime)        << FMC_BWTRx_ADDHLD_Pos)  |
                          ((Timing->DataSetupTime)          << FMC_BWTRx_DATAST_Pos)  |
#if defined(FMC_BTRx_DATAHLD)
                          ((Timing->DataHoldTime)           << FMC_BWTRx_DATAHLD_Pos) |
#endif /* FMC_BTRx_DATAHLD */
                          Timing->AccessMode                                          |
                          ((Timing->BusTurnAroundDuration)  << FMC_BWTRx_BUSTURN_Pos)));
  }
  else
  {
    Device->BWTR[Bank] = 0x0FFFFFFFU;
  }

  return HAL_OK;
}

FMC_NORSRAM_Init()

HAL_StatusTypeDef FMC_NORSRAM_Init	(	FMC_NORSRAM_TypeDef *	Device,
		FMC_NORSRAM_InitTypeDef *	Init
	)

Initialize the FMC_NORSRAM device according to the specified control parameters in the FMC_NORSRAM_InitTypeDef.

Parameters

Device	Pointer to NORSRAM device instance
Init	Pointer to NORSRAM Initialization structure

Return values

HAL

status

Definition at line 234 of file stm32l4xx_ll_fmc.c.

{
  uint32_t flashaccess;

  /* Check the parameters */
  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
  assert_param(IS_FMC_MUX(Init->DataAddressMux));
  assert_param(IS_FMC_MEMORY(Init->MemoryType));
  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
#if defined(FMC_BCR1_WFDIS)
  assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
#endif /* FMC_BCR1_WFDIS */
  assert_param(IS_FMC_PAGESIZE(Init->PageSize));
#if defined(FMC_BCRx_NBLSET)
  assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
#endif /* FMC_BCRx_NBLSET */

  /* Disable NORSRAM Device */
  __FMC_NORSRAM_DISABLE(Device, Init->NSBank);

  /* Set NORSRAM device control parameters */
  if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
  {
    flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
  }
  else
  {
    flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
  }

  MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (flashaccess              |
                                                          Init->DataAddressMux     |
                                                          Init->MemoryType         |
                                                          Init->MemoryDataWidth    |
                                                          Init->BurstAccessMode    |
                                                          Init->WaitSignalPolarity |
                                                          Init->WaitSignalActive   |
                                                          Init->WriteOperation     |
                                                          Init->WaitSignal         |
                                                          Init->ExtendedMode       |
                                                          Init->AsynchronousWait   |
                                                          Init->WriteBurst         |
                                                          Init->ContinuousClock    |
#if defined(FMC_BCR1_WFDIS)
                                                          Init->WriteFifo          |
#endif /* FMC_BCR1_WFDIS */
#if defined(FMC_BCRx_NBLSET)
                                                          Init->NBLSetupTime       |
#endif /* FMC_BCRx_NBLSET */
                                                          Init->PageSize));

  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
  if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
  {
    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
  }

#if defined(FMC_BCR1_WFDIS)
  if (Init->NSBank != FMC_NORSRAM_BANK1)
  {
    /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
    SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
  }
#endif /* FMC_BCR1_WFDIS */

  return HAL_OK;
}

FMC_NORSRAM_Timing_Init()

HAL_StatusTypeDef FMC_NORSRAM_Timing_Init	(	FMC_NORSRAM_TypeDef *	Device,
		FMC_NORSRAM_TimingTypeDef *	Timing,
		uint32_t	Bank
	)

Initialize the FMC_NORSRAM Timing according to the specified parameters in the FMC_NORSRAM_TimingTypeDef.

Parameters

Device	Pointer to NORSRAM device instance
Timing	Pointer to NORSRAM Timing structure
Bank	NORSRAM bank number

Return values

HAL

status

Definition at line 357 of file stm32l4xx_ll_fmc.c.

{
  uint32_t tmpr = 0;

  /* Check the parameters */
  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
#if defined(FMC_BTRx_DATAHLD)
  assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
#endif /* FMC_BTRx_DATAHLD */
  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
  assert_param(IS_FMC_NORSRAM_BANK(Bank));

  /* Set FMC_NORSRAM device timing parameters */
  MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                             |
                        ((Timing->AddressHoldTime)        << FMC_BTRx_ADDHLD_Pos)        |
                        ((Timing->DataSetupTime)          << FMC_BTRx_DATAST_Pos)        |
#if defined(FMC_BTRx_DATAHLD)
                        ((Timing->DataHoldTime)           << FMC_BTRx_DATAHLD_Pos)       |
#endif /* FMC_BTRx_DATAHLD */
                        ((Timing->BusTurnAroundDuration)  << FMC_BTRx_BUSTURN_Pos)       |
                        (((Timing->CLKDivision) - 1)      << FMC_BTRx_CLKDIV_Pos)        |
                        (((Timing->DataLatency) - 2)      << FMC_BTRx_DATLAT_Pos)        |
                        (Timing->AccessMode)));

  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
  if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
  {
    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
    tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos);
    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
  }

  return HAL_OK;
}