Input and Output functions

Input Output and memory control functions. More...

Functions
HAL_StatusTypeDef	HAL_NOR_Read_ID (NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
	Read NOR flash IDs. More...
HAL_StatusTypeDef	HAL_NOR_ReturnToReadMode (NOR_HandleTypeDef *hnor)
	Return the NOR memory to Read mode. More...
HAL_StatusTypeDef	HAL_NOR_Read (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
	Read data from NOR memory. More...
HAL_StatusTypeDef	HAL_NOR_Program (NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
	Program data to NOR memory. More...
HAL_StatusTypeDef	HAL_NOR_ReadBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
	Read a half-word buffer from the NOR memory. More...
HAL_StatusTypeDef	HAL_NOR_ProgramBuffer (NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
	Writes a half-word buffer to the NOR memory. This function must be used only with S29GL128P NOR memory. More...
HAL_StatusTypeDef	HAL_NOR_Erase_Block (NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
	Erase the specified block of the NOR memory. More...
HAL_StatusTypeDef	HAL_NOR_Erase_Chip (NOR_HandleTypeDef *hnor, uint32_t Address)
	Erase the entire NOR chip. More...
HAL_StatusTypeDef	HAL_NOR_Read_CFI (NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
	Read NOR flash CFI IDs. More...

Detailed Description

Input Output and memory control functions.

  ==============================================================================
                ##### NOR Input and Output functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to use and control the NOR memory

Function Documentation

HAL_NOR_Erase_Block()

HAL_StatusTypeDef HAL_NOR_Erase_Block	(	NOR_HandleTypeDef *	hnor,
		uint32_t	BlockAddress,
		uint32_t	Address
	)

Erase the specified block of the NOR memory.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
BlockAddress	Block to erase address
Address	Device address

Return values

HAL

status

Definition at line 680 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send block erase command sequence */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);

  /* Check the NOR memory status and update the controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;

}

HAL_NOR_Erase_Chip()

HAL_StatusTypeDef HAL_NOR_Erase_Chip	(	NOR_HandleTypeDef *	hnor,
		uint32_t	Address
	)

Erase the entire NOR chip.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
Address	Device address

Return values

HAL

status

Definition at line 739 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Prevent unused argument(s) compilation warning */
  UNUSED(Address);

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send NOR chip erase command sequence */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);

  /* Check the NOR memory status and update the controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}

HAL_NOR_Program()

HAL_StatusTypeDef HAL_NOR_Program	(	NOR_HandleTypeDef *	hnor,
		uint32_t *	pAddress,
		uint16_t *	pData
	)

Program data to NOR memory.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress	Device address
pData	pointer to the data to write

Return values

HAL

status

Definition at line 475 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send program data command */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);

  /* Write the data */
  NOR_WRITE(pAddress, *pData);

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}

HAL_NOR_ProgramBuffer()

HAL_StatusTypeDef HAL_NOR_ProgramBuffer	(	NOR_HandleTypeDef *	hnor,
		uint32_t	uwAddress,
		uint16_t *	pData,
		uint32_t	uwBufferSize
	)

Writes a half-word buffer to the NOR memory. This function must be used only with S29GL128P NOR memory.

Parameters

hnor	pointer to the NOR handle
uwAddress	NOR memory internal start write address
pData	pointer to source data buffer.
uwBufferSize	Size of the buffer to write

Return values

HAL

status

Definition at line 600 of file stm32l4xx_hal_nor.c.

{
  uint16_t * p_currentaddress = (uint16_t *)NULL;
  uint16_t * p_endaddress = (uint16_t *)NULL;
  uint32_t lastloadedaddress = 0, deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Initialize variables */
  p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
  p_endaddress      = p_currentaddress + (uwBufferSize-1);
  lastloadedaddress = (uint32_t)(uwAddress);

  /* Issue unlock command sequence */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);

  /* Write Buffer Load Command */
  NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
  NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));

  /* Load Data into NOR Buffer */
  while(p_currentaddress <= p_endaddress)
  {
    /* Store last loaded address & data value (for polling) */
    lastloadedaddress = (uint32_t)p_currentaddress;

    NOR_WRITE(p_currentaddress, *pData++);

    p_currentaddress++;
  }

  NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;

}

HAL_NOR_Read()

HAL_StatusTypeDef HAL_NOR_Read	(	NOR_HandleTypeDef *	hnor,
		uint32_t *	pAddress,
		uint16_t *	pData
	)

Read data from NOR memory.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pAddress	pointer to Device address
pData	pointer to read data

Return values

HAL

status

Definition at line 416 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send read data command */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);

  /* Read the data */
  *pData = *(__IO uint32_t *)(uint32_t)pAddress;

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}

HAL_NOR_Read_CFI()

HAL_StatusTypeDef HAL_NOR_Read_CFI	(	NOR_HandleTypeDef *	hnor,
		NOR_CFITypeDef *	pNOR_CFI
	)

Read NOR flash CFI IDs.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_CFI	pointer to NOR CFI IDs structure

Return values

HAL

status

Definition at line 800 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send read CFI query command */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);

  /* read the NOR CFI information */
  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}

HAL_NOR_Read_ID()

HAL_StatusTypeDef HAL_NOR_Read_ID	(	NOR_HandleTypeDef *	hnor,
		NOR_IDTypeDef *	pNOR_ID
	)

Read NOR flash IDs.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.
pNOR_ID	pointer to NOR ID structure

Return values

HAL

status

Definition at line 306 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send read ID command */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);

  /* Read the NOR IDs */
  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}

HAL_NOR_ReadBuffer()

HAL_StatusTypeDef HAL_NOR_ReadBuffer	(	NOR_HandleTypeDef *	hnor,
		uint32_t	uwAddress,
		uint16_t *	pData,
		uint32_t	uwBufferSize
	)

Read a half-word buffer from the NOR memory.

Parameters

hnor	pointer to the NOR handle
uwAddress	NOR memory internal address to read from.
pData	pointer to the buffer that receives the data read from the NOR memory.
uwBufferSize	number of Half word to read.

Return values

HAL

status

Definition at line 535 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  /* Update the NOR controller state */
  hnor->State = HAL_NOR_STATE_BUSY;

  /* Send read data command */
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);

  /* Read buffer */
  while( uwBufferSize > 0)
  {
    *pData++ = *(__IO uint16_t *)uwAddress;
    uwAddress += 2;
    uwBufferSize--;
  }

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}

HAL_NOR_ReturnToReadMode()

HAL_StatusTypeDef HAL_NOR_ReturnToReadMode

(

NOR_HandleTypeDef *

hnor

)

Return the NOR memory to Read mode.

Parameters

hnor	pointer to a NOR_HandleTypeDef structure that contains the configuration information for NOR module.

Return values

HAL

status

Definition at line 366 of file stm32l4xx_hal_nor.c.

{
  uint32_t deviceaddress = 0;

  /* Process Locked */
  __HAL_LOCK(hnor);

  /* Check the NOR controller state */
  if(hnor->State == HAL_NOR_STATE_BUSY)
  {
     return HAL_BUSY;
  }

  /* Select the NOR device address */
  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  {
    deviceaddress = NOR_MEMORY_ADRESS1;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  {
    deviceaddress = NOR_MEMORY_ADRESS2;
  }
  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  {
    deviceaddress = NOR_MEMORY_ADRESS3;
  }
  else /* FMC_NORSRAM_BANK4 */
  {
    deviceaddress = NOR_MEMORY_ADRESS4;
  }

  NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);

  /* Check the NOR controller state */
  hnor->State = HAL_NOR_STATE_READY;

  /* Process unlocked */
  __HAL_UNLOCK(hnor);

  return HAL_OK;
}