STM32L4xx_HAL_Driver  1.14.0
Functions
Extended Peripheral Control functions
STM32L4xx_HAL_Driver » RCCEx » RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
 Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef. More...
 
void HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
 Get the RCC_ClkInitStruct according to the internal RCC configuration registers. More...
 
uint32_t HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
 Return the peripheral clock frequency for peripherals with clock source from PLLSAIs. More...
 

Detailed Description

Extended Peripheral Control functions. 

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

Function Documentation

◆ HAL_RCCEx_GetPeriphCLKConfig()

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef *  PeriphClkInit)

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters
PeriphClkInitpointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART, USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG).
Return values
None

Definition at line 826 of file stm32l4xx_hal_rcc_ex.c.

827 {
828  /* Set all possible values for the extended clock type parameter------------*/
829 
830 #if defined(STM32L412xx) || defined(STM32L422xx)
831 
832  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
833  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
834  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_USB | \
835  RCC_PERIPHCLK_RNG | \
836  RCC_PERIPHCLK_RTC ;
837 
838 #elif defined(STM32L431xx)
839 
840  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
841  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
842  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
843  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
844  RCC_PERIPHCLK_RTC ;
845 
846 #elif defined(STM32L432xx) || defined(STM32L442xx)
847 
848  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
849  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
850  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
851  RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
852  RCC_PERIPHCLK_RTC ;
853 
854 #elif defined(STM32L433xx) || defined(STM32L443xx)
855 
856  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
857  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
858  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
859  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
860  RCC_PERIPHCLK_RTC ;
861 
862 #elif defined(STM32L451xx)
863 
864  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
865  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
866  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
867  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
868  RCC_PERIPHCLK_RTC ;
869 
870 #elif defined(STM32L452xx) || defined(STM32L462xx)
871 
872  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
873  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
874  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
875  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
876  RCC_PERIPHCLK_RTC ;
877 
878 #elif defined(STM32L471xx)
879 
880  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
881  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
882  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
883  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
884  RCC_PERIPHCLK_RTC ;
885 
886 #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
887 
888  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
889  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
890  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
891  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
892  RCC_PERIPHCLK_RTC ;
893 
894 #elif defined(STM32L496xx) || defined(STM32L4A6xx)
895 
896  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
897  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
898  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
899  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
900  RCC_PERIPHCLK_RTC ;
901 
902 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
903 
904  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
905  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
906  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
907  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
908  RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI;
909 
910 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx)
911 
912  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
913  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
914  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
915  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
916  RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC;
917 
918 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
919 
920  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
921  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
922  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
923  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
924  RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI;
925 
926 #endif /* STM32L431xx */
927 
928 #if defined(RCC_PLLSAI1_SUPPORT)
929 
930  /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
931 
932  PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos;
933 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
934  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U;
935 #else
936  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
937 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
938  PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
939  PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U;
940  PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U;
941  PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U;
942 
943 #endif /* RCC_PLLSAI1_SUPPORT */
944 
945 #if defined(RCC_PLLSAI2_SUPPORT)
946 
947  /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
948 
949  PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
950 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
951  PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U;
952 #else
953  PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
954 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
955  PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
956  PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U;
957 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
958  PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U;
959 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
960  PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U;
961 
962 #endif /* RCC_PLLSAI2_SUPPORT */
963 
964  /* Get the USART1 clock source ---------------------------------------------*/
965  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
966  /* Get the USART2 clock source ---------------------------------------------*/
967  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
968 
969 #if defined(USART3)
970  /* Get the USART3 clock source ---------------------------------------------*/
971  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
972 #endif /* USART3 */
973 
974 #if defined(UART4)
975  /* Get the UART4 clock source ----------------------------------------------*/
976  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
977 #endif /* UART4 */
978 
979 #if defined(UART5)
980  /* Get the UART5 clock source ----------------------------------------------*/
981  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
982 #endif /* UART5 */
983 
984  /* Get the LPUART1 clock source --------------------------------------------*/
985  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
986 
987  /* Get the I2C1 clock source -----------------------------------------------*/
988  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
989 
990 #if defined(I2C2)
991  /* Get the I2C2 clock source ----------------------------------------------*/
992  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
993 #endif /* I2C2 */
994 
995  /* Get the I2C3 clock source -----------------------------------------------*/
996  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
997 
998 #if defined(I2C4)
999  /* Get the I2C4 clock source -----------------------------------------------*/
1000  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
1001 #endif /* I2C4 */
1002 
1003  /* Get the LPTIM1 clock source ---------------------------------------------*/
1004  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1005 
1006  /* Get the LPTIM2 clock source ---------------------------------------------*/
1007  PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1008 
1009 #if defined(SAI1)
1010  /* Get the SAI1 clock source -----------------------------------------------*/
1011  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1012 #endif /* SAI1 */
1013 
1014 #if defined(SAI2)
1015  /* Get the SAI2 clock source -----------------------------------------------*/
1016  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1017 #endif /* SAI2 */
1018 
1019  /* Get the RTC clock source ------------------------------------------------*/
1020  PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1021 
1022 #if defined(USB_OTG_FS) || defined(USB)
1023  /* Get the USB clock source ------------------------------------------------*/
1024  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
1025 #endif /* USB_OTG_FS || USB */
1026 
1027 #if defined(SDMMC1)
1028  /* Get the SDMMC1 clock source ---------------------------------------------*/
1029  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
1030 #endif /* SDMMC1 */
1031 
1032  /* Get the RNG clock source ------------------------------------------------*/
1033  PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1034 
1035 #if !defined(STM32L412xx) && !defined(STM32L422xx)
1036  /* Get the ADC clock source ------------------------------------------------*/
1037  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1038 #endif /* !STM32L412xx && !STM32L422xx */
1039 
1040 #if defined(SWPMI1)
1041  /* Get the SWPMI1 clock source ---------------------------------------------*/
1042  PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
1043 #endif /* SWPMI1 */
1044 
1045 #if defined(DFSDM1_Filter0)
1046  /* Get the DFSDM1 clock source ---------------------------------------------*/
1047  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
1048 
1049 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1050  /* Get the DFSDM1 audio clock source ---------------------------------------*/
1051  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
1052 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1053 #endif /* DFSDM1_Filter0 */
1054 
1055 #if defined(LTDC)
1056  /* Get the LTDC clock source -----------------------------------------------*/
1057  PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
1058 #endif /* LTDC */
1059 
1060 #if defined(DSI)
1061  /* Get the DSI clock source ------------------------------------------------*/
1062  PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1063 #endif /* DSI */
1064 
1065 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1066  /* Get the OctoSPIclock source --------------------------------------------*/
1067  PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1068 #endif /* OCTOSPI1 || OCTOSPI2 */
1069 }
RCC_PeriphCLKInitTypeDef::I2c2ClockSelection
uint32_t I2c2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:172
RCC_PeriphCLKInitTypeDef::OspiClockSelection
uint32_t OspiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:263
RCC_PLLSAI2InitTypeDef::PLLSAI2Source
uint32_t PLLSAI2Source
Definition: stm32l4xx_hal_rcc_ex.h:87
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:123
RCC_PeriphCLKInitTypeDef::Uart4ClockSelection
uint32_t Uart4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:152
RCC_PeriphCLKInitTypeDef::Sai2ClockSelection
uint32_t Sai2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:200
RCC_PLLSAI2InitTypeDef::PLLSAI2P
uint32_t PLLSAI2P
Definition: stm32l4xx_hal_rcc_ex.h:101
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:223
RCC_PeriphCLKInitTypeDef::I2c1ClockSelection
uint32_t I2c1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:167
RCC_PeriphCLKInitTypeDef::I2c3ClockSelection
uint32_t I2c3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:177
RCC_PeriphCLKInitTypeDef::PLLSAI1
RCC_PLLSAI1InitTypeDef PLLSAI1
Definition: stm32l4xx_hal_rcc_ex.h:127
RCC_PLLSAI2InitTypeDef::PLLSAI2Q
uint32_t PLLSAI2Q
Definition: stm32l4xx_hal_rcc_ex.h:105
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:182
RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:229
RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:164
RCC_PLLSAI2InitTypeDef::PLLSAI2R
uint32_t PLLSAI2R
Definition: stm32l4xx_hal_rcc_ex.h:109
RCC_PLLSAI2InitTypeDef::PLLSAI2N
uint32_t PLLSAI2N
Definition: stm32l4xx_hal_rcc_ex.h:98
RCC_PeriphCLKInitTypeDef::Usart1ClockSelection
uint32_t Usart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:137
RCC_PLLSAI2InitTypeDef::PLLSAI2M
uint32_t PLLSAI2M
Definition: stm32l4xx_hal_rcc_ex.h:91
RCC_PeriphCLKInitTypeDef::Uart5ClockSelection
uint32_t Uart5ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:159
RCC_PeriphCLKInitTypeDef::Dfsdm1AudioClockSelection
uint32_t Dfsdm1AudioClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:240
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:236
RCC_PeriphCLKInitTypeDef::Usart2ClockSelection
uint32_t Usart2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:140
RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:190
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:187
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:268
RCC_PeriphCLKInitTypeDef::LtdcClockSelection
uint32_t LtdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:249
RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection
uint32_t Sdmmc1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:214
RCC_PeriphCLKInitTypeDef::DsiClockSelection
uint32_t DsiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:256
RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:207
RCC_PeriphCLKInitTypeDef::PLLSAI2
RCC_PLLSAI2InitTypeDef PLLSAI2
Definition: stm32l4xx_hal_rcc_ex.h:132
RCC_PeriphCLKInitTypeDef::Usart3ClockSelection
uint32_t Usart3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:145
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:194
RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:219

◆ HAL_RCCEx_GetPeriphCLKFreq()

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t  PeriphClk)

Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.

Note
Return 0 if peripheral clock identifier not managed by this API
Parameters
PeriphClkPeripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1)
  • RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART1 peripheral clock
  • RCC_PERIPHCLK_USART3 USART1 peripheral clock
Return values
Frequencyin Hz

Definition at line 1152 of file stm32l4xx_hal_rcc_ex.c.

1153 {
1154  uint32_t frequency = 0U;
1155  uint32_t srcclk, pll_oscsource, pllvco, plln; /* no init needed */
1156 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)
1157  uint32_t pllp; /* no init needed */
1158 #endif
1159 
1160  /* Check the parameters */
1161  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
1162 
1163  if(PeriphClk == RCC_PERIPHCLK_RTC)
1164  {
1165  /* Get the current RTC source */
1166  srcclk = __HAL_RCC_GET_RTC_SOURCE();
1167 
1168  switch(srcclk)
1169  {
1170  case RCC_RTCCLKSOURCE_LSE:
1171  /* Check if LSE is ready */
1172  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1173  {
1174  frequency = LSE_VALUE;
1175  }
1176  break;
1177  case RCC_RTCCLKSOURCE_LSI:
1178  /* Check if LSI is ready */
1179  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
1180  {
1181 #if defined(RCC_CSR_LSIPREDIV)
1182  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
1183  {
1184  frequency = LSI_VALUE/128U;
1185  }
1186  else
1187 #endif /* RCC_CSR_LSIPREDIV */
1188  {
1189  frequency = LSI_VALUE;
1190  }
1191  }
1192  break;
1193  case RCC_RTCCLKSOURCE_HSE_DIV32:
1194  /* Check if HSE is ready */
1195  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1196  {
1197  frequency = HSE_VALUE / 32U;
1198  }
1199  break;
1200  default:
1201  /* No clock source, frequency default init at 0 */
1202  break;
1203  }
1204  }
1205  else
1206  {
1207  /* Other external peripheral clock source than RTC */
1208  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
1209 
1210  /* Compute PLL clock input */
1211  switch(pll_oscsource)
1212  {
1213  case RCC_PLLSOURCE_MSI: /* MSI ? */
1214  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1215  {
1216  /*MSI frequency range in HZ*/
1217  pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1218  }
1219  else
1220  {
1221  pllvco = 0U;
1222  }
1223  break;
1224  case RCC_PLLSOURCE_HSI: /* HSI ? */
1225  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1226  {
1227  pllvco = HSI_VALUE;
1228  }
1229  else
1230  {
1231  pllvco = 0U;
1232  }
1233  break;
1234  case RCC_PLLSOURCE_HSE: /* HSE ? */
1235  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1236  {
1237  pllvco = HSE_VALUE;
1238  }
1239  else
1240  {
1241  pllvco = 0U;
1242  }
1243  break;
1244  default:
1245  /* No source */
1246  pllvco = 0U;
1247  break;
1248  }
1249 
1250  switch(PeriphClk)
1251  {
1252 #if defined(SAI1)
1253 
1254  case RCC_PERIPHCLK_SAI1:
1255  frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);
1256  break;
1257 
1258 #endif
1259 
1260 #if defined(SAI2)
1261 
1262  case RCC_PERIPHCLK_SAI2:
1263  frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco);
1264  break;
1265 
1266 #endif
1267 
1268 #if defined(USB_OTG_FS) || defined(USB)
1269 
1270  case RCC_PERIPHCLK_USB:
1271 
1272 #endif /* USB_OTG_FS || USB */
1273 
1274  case RCC_PERIPHCLK_RNG:
1275 
1276 #if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL)
1277 
1278  case RCC_PERIPHCLK_SDMMC1:
1279 
1280 #endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */
1281  {
1282  srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
1283 
1284  switch(srcclk)
1285  {
1286  case RCC_CCIPR_CLK48SEL: /* MSI ? */
1287  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1288  {
1289  /*MSI frequency range in HZ*/
1290  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1291  }
1292  break;
1293  case RCC_CCIPR_CLK48SEL_1: /* PLL ? */
1294  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1295  {
1296  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
1297  {
1298  /* f(PLL Source) * PLLN / PLLM */
1299  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1300  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1301  /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
1302  frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
1303  }
1304  }
1305  break;
1306 #if defined(RCC_PLLSAI1_SUPPORT)
1307  case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */
1308  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))
1309  {
1310  if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
1311  {
1312  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
1313 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1314  /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
1315  /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
1316  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
1317 #else
1318  /* f(PLL Source) * PLLSAI1N / PLLM */
1319  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1320 #endif
1321  /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */
1322  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));
1323  }
1324  }
1325  break;
1326 #endif /* RCC_PLLSAI1_SUPPORT */
1327 #if defined(RCC_HSI48_SUPPORT)
1328  case 0U:
1329  if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */
1330  {
1331  frequency = HSI48_VALUE;
1332  }
1333  break;
1334 #endif /* RCC_HSI48_SUPPORT */
1335  default:
1336  /* No clock source, frequency default init at 0 */
1337  break;
1338  } /* switch(srcclk) */
1339  break;
1340  }
1341 
1342 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)
1343 
1344  case RCC_PERIPHCLK_SDMMC1:
1345 
1346  if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */
1347  {
1348  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1349  {
1350  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN))
1351  {
1352  /* f(PLL Source) * PLLN / PLLM */
1353  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1354  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1355  /* f(PLLSAI3CLK) = f(VCO input) / PLLP */
1356  pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
1357  if(pllp == 0U)
1358  {
1359  if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
1360  {
1361  pllp = 17U;
1362  }
1363  else
1364  {
1365  pllp = 7U;
1366  }
1367  }
1368  frequency = (pllvco / pllp);
1369  }
1370  }
1371  }
1372  else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */
1373  {
1374  srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
1375 
1376  switch(srcclk)
1377  {
1378  case RCC_CCIPR_CLK48SEL: /* MSI ? */
1379  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1380  {
1381  /*MSI frequency range in HZ*/
1382  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1383  }
1384  break;
1385  case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */
1386  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1387  {
1388  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
1389  {
1390  /* f(PLL Source) * PLLN / PLLM */
1391  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1392  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1393  /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
1394  frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
1395  }
1396  }
1397  break;
1398  case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */
1399  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))
1400  {
1401  if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
1402  {
1403  /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
1404  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
1405  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
1406  /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */
1407  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));
1408  }
1409  }
1410  break;
1411  case 0U:
1412  if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */
1413  {
1414  frequency = HSI48_VALUE;
1415  }
1416  break;
1417  default:
1418  /* No clock source, frequency default init at 0 */
1419  break;
1420  } /* switch(srcclk) */
1421  }
1422  break;
1423 
1424 #endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */
1425 
1426  case RCC_PERIPHCLK_USART1:
1427  {
1428  /* Get the current USART1 source */
1429  srcclk = __HAL_RCC_GET_USART1_SOURCE();
1430 
1431  switch(srcclk)
1432  {
1433  case RCC_USART1CLKSOURCE_PCLK2:
1434  frequency = HAL_RCC_GetPCLK2Freq();
1435  break;
1436  case RCC_USART1CLKSOURCE_SYSCLK:
1437  frequency = HAL_RCC_GetSysClockFreq();
1438  break;
1439  case RCC_USART1CLKSOURCE_HSI:
1440  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1441  {
1442  frequency = HSI_VALUE;
1443  }
1444  break;
1445  case RCC_USART1CLKSOURCE_LSE:
1446  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1447  {
1448  frequency = LSE_VALUE;
1449  }
1450  break;
1451  default:
1452  /* No clock source, frequency default init at 0 */
1453  break;
1454  }
1455 
1456  break;
1457  }
1458 
1459  case RCC_PERIPHCLK_USART2:
1460  {
1461  /* Get the current USART2 source */
1462  srcclk = __HAL_RCC_GET_USART2_SOURCE();
1463 
1464  switch(srcclk)
1465  {
1466  case RCC_USART2CLKSOURCE_PCLK1:
1467  frequency = HAL_RCC_GetPCLK1Freq();
1468  break;
1469  case RCC_USART2CLKSOURCE_SYSCLK:
1470  frequency = HAL_RCC_GetSysClockFreq();
1471  break;
1472  case RCC_USART2CLKSOURCE_HSI:
1473  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1474  {
1475  frequency = HSI_VALUE;
1476  }
1477  break;
1478  case RCC_USART2CLKSOURCE_LSE:
1479  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1480  {
1481  frequency = LSE_VALUE;
1482  }
1483  break;
1484  default:
1485  /* No clock source, frequency default init at 0 */
1486  break;
1487  }
1488 
1489  break;
1490  }
1491 
1492 #if defined(USART3)
1493 
1494  case RCC_PERIPHCLK_USART3:
1495  {
1496  /* Get the current USART3 source */
1497  srcclk = __HAL_RCC_GET_USART3_SOURCE();
1498 
1499  switch(srcclk)
1500  {
1501  case RCC_USART3CLKSOURCE_PCLK1:
1502  frequency = HAL_RCC_GetPCLK1Freq();
1503  break;
1504  case RCC_USART3CLKSOURCE_SYSCLK:
1505  frequency = HAL_RCC_GetSysClockFreq();
1506  break;
1507  case RCC_USART3CLKSOURCE_HSI:
1508  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1509  {
1510  frequency = HSI_VALUE;
1511  }
1512  break;
1513  case RCC_USART3CLKSOURCE_LSE:
1514  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1515  {
1516  frequency = LSE_VALUE;
1517  }
1518  break;
1519  default:
1520  /* No clock source, frequency default init at 0 */
1521  break;
1522  }
1523 
1524  break;
1525  }
1526 
1527 #endif /* USART3 */
1528 
1529 #if defined(UART4)
1530 
1531  case RCC_PERIPHCLK_UART4:
1532  {
1533  /* Get the current UART4 source */
1534  srcclk = __HAL_RCC_GET_UART4_SOURCE();
1535 
1536  switch(srcclk)
1537  {
1538  case RCC_UART4CLKSOURCE_PCLK1:
1539  frequency = HAL_RCC_GetPCLK1Freq();
1540  break;
1541  case RCC_UART4CLKSOURCE_SYSCLK:
1542  frequency = HAL_RCC_GetSysClockFreq();
1543  break;
1544  case RCC_UART4CLKSOURCE_HSI:
1545  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1546  {
1547  frequency = HSI_VALUE;
1548  }
1549  break;
1550  case RCC_UART4CLKSOURCE_LSE:
1551  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1552  {
1553  frequency = LSE_VALUE;
1554  }
1555  break;
1556  default:
1557  /* No clock source, frequency default init at 0 */
1558  break;
1559  }
1560 
1561  break;
1562  }
1563 
1564 #endif /* UART4 */
1565 
1566 #if defined(UART5)
1567 
1568  case RCC_PERIPHCLK_UART5:
1569  {
1570  /* Get the current UART5 source */
1571  srcclk = __HAL_RCC_GET_UART5_SOURCE();
1572 
1573  switch(srcclk)
1574  {
1575  case RCC_UART5CLKSOURCE_PCLK1:
1576  frequency = HAL_RCC_GetPCLK1Freq();
1577  break;
1578  case RCC_UART5CLKSOURCE_SYSCLK:
1579  frequency = HAL_RCC_GetSysClockFreq();
1580  break;
1581  case RCC_UART5CLKSOURCE_HSI:
1582  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1583  {
1584  frequency = HSI_VALUE;
1585  }
1586  break;
1587  case RCC_UART5CLKSOURCE_LSE:
1588  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1589  {
1590  frequency = LSE_VALUE;
1591  }
1592  break;
1593  default:
1594  /* No clock source, frequency default init at 0 */
1595  break;
1596  }
1597 
1598  break;
1599  }
1600 
1601 #endif /* UART5 */
1602 
1603  case RCC_PERIPHCLK_LPUART1:
1604  {
1605  /* Get the current LPUART1 source */
1606  srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
1607 
1608  switch(srcclk)
1609  {
1610  case RCC_LPUART1CLKSOURCE_PCLK1:
1611  frequency = HAL_RCC_GetPCLK1Freq();
1612  break;
1613  case RCC_LPUART1CLKSOURCE_SYSCLK:
1614  frequency = HAL_RCC_GetSysClockFreq();
1615  break;
1616  case RCC_LPUART1CLKSOURCE_HSI:
1617  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1618  {
1619  frequency = HSI_VALUE;
1620  }
1621  break;
1622  case RCC_LPUART1CLKSOURCE_LSE:
1623  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1624  {
1625  frequency = LSE_VALUE;
1626  }
1627  break;
1628  default:
1629  /* No clock source, frequency default init at 0 */
1630  break;
1631  }
1632 
1633  break;
1634  }
1635 
1636  case RCC_PERIPHCLK_ADC:
1637  {
1638  srcclk = __HAL_RCC_GET_ADC_SOURCE();
1639 
1640  switch(srcclk)
1641  {
1642  case RCC_ADCCLKSOURCE_SYSCLK:
1643  frequency = HAL_RCC_GetSysClockFreq();
1644  break;
1645 #if defined(RCC_PLLSAI1_SUPPORT)
1646  case RCC_ADCCLKSOURCE_PLLSAI1:
1647  if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U)
1648  {
1649  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
1650 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1651  /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
1652  /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
1653  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
1654 #else
1655  /* f(PLL Source) * PLLSAI1N / PLLM */
1656  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1657 #endif
1658  /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */
1659  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U));
1660  }
1661  break;
1662 #endif /* RCC_PLLSAI1_SUPPORT */
1663 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
1664  case RCC_ADCCLKSOURCE_PLLSAI2:
1665  if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U)
1666  {
1667  plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
1668 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1669  /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */
1670  /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */
1671  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));
1672 #else
1673  /* f(PLL Source) * PLLSAI2N / PLLM */
1674  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1675 #endif
1676  /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */
1677  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U));
1678  }
1679  break;
1680 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
1681  default:
1682  /* No clock source, frequency default init at 0 */
1683  break;
1684  }
1685 
1686  break;
1687  }
1688 
1689 #if defined(DFSDM1_Filter0)
1690 
1691  case RCC_PERIPHCLK_DFSDM1:
1692  {
1693  /* Get the current DFSDM1 source */
1694  srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
1695 
1696  if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)
1697  {
1698  frequency = HAL_RCC_GetPCLK2Freq();
1699  }
1700  else
1701  {
1702  frequency = HAL_RCC_GetSysClockFreq();
1703  }
1704 
1705  break;
1706  }
1707 
1708 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1709 
1710  case RCC_PERIPHCLK_DFSDM1AUDIO:
1711  {
1712  /* Get the current DFSDM1 audio source */
1713  srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
1714 
1715  switch(srcclk)
1716  {
1717  case RCC_DFSDM1AUDIOCLKSOURCE_SAI1:
1718  frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);
1719  break;
1720  case RCC_DFSDM1AUDIOCLKSOURCE_MSI:
1721  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1722  {
1723  /*MSI frequency range in HZ*/
1724  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1725  }
1726  break;
1727  case RCC_DFSDM1AUDIOCLKSOURCE_HSI:
1728  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1729  {
1730  frequency = HSI_VALUE;
1731  }
1732  break;
1733  default:
1734  /* No clock source, frequency default init at 0 */
1735  break;
1736  }
1737 
1738  break;
1739  }
1740 
1741 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1742 
1743 #endif /* DFSDM1_Filter0 */
1744 
1745  case RCC_PERIPHCLK_I2C1:
1746  {
1747  /* Get the current I2C1 source */
1748  srcclk = __HAL_RCC_GET_I2C1_SOURCE();
1749 
1750  switch(srcclk)
1751  {
1752  case RCC_I2C1CLKSOURCE_PCLK1:
1753  frequency = HAL_RCC_GetPCLK1Freq();
1754  break;
1755  case RCC_I2C1CLKSOURCE_SYSCLK:
1756  frequency = HAL_RCC_GetSysClockFreq();
1757  break;
1758  case RCC_I2C1CLKSOURCE_HSI:
1759  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1760  {
1761  frequency = HSI_VALUE;
1762  }
1763  break;
1764  default:
1765  /* No clock source, frequency default init at 0 */
1766  break;
1767  }
1768 
1769  break;
1770  }
1771 
1772 #if defined(I2C2)
1773 
1774  case RCC_PERIPHCLK_I2C2:
1775  {
1776  /* Get the current I2C2 source */
1777  srcclk = __HAL_RCC_GET_I2C2_SOURCE();
1778 
1779  switch(srcclk)
1780  {
1781  case RCC_I2C2CLKSOURCE_PCLK1:
1782  frequency = HAL_RCC_GetPCLK1Freq();
1783  break;
1784  case RCC_I2C2CLKSOURCE_SYSCLK:
1785  frequency = HAL_RCC_GetSysClockFreq();
1786  break;
1787  case RCC_I2C2CLKSOURCE_HSI:
1788  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1789  {
1790  frequency = HSI_VALUE;
1791  }
1792  break;
1793  default:
1794  /* No clock source, frequency default init at 0 */
1795  break;
1796  }
1797 
1798  break;
1799  }
1800 
1801 #endif /* I2C2 */
1802 
1803  case RCC_PERIPHCLK_I2C3:
1804  {
1805  /* Get the current I2C3 source */
1806  srcclk = __HAL_RCC_GET_I2C3_SOURCE();
1807 
1808  switch(srcclk)
1809  {
1810  case RCC_I2C3CLKSOURCE_PCLK1:
1811  frequency = HAL_RCC_GetPCLK1Freq();
1812  break;
1813  case RCC_I2C3CLKSOURCE_SYSCLK:
1814  frequency = HAL_RCC_GetSysClockFreq();
1815  break;
1816  case RCC_I2C3CLKSOURCE_HSI:
1817  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1818  {
1819  frequency = HSI_VALUE;
1820  }
1821  break;
1822  default:
1823  /* No clock source, frequency default init at 0 */
1824  break;
1825  }
1826 
1827  break;
1828  }
1829 
1830 #if defined(I2C4)
1831 
1832  case RCC_PERIPHCLK_I2C4:
1833  {
1834  /* Get the current I2C4 source */
1835  srcclk = __HAL_RCC_GET_I2C4_SOURCE();
1836 
1837  switch(srcclk)
1838  {
1839  case RCC_I2C4CLKSOURCE_PCLK1:
1840  frequency = HAL_RCC_GetPCLK1Freq();
1841  break;
1842  case RCC_I2C4CLKSOURCE_SYSCLK:
1843  frequency = HAL_RCC_GetSysClockFreq();
1844  break;
1845  case RCC_I2C4CLKSOURCE_HSI:
1846  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1847  {
1848  frequency = HSI_VALUE;
1849  }
1850  break;
1851  default:
1852  /* No clock source, frequency default init at 0 */
1853  break;
1854  }
1855 
1856  break;
1857  }
1858 
1859 #endif /* I2C4 */
1860 
1861  case RCC_PERIPHCLK_LPTIM1:
1862  {
1863  /* Get the current LPTIM1 source */
1864  srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
1865 
1866  switch(srcclk)
1867  {
1868  case RCC_LPTIM1CLKSOURCE_PCLK1:
1869  frequency = HAL_RCC_GetPCLK1Freq();
1870  break;
1871  case RCC_LPTIM1CLKSOURCE_LSI:
1872  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
1873  {
1874 #if defined(RCC_CSR_LSIPREDIV)
1875  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
1876  {
1877  frequency = LSI_VALUE/128U;
1878  }
1879  else
1880 #endif /* RCC_CSR_LSIPREDIV */
1881  {
1882  frequency = LSI_VALUE;
1883  }
1884  }
1885  break;
1886  case RCC_LPTIM1CLKSOURCE_HSI:
1887  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1888  {
1889  frequency = HSI_VALUE;
1890  }
1891  break;
1892  case RCC_LPTIM1CLKSOURCE_LSE:
1893  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1894  {
1895  frequency = LSE_VALUE;
1896  }
1897  break;
1898  default:
1899  /* No clock source, frequency default init at 0 */
1900  break;
1901  }
1902 
1903  break;
1904  }
1905 
1906  case RCC_PERIPHCLK_LPTIM2:
1907  {
1908  /* Get the current LPTIM2 source */
1909  srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
1910 
1911  switch(srcclk)
1912  {
1913  case RCC_LPTIM2CLKSOURCE_PCLK1:
1914  frequency = HAL_RCC_GetPCLK1Freq();
1915  break;
1916  case RCC_LPTIM2CLKSOURCE_LSI:
1917  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
1918  {
1919 #if defined(RCC_CSR_LSIPREDIV)
1920  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
1921  {
1922  frequency = LSI_VALUE/128U;
1923  }
1924  else
1925 #endif /* RCC_CSR_LSIPREDIV */
1926  {
1927  frequency = LSI_VALUE;
1928  }
1929  }
1930  break;
1931  case RCC_LPTIM2CLKSOURCE_HSI:
1932  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1933  {
1934  frequency = HSI_VALUE;
1935  }
1936  break;
1937  case RCC_LPTIM2CLKSOURCE_LSE:
1938  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1939  {
1940  frequency = LSE_VALUE;
1941  }
1942  break;
1943  default:
1944  /* No clock source, frequency default init at 0 */
1945  break;
1946  }
1947 
1948  break;
1949  }
1950 
1951 #if defined(SWPMI1)
1952 
1953  case RCC_PERIPHCLK_SWPMI1:
1954  {
1955  /* Get the current SWPMI1 source */
1956  srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
1957 
1958  switch(srcclk)
1959  {
1960  case RCC_SWPMI1CLKSOURCE_PCLK1:
1961  frequency = HAL_RCC_GetPCLK1Freq();
1962  break;
1963  case RCC_SWPMI1CLKSOURCE_HSI:
1964  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1965  {
1966  frequency = HSI_VALUE;
1967  }
1968  break;
1969  default:
1970  /* No clock source, frequency default init at 0 */
1971  break;
1972  }
1973 
1974  break;
1975  }
1976 
1977 #endif /* SWPMI1 */
1978 
1979 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1980 
1981  case RCC_PERIPHCLK_OSPI:
1982  {
1983  /* Get the current OctoSPI clock source */
1984  srcclk = __HAL_RCC_GET_OSPI_SOURCE();
1985 
1986  switch(srcclk)
1987  {
1988  case RCC_OSPICLKSOURCE_SYSCLK:
1989  frequency = HAL_RCC_GetSysClockFreq();
1990  break;
1991  case RCC_OSPICLKSOURCE_MSI:
1992  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1993  {
1994  /*MSI frequency range in HZ*/
1995  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1996  }
1997  break;
1998  case RCC_OSPICLKSOURCE_PLL:
1999  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
2000  {
2001  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
2002  {
2003  /* f(PLL Source) * PLLN / PLLM */
2004  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
2005  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
2006  /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
2007  frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
2008  }
2009  }
2010  break;
2011  default:
2012  /* No clock source, frequency default init at 0 */
2013  break;
2014  }
2015 
2016  break;
2017  }
2018 
2019 #endif /* OCTOSPI1 || OCTOSPI2 */
2020 
2021  default:
2022  break;
2023  }
2024  }
2025 
2026  return(frequency);
2027 }
PeriphClk
__STATIC_INLINE void uint32_t PeriphClk
Definition: stm32l4xx_ll_lpuart.h:1431
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
Return the PCLK2 frequency.
Definition: stm32l4xx_hal_rcc.c:1457
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
Return the SYSCLK frequency.
Definition: stm32l4xx_hal_rcc.c:1346
RCCEx_GetSAIxPeriphCLKFreq
static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)
Definition: stm32l4xx_hal_rcc_ex.c:3290
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
Return the PCLK1 frequency.
Definition: stm32l4xx_hal_rcc.c:1445
assert_param
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock))

◆ HAL_RCCEx_PeriphCLKConfig()

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef *  PeriphClkInit)

Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters
PeriphClkInitpointer to an RCC_PeriphCLKInitTypeDef structure that contains a field PeriphClockSelection which can be a combination of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
  • RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
  • RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
  • RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
  • RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
  • RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
  • RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
  • RCC_PERIPHCLK_RNG RNG peripheral clock
  • RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (only for devices with SAI1)
  • RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock
  • RCC_PERIPHCLK_USART1 USART1 peripheral clock
  • RCC_PERIPHCLK_USART2 USART1 peripheral clock
  • RCC_PERIPHCLK_USART3 USART1 peripheral clock
Note
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source: in this case the access to Backup domain is enabled.
Return values
HALstatus

Definition at line 196 of file stm32l4xx_hal_rcc_ex.c.

197 {
198  uint32_t tmpregister, tickstart; /* no init needed */
199  HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
200  HAL_StatusTypeDef status = HAL_OK; /* Final status */
201 
202  /* Check the parameters */
203  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
204 
205 #if defined(SAI1)
206 
207  /*-------------------------- SAI1 clock source configuration ---------------------*/
208  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
209  {
210  /* Check the parameters */
211  assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
212 
213  switch(PeriphClkInit->Sai1ClockSelection)
214  {
215  case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
216  /* Enable SAI Clock output generated form System PLL . */
217 #if defined(RCC_PLLSAI2_SUPPORT)
218  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
219 #else
220  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
221 #endif /* RCC_PLLSAI2_SUPPORT */
222  /* SAI1 clock source config set later after clock selection check */
223  break;
224 
225  case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
226  /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
227  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
228  /* SAI1 clock source config set later after clock selection check */
229  break;
230 
231 #if defined(RCC_PLLSAI2_SUPPORT)
232 
233  case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
234  /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
235  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
236  /* SAI1 clock source config set later after clock selection check */
237  break;
238 
239 #endif /* RCC_PLLSAI2_SUPPORT */
240 
241  case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
242 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
243  case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
244 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
245  /* SAI1 clock source config set later after clock selection check */
246  break;
247 
248  default:
249  ret = HAL_ERROR;
250  break;
251  }
252 
253  if(ret == HAL_OK)
254  {
255  /* Set the source of SAI1 clock*/
256  __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
257  }
258  else
259  {
260  /* set overall return value */
261  status = ret;
262  }
263  }
264 
265 #endif /* SAI1 */
266 
267 #if defined(SAI2)
268 
269  /*-------------------------- SAI2 clock source configuration ---------------------*/
270  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
271  {
272  /* Check the parameters */
273  assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
274 
275  switch(PeriphClkInit->Sai2ClockSelection)
276  {
277  case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
278  /* Enable SAI Clock output generated form System PLL . */
279  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
280  /* SAI2 clock source config set later after clock selection check */
281  break;
282 
283  case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
284  /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
285  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
286  /* SAI2 clock source config set later after clock selection check */
287  break;
288 
289  case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
290  /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
291  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
292  /* SAI2 clock source config set later after clock selection check */
293  break;
294 
295  case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
296 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
297  case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
298 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
299  /* SAI2 clock source config set later after clock selection check */
300  break;
301 
302  default:
303  ret = HAL_ERROR;
304  break;
305  }
306 
307  if(ret == HAL_OK)
308  {
309  /* Set the source of SAI2 clock*/
310  __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
311  }
312  else
313  {
314  /* set overall return value */
315  status = ret;
316  }
317  }
318 #endif /* SAI2 */
319 
320  /*-------------------------- RTC clock source configuration ----------------------*/
321  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
322  {
323  FlagStatus pwrclkchanged = RESET;
324 
325  /* Check for RTC Parameters used to output RTCCLK */
326  assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
327 
328  /* Enable Power Clock */
329  if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
330  {
331  __HAL_RCC_PWR_CLK_ENABLE();
332  pwrclkchanged = SET;
333  }
334 
335  /* Enable write access to Backup domain */
336  SET_BIT(PWR->CR1, PWR_CR1_DBP);
337 
338  /* Wait for Backup domain Write protection disable */
339  tickstart = HAL_GetTick();
340 
341  while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
342  {
343  if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
344  {
345  ret = HAL_TIMEOUT;
346  break;
347  }
348  }
349 
350  if(ret == HAL_OK)
351  {
352  /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
353  tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
354 
355  if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
356  {
357  /* Store the content of BDCR register before the reset of Backup Domain */
358  tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
359  /* RTC Clock selection can be changed only if the Backup Domain is reset */
360  __HAL_RCC_BACKUPRESET_FORCE();
361  __HAL_RCC_BACKUPRESET_RELEASE();
362  /* Restore the Content of BDCR register */
363  RCC->BDCR = tmpregister;
364  }
365 
366  /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
367  if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
368  {
369  /* Get Start Tick*/
370  tickstart = HAL_GetTick();
371 
372  /* Wait till LSE is ready */
373  while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
374  {
375  if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
376  {
377  ret = HAL_TIMEOUT;
378  break;
379  }
380  }
381  }
382 
383  if(ret == HAL_OK)
384  {
385  /* Apply new RTC clock source selection */
386  __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
387  }
388  else
389  {
390  /* set overall return value */
391  status = ret;
392  }
393  }
394  else
395  {
396  /* set overall return value */
397  status = ret;
398  }
399 
400  /* Restore clock configuration if changed */
401  if(pwrclkchanged == SET)
402  {
403  __HAL_RCC_PWR_CLK_DISABLE();
404  }
405  }
406 
407  /*-------------------------- USART1 clock source configuration -------------------*/
408  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
409  {
410  /* Check the parameters */
411  assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
412 
413  /* Configure the USART1 clock source */
414  __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
415  }
416 
417  /*-------------------------- USART2 clock source configuration -------------------*/
418  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
419  {
420  /* Check the parameters */
421  assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
422 
423  /* Configure the USART2 clock source */
424  __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
425  }
426 
427 #if defined(USART3)
428 
429  /*-------------------------- USART3 clock source configuration -------------------*/
430  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
431  {
432  /* Check the parameters */
433  assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
434 
435  /* Configure the USART3 clock source */
436  __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
437  }
438 
439 #endif /* USART3 */
440 
441 #if defined(UART4)
442 
443  /*-------------------------- UART4 clock source configuration --------------------*/
444  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
445  {
446  /* Check the parameters */
447  assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
448 
449  /* Configure the UART4 clock source */
450  __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
451  }
452 
453 #endif /* UART4 */
454 
455 #if defined(UART5)
456 
457  /*-------------------------- UART5 clock source configuration --------------------*/
458  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
459  {
460  /* Check the parameters */
461  assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
462 
463  /* Configure the UART5 clock source */
464  __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
465  }
466 
467 #endif /* UART5 */
468 
469  /*-------------------------- LPUART1 clock source configuration ------------------*/
470  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
471  {
472  /* Check the parameters */
473  assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
474 
475  /* Configure the LPUAR1 clock source */
476  __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
477  }
478 
479  /*-------------------------- LPTIM1 clock source configuration -------------------*/
480  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
481  {
482  assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
483  __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
484  }
485 
486  /*-------------------------- LPTIM2 clock source configuration -------------------*/
487  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
488  {
489  assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
490  __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
491  }
492 
493  /*-------------------------- I2C1 clock source configuration ---------------------*/
494  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
495  {
496  /* Check the parameters */
497  assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
498 
499  /* Configure the I2C1 clock source */
500  __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
501  }
502 
503 #if defined(I2C2)
504 
505  /*-------------------------- I2C2 clock source configuration ---------------------*/
506  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
507  {
508  /* Check the parameters */
509  assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
510 
511  /* Configure the I2C2 clock source */
512  __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
513  }
514 
515 #endif /* I2C2 */
516 
517  /*-------------------------- I2C3 clock source configuration ---------------------*/
518  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
519  {
520  /* Check the parameters */
521  assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
522 
523  /* Configure the I2C3 clock source */
524  __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
525  }
526 
527 #if defined(I2C4)
528 
529  /*-------------------------- I2C4 clock source configuration ---------------------*/
530  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
531  {
532  /* Check the parameters */
533  assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
534 
535  /* Configure the I2C4 clock source */
536  __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
537  }
538 
539 #endif /* I2C4 */
540 
541 #if defined(USB_OTG_FS) || defined(USB)
542 
543  /*-------------------------- USB clock source configuration ----------------------*/
544  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
545  {
546  assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
547  __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
548 
549  if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
550  {
551  /* Enable PLL48M1CLK output */
552  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
553  }
554  else
555  {
556 #if defined(RCC_PLLSAI1_SUPPORT)
557  if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
558  {
559  /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
560  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
561 
562  if(ret != HAL_OK)
563  {
564  /* set overall return value */
565  status = ret;
566  }
567  }
568 #endif /* RCC_PLLSAI1_SUPPORT */
569  }
570  }
571 
572 #endif /* USB_OTG_FS || USB */
573 
574 #if defined(SDMMC1)
575 
576  /*-------------------------- SDMMC1 clock source configuration -------------------*/
577  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
578  {
579  assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
580  __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
581 
582  if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
583  {
584  /* Enable PLL48M1CLK output */
585  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
586  }
587 #if defined(RCC_CCIPR2_SDMMCSEL)
588  else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */
589  {
590  /* Enable PLLSAI3CLK output */
591  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
592  }
593 #endif
594  else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
595  {
596  /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
597  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
598 
599  if(ret != HAL_OK)
600  {
601  /* set overall return value */
602  status = ret;
603  }
604  }
605  else
606  {
607  /* nothing to do */
608  }
609  }
610 
611 #endif /* SDMMC1 */
612 
613  /*-------------------------- RNG clock source configuration ----------------------*/
614  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
615  {
616  assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
617  __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
618 
619  if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
620  {
621  /* Enable PLL48M1CLK output */
622  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
623  }
624 #if defined(RCC_PLLSAI1_SUPPORT)
625  else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
626  {
627  /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
628  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
629 
630  if(ret != HAL_OK)
631  {
632  /* set overall return value */
633  status = ret;
634  }
635  }
636 #endif /* RCC_PLLSAI1_SUPPORT */
637  else
638  {
639  /* nothing to do */
640  }
641  }
642 
643  /*-------------------------- ADC clock source configuration ----------------------*/
644 #if !defined(STM32L412xx) && !defined(STM32L422xx)
645  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
646  {
647  /* Check the parameters */
648  assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
649 
650  /* Configure the ADC interface clock source */
651  __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
652 
653 #if defined(RCC_PLLSAI1_SUPPORT)
654  if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
655  {
656  /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
657  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
658 
659  if(ret != HAL_OK)
660  {
661  /* set overall return value */
662  status = ret;
663  }
664  }
665 #endif /* RCC_PLLSAI1_SUPPORT */
666 
667 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
668 
669  else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
670  {
671  /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
672  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
673 
674  if(ret != HAL_OK)
675  {
676  /* set overall return value */
677  status = ret;
678  }
679  }
680 
681 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
682 
683  }
684 #endif /* !STM32L412xx && !STM32L422xx */
685 
686 #if defined(SWPMI1)
687 
688  /*-------------------------- SWPMI1 clock source configuration -------------------*/
689  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
690  {
691  /* Check the parameters */
692  assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
693 
694  /* Configure the SWPMI1 clock source */
695  __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
696  }
697 
698 #endif /* SWPMI1 */
699 
700 #if defined(DFSDM1_Filter0)
701 
702  /*-------------------------- DFSDM1 clock source configuration -------------------*/
703  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
704  {
705  /* Check the parameters */
706  assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
707 
708  /* Configure the DFSDM1 interface clock source */
709  __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
710  }
711 
712 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
713  /*-------------------------- DFSDM1 audio clock source configuration -------------*/
714  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO)
715  {
716  /* Check the parameters */
717  assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
718 
719  /* Configure the DFSDM1 interface audio clock source */
720  __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
721  }
722 
723 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
724 
725 #endif /* DFSDM1_Filter0 */
726 
727 #if defined(LTDC)
728 
729  /*-------------------------- LTDC clock source configuration --------------------*/
730  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
731  {
732  /* Check the parameters */
733  assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));
734 
735  /* Disable the PLLSAI2 */
736  __HAL_RCC_PLLSAI2_DISABLE();
737 
738  /* Get Start Tick*/
739  tickstart = HAL_GetTick();
740 
741  /* Wait till PLLSAI2 is ready */
742  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
743  {
744  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
745  {
746  ret = HAL_TIMEOUT;
747  break;
748  }
749  }
750 
751  if(ret == HAL_OK)
752  {
753  /* Configure the LTDC clock source */
754  __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);
755 
756  /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
757  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
758  }
759 
760  if(ret != HAL_OK)
761  {
762  /* set overall return value */
763  status = ret;
764  }
765  }
766 
767 #endif /* LTDC */
768 
769 #if defined(DSI)
770 
771  /*-------------------------- DSI clock source configuration ---------------------*/
772  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
773  {
774  /* Check the parameters */
775  assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));
776 
777  /* Configure the DSI clock source */
778  __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
779 
780  if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2)
781  {
782  /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */
783  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE);
784 
785  if(ret != HAL_OK)
786  {
787  /* set overall return value */
788  status = ret;
789  }
790  }
791  }
792 
793 #endif /* DSI */
794 
795 #if defined(OCTOSPI1) || defined(OCTOSPI2)
796 
797  /*-------------------------- OctoSPIx clock source configuration ----------------*/
798  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
799  {
800  /* Check the parameters */
801  assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection));
802 
803  /* Configure the OctoSPI clock source */
804  __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
805 
806  if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL)
807  {
808  /* Enable PLL48M1CLK output */
809  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
810  }
811  }
812 
813 #endif /* OCTOSPI1 || OCTOSPI2 */
814 
815  return status;
816 }
RCC_PeriphCLKInitTypeDef::I2c2ClockSelection
uint32_t I2c2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:172
RCC_PeriphCLKInitTypeDef::OspiClockSelection
uint32_t OspiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:263
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:123
RCC_PeriphCLKInitTypeDef::Uart4ClockSelection
uint32_t Uart4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:152
RCC_PeriphCLKInitTypeDef::Sai2ClockSelection
uint32_t Sai2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:200
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:223
RCC_PeriphCLKInitTypeDef::I2c1ClockSelection
uint32_t I2c1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:167
RCC_PeriphCLKInitTypeDef::I2c3ClockSelection
uint32_t I2c3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:177
RCC_PeriphCLKInitTypeDef::PLLSAI1
RCC_PLLSAI1InitTypeDef PLLSAI1
Definition: stm32l4xx_hal_rcc_ex.h:127
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:182
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:229
RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:164
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
RCC_PeriphCLKInitTypeDef::Usart1ClockSelection
uint32_t Usart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:137
RCC_PeriphCLKInitTypeDef::Uart5ClockSelection
uint32_t Uart5ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:159
RCC_PeriphCLKInitTypeDef::Dfsdm1AudioClockSelection
uint32_t Dfsdm1AudioClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:240
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:236
RCCEx_PLLSAI2_Config
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s)...
Definition: stm32l4xx_hal_rcc_ex.c:3093
RCC_PeriphCLKInitTypeDef::Usart2ClockSelection
uint32_t Usart2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:140
RCCEx_PLLSAI1_Config
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s)...
Definition: stm32l4xx_hal_rcc_ex.c:2888
RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:190
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:187
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:268
RCC_PeriphCLKInitTypeDef::LtdcClockSelection
uint32_t LtdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:249
RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection
uint32_t Sdmmc1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:214
RCC_PeriphCLKInitTypeDef::DsiClockSelection
uint32_t DsiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:256
RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:207
RCC_PeriphCLKInitTypeDef::PLLSAI2
RCC_PLLSAI2InitTypeDef PLLSAI2
Definition: stm32l4xx_hal_rcc_ex.h:132
RCC_PeriphCLKInitTypeDef::Usart3ClockSelection
uint32_t Usart3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:145
assert_param
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock))
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:194
RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:219