STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_rcc_ex.c
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1 
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32l4xx_hal.h"
28 
38 #ifdef HAL_RCC_MODULE_ENABLED
39 
40 /* Private typedef -----------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
45 #define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
46 #define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
47 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
48 
49 #define DIVIDER_P_UPDATE 0U
50 #define DIVIDER_Q_UPDATE 1U
51 #define DIVIDER_R_UPDATE 2U
52 
53 #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
54 #define LSCO_GPIO_PORT GPIOA
55 #define LSCO_PIN GPIO_PIN_2
56 
60 /* Private macros ------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private function prototypes -----------------------------------------------*/
66 #if defined(RCC_PLLSAI1_SUPPORT)
67 
68 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider);
69 
70 #endif /* RCC_PLLSAI1_SUPPORT */
71 
72 #if defined(RCC_PLLSAI2_SUPPORT)
73 
74 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider);
75 
76 #endif /* RCC_PLLSAI2_SUPPORT */
77 
78 #if defined(SAI1)
79 
80 static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency);
81 
82 #endif /* SAI1 */
83 
87 /* Exported functions --------------------------------------------------------*/
88 
196 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
197 {
198  uint32_t tmpregister, tickstart; /* no init needed */
199  HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
200  HAL_StatusTypeDef status = HAL_OK; /* Final status */
201 
202  /* Check the parameters */
203  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
204 
205 #if defined(SAI1)
206 
207  /*-------------------------- SAI1 clock source configuration ---------------------*/
208  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
209  {
210  /* Check the parameters */
211  assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
212 
213  switch(PeriphClkInit->Sai1ClockSelection)
214  {
215  case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
216  /* Enable SAI Clock output generated form System PLL . */
217 #if defined(RCC_PLLSAI2_SUPPORT)
218  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
219 #else
220  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
221 #endif /* RCC_PLLSAI2_SUPPORT */
222  /* SAI1 clock source config set later after clock selection check */
223  break;
224 
225  case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
226  /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
227  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
228  /* SAI1 clock source config set later after clock selection check */
229  break;
230 
231 #if defined(RCC_PLLSAI2_SUPPORT)
232 
233  case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
234  /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
235  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
236  /* SAI1 clock source config set later after clock selection check */
237  break;
238 
239 #endif /* RCC_PLLSAI2_SUPPORT */
240 
241  case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
242 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
243  case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
244 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
245  /* SAI1 clock source config set later after clock selection check */
246  break;
247 
248  default:
249  ret = HAL_ERROR;
250  break;
251  }
252 
253  if(ret == HAL_OK)
254  {
255  /* Set the source of SAI1 clock*/
256  __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
257  }
258  else
259  {
260  /* set overall return value */
261  status = ret;
262  }
263  }
264 
265 #endif /* SAI1 */
266 
267 #if defined(SAI2)
268 
269  /*-------------------------- SAI2 clock source configuration ---------------------*/
270  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
271  {
272  /* Check the parameters */
273  assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
274 
275  switch(PeriphClkInit->Sai2ClockSelection)
276  {
277  case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
278  /* Enable SAI Clock output generated form System PLL . */
279  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
280  /* SAI2 clock source config set later after clock selection check */
281  break;
282 
283  case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
284  /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
285  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
286  /* SAI2 clock source config set later after clock selection check */
287  break;
288 
289  case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
290  /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
291  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
292  /* SAI2 clock source config set later after clock selection check */
293  break;
294 
295  case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
296 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
297  case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
298 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
299  /* SAI2 clock source config set later after clock selection check */
300  break;
301 
302  default:
303  ret = HAL_ERROR;
304  break;
305  }
306 
307  if(ret == HAL_OK)
308  {
309  /* Set the source of SAI2 clock*/
310  __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
311  }
312  else
313  {
314  /* set overall return value */
315  status = ret;
316  }
317  }
318 #endif /* SAI2 */
319 
320  /*-------------------------- RTC clock source configuration ----------------------*/
321  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
322  {
323  FlagStatus pwrclkchanged = RESET;
324 
325  /* Check for RTC Parameters used to output RTCCLK */
326  assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
327 
328  /* Enable Power Clock */
329  if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
330  {
331  __HAL_RCC_PWR_CLK_ENABLE();
332  pwrclkchanged = SET;
333  }
334 
335  /* Enable write access to Backup domain */
336  SET_BIT(PWR->CR1, PWR_CR1_DBP);
337 
338  /* Wait for Backup domain Write protection disable */
339  tickstart = HAL_GetTick();
340 
341  while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
342  {
343  if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
344  {
345  ret = HAL_TIMEOUT;
346  break;
347  }
348  }
349 
350  if(ret == HAL_OK)
351  {
352  /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
353  tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
354 
355  if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
356  {
357  /* Store the content of BDCR register before the reset of Backup Domain */
358  tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
359  /* RTC Clock selection can be changed only if the Backup Domain is reset */
360  __HAL_RCC_BACKUPRESET_FORCE();
361  __HAL_RCC_BACKUPRESET_RELEASE();
362  /* Restore the Content of BDCR register */
363  RCC->BDCR = tmpregister;
364  }
365 
366  /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
367  if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
368  {
369  /* Get Start Tick*/
370  tickstart = HAL_GetTick();
371 
372  /* Wait till LSE is ready */
373  while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
374  {
375  if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
376  {
377  ret = HAL_TIMEOUT;
378  break;
379  }
380  }
381  }
382 
383  if(ret == HAL_OK)
384  {
385  /* Apply new RTC clock source selection */
386  __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
387  }
388  else
389  {
390  /* set overall return value */
391  status = ret;
392  }
393  }
394  else
395  {
396  /* set overall return value */
397  status = ret;
398  }
399 
400  /* Restore clock configuration if changed */
401  if(pwrclkchanged == SET)
402  {
403  __HAL_RCC_PWR_CLK_DISABLE();
404  }
405  }
406 
407  /*-------------------------- USART1 clock source configuration -------------------*/
408  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
409  {
410  /* Check the parameters */
411  assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
412 
413  /* Configure the USART1 clock source */
414  __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
415  }
416 
417  /*-------------------------- USART2 clock source configuration -------------------*/
418  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
419  {
420  /* Check the parameters */
421  assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
422 
423  /* Configure the USART2 clock source */
424  __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
425  }
426 
427 #if defined(USART3)
428 
429  /*-------------------------- USART3 clock source configuration -------------------*/
430  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
431  {
432  /* Check the parameters */
433  assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
434 
435  /* Configure the USART3 clock source */
436  __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
437  }
438 
439 #endif /* USART3 */
440 
441 #if defined(UART4)
442 
443  /*-------------------------- UART4 clock source configuration --------------------*/
444  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
445  {
446  /* Check the parameters */
447  assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
448 
449  /* Configure the UART4 clock source */
450  __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
451  }
452 
453 #endif /* UART4 */
454 
455 #if defined(UART5)
456 
457  /*-------------------------- UART5 clock source configuration --------------------*/
458  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
459  {
460  /* Check the parameters */
461  assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
462 
463  /* Configure the UART5 clock source */
464  __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
465  }
466 
467 #endif /* UART5 */
468 
469  /*-------------------------- LPUART1 clock source configuration ------------------*/
470  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
471  {
472  /* Check the parameters */
473  assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
474 
475  /* Configure the LPUAR1 clock source */
476  __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
477  }
478 
479  /*-------------------------- LPTIM1 clock source configuration -------------------*/
480  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
481  {
482  assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
483  __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
484  }
485 
486  /*-------------------------- LPTIM2 clock source configuration -------------------*/
487  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
488  {
489  assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
490  __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
491  }
492 
493  /*-------------------------- I2C1 clock source configuration ---------------------*/
494  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
495  {
496  /* Check the parameters */
497  assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
498 
499  /* Configure the I2C1 clock source */
500  __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
501  }
502 
503 #if defined(I2C2)
504 
505  /*-------------------------- I2C2 clock source configuration ---------------------*/
506  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
507  {
508  /* Check the parameters */
509  assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
510 
511  /* Configure the I2C2 clock source */
512  __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
513  }
514 
515 #endif /* I2C2 */
516 
517  /*-------------------------- I2C3 clock source configuration ---------------------*/
518  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
519  {
520  /* Check the parameters */
521  assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
522 
523  /* Configure the I2C3 clock source */
524  __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
525  }
526 
527 #if defined(I2C4)
528 
529  /*-------------------------- I2C4 clock source configuration ---------------------*/
530  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
531  {
532  /* Check the parameters */
533  assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
534 
535  /* Configure the I2C4 clock source */
536  __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
537  }
538 
539 #endif /* I2C4 */
540 
541 #if defined(USB_OTG_FS) || defined(USB)
542 
543  /*-------------------------- USB clock source configuration ----------------------*/
544  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
545  {
546  assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
547  __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
548 
549  if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
550  {
551  /* Enable PLL48M1CLK output */
552  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
553  }
554  else
555  {
556 #if defined(RCC_PLLSAI1_SUPPORT)
557  if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
558  {
559  /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
560  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
561 
562  if(ret != HAL_OK)
563  {
564  /* set overall return value */
565  status = ret;
566  }
567  }
568 #endif /* RCC_PLLSAI1_SUPPORT */
569  }
570  }
571 
572 #endif /* USB_OTG_FS || USB */
573 
574 #if defined(SDMMC1)
575 
576  /*-------------------------- SDMMC1 clock source configuration -------------------*/
577  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
578  {
579  assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
580  __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
581 
582  if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
583  {
584  /* Enable PLL48M1CLK output */
585  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
586  }
587 #if defined(RCC_CCIPR2_SDMMCSEL)
588  else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */
589  {
590  /* Enable PLLSAI3CLK output */
591  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
592  }
593 #endif
594  else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
595  {
596  /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
597  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
598 
599  if(ret != HAL_OK)
600  {
601  /* set overall return value */
602  status = ret;
603  }
604  }
605  else
606  {
607  /* nothing to do */
608  }
609  }
610 
611 #endif /* SDMMC1 */
612 
613  /*-------------------------- RNG clock source configuration ----------------------*/
614  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
615  {
616  assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
617  __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
618 
619  if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
620  {
621  /* Enable PLL48M1CLK output */
622  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
623  }
624 #if defined(RCC_PLLSAI1_SUPPORT)
625  else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
626  {
627  /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
628  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
629 
630  if(ret != HAL_OK)
631  {
632  /* set overall return value */
633  status = ret;
634  }
635  }
636 #endif /* RCC_PLLSAI1_SUPPORT */
637  else
638  {
639  /* nothing to do */
640  }
641  }
642 
643  /*-------------------------- ADC clock source configuration ----------------------*/
644 #if !defined(STM32L412xx) && !defined(STM32L422xx)
645  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
646  {
647  /* Check the parameters */
648  assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
649 
650  /* Configure the ADC interface clock source */
651  __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
652 
653 #if defined(RCC_PLLSAI1_SUPPORT)
654  if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
655  {
656  /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
657  ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
658 
659  if(ret != HAL_OK)
660  {
661  /* set overall return value */
662  status = ret;
663  }
664  }
665 #endif /* RCC_PLLSAI1_SUPPORT */
666 
667 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
668 
669  else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
670  {
671  /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
672  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
673 
674  if(ret != HAL_OK)
675  {
676  /* set overall return value */
677  status = ret;
678  }
679  }
680 
681 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
682 
683  }
684 #endif /* !STM32L412xx && !STM32L422xx */
685 
686 #if defined(SWPMI1)
687 
688  /*-------------------------- SWPMI1 clock source configuration -------------------*/
689  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
690  {
691  /* Check the parameters */
692  assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
693 
694  /* Configure the SWPMI1 clock source */
695  __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
696  }
697 
698 #endif /* SWPMI1 */
699 
700 #if defined(DFSDM1_Filter0)
701 
702  /*-------------------------- DFSDM1 clock source configuration -------------------*/
703  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
704  {
705  /* Check the parameters */
706  assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
707 
708  /* Configure the DFSDM1 interface clock source */
709  __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
710  }
711 
712 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
713  /*-------------------------- DFSDM1 audio clock source configuration -------------*/
714  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO)
715  {
716  /* Check the parameters */
717  assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
718 
719  /* Configure the DFSDM1 interface audio clock source */
720  __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
721  }
722 
723 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
724 
725 #endif /* DFSDM1_Filter0 */
726 
727 #if defined(LTDC)
728 
729  /*-------------------------- LTDC clock source configuration --------------------*/
730  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
731  {
732  /* Check the parameters */
733  assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));
734 
735  /* Disable the PLLSAI2 */
736  __HAL_RCC_PLLSAI2_DISABLE();
737 
738  /* Get Start Tick*/
739  tickstart = HAL_GetTick();
740 
741  /* Wait till PLLSAI2 is ready */
742  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
743  {
744  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
745  {
746  ret = HAL_TIMEOUT;
747  break;
748  }
749  }
750 
751  if(ret == HAL_OK)
752  {
753  /* Configure the LTDC clock source */
754  __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);
755 
756  /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
757  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
758  }
759 
760  if(ret != HAL_OK)
761  {
762  /* set overall return value */
763  status = ret;
764  }
765  }
766 
767 #endif /* LTDC */
768 
769 #if defined(DSI)
770 
771  /*-------------------------- DSI clock source configuration ---------------------*/
772  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
773  {
774  /* Check the parameters */
775  assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));
776 
777  /* Configure the DSI clock source */
778  __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
779 
780  if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2)
781  {
782  /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */
783  ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE);
784 
785  if(ret != HAL_OK)
786  {
787  /* set overall return value */
788  status = ret;
789  }
790  }
791  }
792 
793 #endif /* DSI */
794 
795 #if defined(OCTOSPI1) || defined(OCTOSPI2)
796 
797  /*-------------------------- OctoSPIx clock source configuration ----------------*/
798  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
799  {
800  /* Check the parameters */
801  assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection));
802 
803  /* Configure the OctoSPI clock source */
804  __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
805 
806  if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL)
807  {
808  /* Enable PLL48M1CLK output */
809  __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
810  }
811  }
812 
813 #endif /* OCTOSPI1 || OCTOSPI2 */
814 
815  return status;
816 }
817 
826 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
827 {
828  /* Set all possible values for the extended clock type parameter------------*/
829 
830 #if defined(STM32L412xx) || defined(STM32L422xx)
831 
832  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
833  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
834  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_USB | \
835  RCC_PERIPHCLK_RNG | \
836  RCC_PERIPHCLK_RTC ;
837 
838 #elif defined(STM32L431xx)
839 
840  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
841  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
842  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
843  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
844  RCC_PERIPHCLK_RTC ;
845 
846 #elif defined(STM32L432xx) || defined(STM32L442xx)
847 
848  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
849  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
850  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
851  RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
852  RCC_PERIPHCLK_RTC ;
853 
854 #elif defined(STM32L433xx) || defined(STM32L443xx)
855 
856  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
857  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
858  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
859  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \
860  RCC_PERIPHCLK_RTC ;
861 
862 #elif defined(STM32L451xx)
863 
864  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
865  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
866  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \
867  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
868  RCC_PERIPHCLK_RTC ;
869 
870 #elif defined(STM32L452xx) || defined(STM32L462xx)
871 
872  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
873  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
874  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
875  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
876  RCC_PERIPHCLK_RTC ;
877 
878 #elif defined(STM32L471xx)
879 
880  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
881  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
882  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
883  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
884  RCC_PERIPHCLK_RTC ;
885 
886 #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
887 
888  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
889  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
890  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
891  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
892  RCC_PERIPHCLK_RTC ;
893 
894 #elif defined(STM32L496xx) || defined(STM32L4A6xx)
895 
896  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
897  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
898  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
899  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \
900  RCC_PERIPHCLK_RTC ;
901 
902 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
903 
904  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
905  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
906  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
907  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
908  RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI;
909 
910 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx)
911 
912  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
913  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
914  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
915  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
916  RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC;
917 
918 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
919 
920  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
921  RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \
922  RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \
923  RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \
924  RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI;
925 
926 #endif /* STM32L431xx */
927 
928 #if defined(RCC_PLLSAI1_SUPPORT)
929 
930  /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
931 
932  PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos;
933 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
934  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U;
935 #else
936  PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
937 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
938  PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
939  PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U;
940  PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U;
941  PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U;
942 
943 #endif /* RCC_PLLSAI1_SUPPORT */
944 
945 #if defined(RCC_PLLSAI2_SUPPORT)
946 
947  /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/
948 
949  PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
950 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
951  PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U;
952 #else
953  PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
954 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
955  PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
956  PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U;
957 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
958  PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U;
959 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
960  PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U;
961 
962 #endif /* RCC_PLLSAI2_SUPPORT */
963 
964  /* Get the USART1 clock source ---------------------------------------------*/
965  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
966  /* Get the USART2 clock source ---------------------------------------------*/
967  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
968 
969 #if defined(USART3)
970  /* Get the USART3 clock source ---------------------------------------------*/
971  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
972 #endif /* USART3 */
973 
974 #if defined(UART4)
975  /* Get the UART4 clock source ----------------------------------------------*/
976  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
977 #endif /* UART4 */
978 
979 #if defined(UART5)
980  /* Get the UART5 clock source ----------------------------------------------*/
981  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
982 #endif /* UART5 */
983 
984  /* Get the LPUART1 clock source --------------------------------------------*/
985  PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
986 
987  /* Get the I2C1 clock source -----------------------------------------------*/
988  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
989 
990 #if defined(I2C2)
991  /* Get the I2C2 clock source ----------------------------------------------*/
992  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
993 #endif /* I2C2 */
994 
995  /* Get the I2C3 clock source -----------------------------------------------*/
996  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
997 
998 #if defined(I2C4)
999  /* Get the I2C4 clock source -----------------------------------------------*/
1000  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
1001 #endif /* I2C4 */
1002 
1003  /* Get the LPTIM1 clock source ---------------------------------------------*/
1004  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1005 
1006  /* Get the LPTIM2 clock source ---------------------------------------------*/
1007  PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1008 
1009 #if defined(SAI1)
1010  /* Get the SAI1 clock source -----------------------------------------------*/
1011  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1012 #endif /* SAI1 */
1013 
1014 #if defined(SAI2)
1015  /* Get the SAI2 clock source -----------------------------------------------*/
1016  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1017 #endif /* SAI2 */
1018 
1019  /* Get the RTC clock source ------------------------------------------------*/
1020  PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1021 
1022 #if defined(USB_OTG_FS) || defined(USB)
1023  /* Get the USB clock source ------------------------------------------------*/
1024  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
1025 #endif /* USB_OTG_FS || USB */
1026 
1027 #if defined(SDMMC1)
1028  /* Get the SDMMC1 clock source ---------------------------------------------*/
1029  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
1030 #endif /* SDMMC1 */
1031 
1032  /* Get the RNG clock source ------------------------------------------------*/
1033  PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1034 
1035 #if !defined(STM32L412xx) && !defined(STM32L422xx)
1036  /* Get the ADC clock source ------------------------------------------------*/
1037  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1038 #endif /* !STM32L412xx && !STM32L422xx */
1039 
1040 #if defined(SWPMI1)
1041  /* Get the SWPMI1 clock source ---------------------------------------------*/
1042  PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
1043 #endif /* SWPMI1 */
1044 
1045 #if defined(DFSDM1_Filter0)
1046  /* Get the DFSDM1 clock source ---------------------------------------------*/
1047  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
1048 
1049 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1050  /* Get the DFSDM1 audio clock source ---------------------------------------*/
1051  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
1052 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1053 #endif /* DFSDM1_Filter0 */
1054 
1055 #if defined(LTDC)
1056  /* Get the LTDC clock source -----------------------------------------------*/
1057  PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
1058 #endif /* LTDC */
1059 
1060 #if defined(DSI)
1061  /* Get the DSI clock source ------------------------------------------------*/
1062  PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1063 #endif /* DSI */
1064 
1065 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1066  /* Get the OctoSPIclock source --------------------------------------------*/
1067  PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1068 #endif /* OCTOSPI1 || OCTOSPI2 */
1069 }
1070 
1152 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
1153 {
1154  uint32_t frequency = 0U;
1155  uint32_t srcclk, pll_oscsource, pllvco, plln; /* no init needed */
1156 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)
1157  uint32_t pllp; /* no init needed */
1158 #endif
1159 
1160  /* Check the parameters */
1161  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
1162 
1163  if(PeriphClk == RCC_PERIPHCLK_RTC)
1164  {
1165  /* Get the current RTC source */
1166  srcclk = __HAL_RCC_GET_RTC_SOURCE();
1167 
1168  switch(srcclk)
1169  {
1170  case RCC_RTCCLKSOURCE_LSE:
1171  /* Check if LSE is ready */
1172  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1173  {
1174  frequency = LSE_VALUE;
1175  }
1176  break;
1177  case RCC_RTCCLKSOURCE_LSI:
1178  /* Check if LSI is ready */
1179  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
1180  {
1181 #if defined(RCC_CSR_LSIPREDIV)
1182  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
1183  {
1184  frequency = LSI_VALUE/128U;
1185  }
1186  else
1187 #endif /* RCC_CSR_LSIPREDIV */
1188  {
1189  frequency = LSI_VALUE;
1190  }
1191  }
1192  break;
1193  case RCC_RTCCLKSOURCE_HSE_DIV32:
1194  /* Check if HSE is ready */
1195  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1196  {
1197  frequency = HSE_VALUE / 32U;
1198  }
1199  break;
1200  default:
1201  /* No clock source, frequency default init at 0 */
1202  break;
1203  }
1204  }
1205  else
1206  {
1207  /* Other external peripheral clock source than RTC */
1208  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
1209 
1210  /* Compute PLL clock input */
1211  switch(pll_oscsource)
1212  {
1213  case RCC_PLLSOURCE_MSI: /* MSI ? */
1214  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1215  {
1216  /*MSI frequency range in HZ*/
1217  pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1218  }
1219  else
1220  {
1221  pllvco = 0U;
1222  }
1223  break;
1224  case RCC_PLLSOURCE_HSI: /* HSI ? */
1225  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1226  {
1227  pllvco = HSI_VALUE;
1228  }
1229  else
1230  {
1231  pllvco = 0U;
1232  }
1233  break;
1234  case RCC_PLLSOURCE_HSE: /* HSE ? */
1235  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1236  {
1237  pllvco = HSE_VALUE;
1238  }
1239  else
1240  {
1241  pllvco = 0U;
1242  }
1243  break;
1244  default:
1245  /* No source */
1246  pllvco = 0U;
1247  break;
1248  }
1249 
1250  switch(PeriphClk)
1251  {
1252 #if defined(SAI1)
1253 
1254  case RCC_PERIPHCLK_SAI1:
1255  frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);
1256  break;
1257 
1258 #endif
1259 
1260 #if defined(SAI2)
1261 
1262  case RCC_PERIPHCLK_SAI2:
1263  frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI2, pllvco);
1264  break;
1265 
1266 #endif
1267 
1268 #if defined(USB_OTG_FS) || defined(USB)
1269 
1270  case RCC_PERIPHCLK_USB:
1271 
1272 #endif /* USB_OTG_FS || USB */
1273 
1274  case RCC_PERIPHCLK_RNG:
1275 
1276 #if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL)
1277 
1278  case RCC_PERIPHCLK_SDMMC1:
1279 
1280 #endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */
1281  {
1282  srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
1283 
1284  switch(srcclk)
1285  {
1286  case RCC_CCIPR_CLK48SEL: /* MSI ? */
1287  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1288  {
1289  /*MSI frequency range in HZ*/
1290  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1291  }
1292  break;
1293  case RCC_CCIPR_CLK48SEL_1: /* PLL ? */
1294  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1295  {
1296  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
1297  {
1298  /* f(PLL Source) * PLLN / PLLM */
1299  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1300  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1301  /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
1302  frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
1303  }
1304  }
1305  break;
1306 #if defined(RCC_PLLSAI1_SUPPORT)
1307  case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */
1308  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))
1309  {
1310  if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
1311  {
1312  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
1313 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1314  /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
1315  /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
1316  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
1317 #else
1318  /* f(PLL Source) * PLLSAI1N / PLLM */
1319  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1320 #endif
1321  /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */
1322  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));
1323  }
1324  }
1325  break;
1326 #endif /* RCC_PLLSAI1_SUPPORT */
1327 #if defined(RCC_HSI48_SUPPORT)
1328  case 0U:
1329  if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */
1330  {
1331  frequency = HSI48_VALUE;
1332  }
1333  break;
1334 #endif /* RCC_HSI48_SUPPORT */
1335  default:
1336  /* No clock source, frequency default init at 0 */
1337  break;
1338  } /* switch(srcclk) */
1339  break;
1340  }
1341 
1342 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL)
1343 
1344  case RCC_PERIPHCLK_SDMMC1:
1345 
1346  if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */
1347  {
1348  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1349  {
1350  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN))
1351  {
1352  /* f(PLL Source) * PLLN / PLLM */
1353  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1354  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1355  /* f(PLLSAI3CLK) = f(VCO input) / PLLP */
1356  pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
1357  if(pllp == 0U)
1358  {
1359  if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
1360  {
1361  pllp = 17U;
1362  }
1363  else
1364  {
1365  pllp = 7U;
1366  }
1367  }
1368  frequency = (pllvco / pllp);
1369  }
1370  }
1371  }
1372  else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */
1373  {
1374  srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
1375 
1376  switch(srcclk)
1377  {
1378  case RCC_CCIPR_CLK48SEL: /* MSI ? */
1379  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1380  {
1381  /*MSI frequency range in HZ*/
1382  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1383  }
1384  break;
1385  case RCC_CCIPR_CLK48SEL_1: /* PLL "Q" ? */
1386  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
1387  {
1388  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
1389  {
1390  /* f(PLL Source) * PLLN / PLLM */
1391  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
1392  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1393  /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
1394  frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
1395  }
1396  }
1397  break;
1398  case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */
1399  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY))
1400  {
1401  if(HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
1402  {
1403  /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
1404  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
1405  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
1406  /* f(PLL48M2CLK) = f(VCOSAI1 input) / PLLSAI1Q */
1407  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U));
1408  }
1409  }
1410  break;
1411  case 0U:
1412  if(HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) /* HSI48 ? */
1413  {
1414  frequency = HSI48_VALUE;
1415  }
1416  break;
1417  default:
1418  /* No clock source, frequency default init at 0 */
1419  break;
1420  } /* switch(srcclk) */
1421  }
1422  break;
1423 
1424 #endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */
1425 
1426  case RCC_PERIPHCLK_USART1:
1427  {
1428  /* Get the current USART1 source */
1429  srcclk = __HAL_RCC_GET_USART1_SOURCE();
1430 
1431  switch(srcclk)
1432  {
1433  case RCC_USART1CLKSOURCE_PCLK2:
1434  frequency = HAL_RCC_GetPCLK2Freq();
1435  break;
1436  case RCC_USART1CLKSOURCE_SYSCLK:
1437  frequency = HAL_RCC_GetSysClockFreq();
1438  break;
1439  case RCC_USART1CLKSOURCE_HSI:
1440  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1441  {
1442  frequency = HSI_VALUE;
1443  }
1444  break;
1445  case RCC_USART1CLKSOURCE_LSE:
1446  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1447  {
1448  frequency = LSE_VALUE;
1449  }
1450  break;
1451  default:
1452  /* No clock source, frequency default init at 0 */
1453  break;
1454  }
1455 
1456  break;
1457  }
1458 
1459  case RCC_PERIPHCLK_USART2:
1460  {
1461  /* Get the current USART2 source */
1462  srcclk = __HAL_RCC_GET_USART2_SOURCE();
1463 
1464  switch(srcclk)
1465  {
1466  case RCC_USART2CLKSOURCE_PCLK1:
1467  frequency = HAL_RCC_GetPCLK1Freq();
1468  break;
1469  case RCC_USART2CLKSOURCE_SYSCLK:
1470  frequency = HAL_RCC_GetSysClockFreq();
1471  break;
1472  case RCC_USART2CLKSOURCE_HSI:
1473  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1474  {
1475  frequency = HSI_VALUE;
1476  }
1477  break;
1478  case RCC_USART2CLKSOURCE_LSE:
1479  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1480  {
1481  frequency = LSE_VALUE;
1482  }
1483  break;
1484  default:
1485  /* No clock source, frequency default init at 0 */
1486  break;
1487  }
1488 
1489  break;
1490  }
1491 
1492 #if defined(USART3)
1493 
1494  case RCC_PERIPHCLK_USART3:
1495  {
1496  /* Get the current USART3 source */
1497  srcclk = __HAL_RCC_GET_USART3_SOURCE();
1498 
1499  switch(srcclk)
1500  {
1501  case RCC_USART3CLKSOURCE_PCLK1:
1502  frequency = HAL_RCC_GetPCLK1Freq();
1503  break;
1504  case RCC_USART3CLKSOURCE_SYSCLK:
1505  frequency = HAL_RCC_GetSysClockFreq();
1506  break;
1507  case RCC_USART3CLKSOURCE_HSI:
1508  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1509  {
1510  frequency = HSI_VALUE;
1511  }
1512  break;
1513  case RCC_USART3CLKSOURCE_LSE:
1514  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1515  {
1516  frequency = LSE_VALUE;
1517  }
1518  break;
1519  default:
1520  /* No clock source, frequency default init at 0 */
1521  break;
1522  }
1523 
1524  break;
1525  }
1526 
1527 #endif /* USART3 */
1528 
1529 #if defined(UART4)
1530 
1531  case RCC_PERIPHCLK_UART4:
1532  {
1533  /* Get the current UART4 source */
1534  srcclk = __HAL_RCC_GET_UART4_SOURCE();
1535 
1536  switch(srcclk)
1537  {
1538  case RCC_UART4CLKSOURCE_PCLK1:
1539  frequency = HAL_RCC_GetPCLK1Freq();
1540  break;
1541  case RCC_UART4CLKSOURCE_SYSCLK:
1542  frequency = HAL_RCC_GetSysClockFreq();
1543  break;
1544  case RCC_UART4CLKSOURCE_HSI:
1545  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1546  {
1547  frequency = HSI_VALUE;
1548  }
1549  break;
1550  case RCC_UART4CLKSOURCE_LSE:
1551  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1552  {
1553  frequency = LSE_VALUE;
1554  }
1555  break;
1556  default:
1557  /* No clock source, frequency default init at 0 */
1558  break;
1559  }
1560 
1561  break;
1562  }
1563 
1564 #endif /* UART4 */
1565 
1566 #if defined(UART5)
1567 
1568  case RCC_PERIPHCLK_UART5:
1569  {
1570  /* Get the current UART5 source */
1571  srcclk = __HAL_RCC_GET_UART5_SOURCE();
1572 
1573  switch(srcclk)
1574  {
1575  case RCC_UART5CLKSOURCE_PCLK1:
1576  frequency = HAL_RCC_GetPCLK1Freq();
1577  break;
1578  case RCC_UART5CLKSOURCE_SYSCLK:
1579  frequency = HAL_RCC_GetSysClockFreq();
1580  break;
1581  case RCC_UART5CLKSOURCE_HSI:
1582  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1583  {
1584  frequency = HSI_VALUE;
1585  }
1586  break;
1587  case RCC_UART5CLKSOURCE_LSE:
1588  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1589  {
1590  frequency = LSE_VALUE;
1591  }
1592  break;
1593  default:
1594  /* No clock source, frequency default init at 0 */
1595  break;
1596  }
1597 
1598  break;
1599  }
1600 
1601 #endif /* UART5 */
1602 
1603  case RCC_PERIPHCLK_LPUART1:
1604  {
1605  /* Get the current LPUART1 source */
1606  srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
1607 
1608  switch(srcclk)
1609  {
1610  case RCC_LPUART1CLKSOURCE_PCLK1:
1611  frequency = HAL_RCC_GetPCLK1Freq();
1612  break;
1613  case RCC_LPUART1CLKSOURCE_SYSCLK:
1614  frequency = HAL_RCC_GetSysClockFreq();
1615  break;
1616  case RCC_LPUART1CLKSOURCE_HSI:
1617  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1618  {
1619  frequency = HSI_VALUE;
1620  }
1621  break;
1622  case RCC_LPUART1CLKSOURCE_LSE:
1623  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1624  {
1625  frequency = LSE_VALUE;
1626  }
1627  break;
1628  default:
1629  /* No clock source, frequency default init at 0 */
1630  break;
1631  }
1632 
1633  break;
1634  }
1635 
1636  case RCC_PERIPHCLK_ADC:
1637  {
1638  srcclk = __HAL_RCC_GET_ADC_SOURCE();
1639 
1640  switch(srcclk)
1641  {
1642  case RCC_ADCCLKSOURCE_SYSCLK:
1643  frequency = HAL_RCC_GetSysClockFreq();
1644  break;
1645 #if defined(RCC_PLLSAI1_SUPPORT)
1646  case RCC_ADCCLKSOURCE_PLLSAI1:
1647  if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != 0U)
1648  {
1649  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
1650 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1651  /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
1652  /* f(PLLSAI1 Source) * PLLSAI1N / PLLSAI1M */
1653  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
1654 #else
1655  /* f(PLL Source) * PLLSAI1N / PLLM */
1656  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1657 #endif
1658  /* f(PLLADC1CLK) = f(VCOSAI1 input) / PLLSAI1R */
1659  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U));
1660  }
1661  break;
1662 #endif /* RCC_PLLSAI1_SUPPORT */
1663 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
1664  case RCC_ADCCLKSOURCE_PLLSAI2:
1665  if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != 0U)
1666  {
1667  plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
1668 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1669  /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */
1670  /* f(PLLSAI2 Source) * PLLSAI2N / PLLSAI2M */
1671  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));
1672 #else
1673  /* f(PLL Source) * PLLSAI2N / PLLM */
1674  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
1675 #endif
1676  /* f(PLLADC2CLK) = f(VCOSAI2 input) / PLLSAI2R */
1677  frequency = (pllvco / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U));
1678  }
1679  break;
1680 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
1681  default:
1682  /* No clock source, frequency default init at 0 */
1683  break;
1684  }
1685 
1686  break;
1687  }
1688 
1689 #if defined(DFSDM1_Filter0)
1690 
1691  case RCC_PERIPHCLK_DFSDM1:
1692  {
1693  /* Get the current DFSDM1 source */
1694  srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
1695 
1696  if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)
1697  {
1698  frequency = HAL_RCC_GetPCLK2Freq();
1699  }
1700  else
1701  {
1702  frequency = HAL_RCC_GetSysClockFreq();
1703  }
1704 
1705  break;
1706  }
1707 
1708 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1709 
1710  case RCC_PERIPHCLK_DFSDM1AUDIO:
1711  {
1712  /* Get the current DFSDM1 audio source */
1713  srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
1714 
1715  switch(srcclk)
1716  {
1717  case RCC_DFSDM1AUDIOCLKSOURCE_SAI1:
1718  frequency = RCCEx_GetSAIxPeriphCLKFreq(RCC_PERIPHCLK_SAI1, pllvco);
1719  break;
1720  case RCC_DFSDM1AUDIOCLKSOURCE_MSI:
1721  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1722  {
1723  /*MSI frequency range in HZ*/
1724  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1725  }
1726  break;
1727  case RCC_DFSDM1AUDIOCLKSOURCE_HSI:
1728  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1729  {
1730  frequency = HSI_VALUE;
1731  }
1732  break;
1733  default:
1734  /* No clock source, frequency default init at 0 */
1735  break;
1736  }
1737 
1738  break;
1739  }
1740 
1741 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1742 
1743 #endif /* DFSDM1_Filter0 */
1744 
1745  case RCC_PERIPHCLK_I2C1:
1746  {
1747  /* Get the current I2C1 source */
1748  srcclk = __HAL_RCC_GET_I2C1_SOURCE();
1749 
1750  switch(srcclk)
1751  {
1752  case RCC_I2C1CLKSOURCE_PCLK1:
1753  frequency = HAL_RCC_GetPCLK1Freq();
1754  break;
1755  case RCC_I2C1CLKSOURCE_SYSCLK:
1756  frequency = HAL_RCC_GetSysClockFreq();
1757  break;
1758  case RCC_I2C1CLKSOURCE_HSI:
1759  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1760  {
1761  frequency = HSI_VALUE;
1762  }
1763  break;
1764  default:
1765  /* No clock source, frequency default init at 0 */
1766  break;
1767  }
1768 
1769  break;
1770  }
1771 
1772 #if defined(I2C2)
1773 
1774  case RCC_PERIPHCLK_I2C2:
1775  {
1776  /* Get the current I2C2 source */
1777  srcclk = __HAL_RCC_GET_I2C2_SOURCE();
1778 
1779  switch(srcclk)
1780  {
1781  case RCC_I2C2CLKSOURCE_PCLK1:
1782  frequency = HAL_RCC_GetPCLK1Freq();
1783  break;
1784  case RCC_I2C2CLKSOURCE_SYSCLK:
1785  frequency = HAL_RCC_GetSysClockFreq();
1786  break;
1787  case RCC_I2C2CLKSOURCE_HSI:
1788  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1789  {
1790  frequency = HSI_VALUE;
1791  }
1792  break;
1793  default:
1794  /* No clock source, frequency default init at 0 */
1795  break;
1796  }
1797 
1798  break;
1799  }
1800 
1801 #endif /* I2C2 */
1802 
1803  case RCC_PERIPHCLK_I2C3:
1804  {
1805  /* Get the current I2C3 source */
1806  srcclk = __HAL_RCC_GET_I2C3_SOURCE();
1807 
1808  switch(srcclk)
1809  {
1810  case RCC_I2C3CLKSOURCE_PCLK1:
1811  frequency = HAL_RCC_GetPCLK1Freq();
1812  break;
1813  case RCC_I2C3CLKSOURCE_SYSCLK:
1814  frequency = HAL_RCC_GetSysClockFreq();
1815  break;
1816  case RCC_I2C3CLKSOURCE_HSI:
1817  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1818  {
1819  frequency = HSI_VALUE;
1820  }
1821  break;
1822  default:
1823  /* No clock source, frequency default init at 0 */
1824  break;
1825  }
1826 
1827  break;
1828  }
1829 
1830 #if defined(I2C4)
1831 
1832  case RCC_PERIPHCLK_I2C4:
1833  {
1834  /* Get the current I2C4 source */
1835  srcclk = __HAL_RCC_GET_I2C4_SOURCE();
1836 
1837  switch(srcclk)
1838  {
1839  case RCC_I2C4CLKSOURCE_PCLK1:
1840  frequency = HAL_RCC_GetPCLK1Freq();
1841  break;
1842  case RCC_I2C4CLKSOURCE_SYSCLK:
1843  frequency = HAL_RCC_GetSysClockFreq();
1844  break;
1845  case RCC_I2C4CLKSOURCE_HSI:
1846  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1847  {
1848  frequency = HSI_VALUE;
1849  }
1850  break;
1851  default:
1852  /* No clock source, frequency default init at 0 */
1853  break;
1854  }
1855 
1856  break;
1857  }
1858 
1859 #endif /* I2C4 */
1860 
1861  case RCC_PERIPHCLK_LPTIM1:
1862  {
1863  /* Get the current LPTIM1 source */
1864  srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
1865 
1866  switch(srcclk)
1867  {
1868  case RCC_LPTIM1CLKSOURCE_PCLK1:
1869  frequency = HAL_RCC_GetPCLK1Freq();
1870  break;
1871  case RCC_LPTIM1CLKSOURCE_LSI:
1872  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
1873  {
1874 #if defined(RCC_CSR_LSIPREDIV)
1875  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
1876  {
1877  frequency = LSI_VALUE/128U;
1878  }
1879  else
1880 #endif /* RCC_CSR_LSIPREDIV */
1881  {
1882  frequency = LSI_VALUE;
1883  }
1884  }
1885  break;
1886  case RCC_LPTIM1CLKSOURCE_HSI:
1887  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1888  {
1889  frequency = HSI_VALUE;
1890  }
1891  break;
1892  case RCC_LPTIM1CLKSOURCE_LSE:
1893  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1894  {
1895  frequency = LSE_VALUE;
1896  }
1897  break;
1898  default:
1899  /* No clock source, frequency default init at 0 */
1900  break;
1901  }
1902 
1903  break;
1904  }
1905 
1906  case RCC_PERIPHCLK_LPTIM2:
1907  {
1908  /* Get the current LPTIM2 source */
1909  srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
1910 
1911  switch(srcclk)
1912  {
1913  case RCC_LPTIM2CLKSOURCE_PCLK1:
1914  frequency = HAL_RCC_GetPCLK1Freq();
1915  break;
1916  case RCC_LPTIM2CLKSOURCE_LSI:
1917  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
1918  {
1919 #if defined(RCC_CSR_LSIPREDIV)
1920  if(HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIPREDIV))
1921  {
1922  frequency = LSI_VALUE/128U;
1923  }
1924  else
1925 #endif /* RCC_CSR_LSIPREDIV */
1926  {
1927  frequency = LSI_VALUE;
1928  }
1929  }
1930  break;
1931  case RCC_LPTIM2CLKSOURCE_HSI:
1932  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1933  {
1934  frequency = HSI_VALUE;
1935  }
1936  break;
1937  case RCC_LPTIM2CLKSOURCE_LSE:
1938  if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
1939  {
1940  frequency = LSE_VALUE;
1941  }
1942  break;
1943  default:
1944  /* No clock source, frequency default init at 0 */
1945  break;
1946  }
1947 
1948  break;
1949  }
1950 
1951 #if defined(SWPMI1)
1952 
1953  case RCC_PERIPHCLK_SWPMI1:
1954  {
1955  /* Get the current SWPMI1 source */
1956  srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
1957 
1958  switch(srcclk)
1959  {
1960  case RCC_SWPMI1CLKSOURCE_PCLK1:
1961  frequency = HAL_RCC_GetPCLK1Freq();
1962  break;
1963  case RCC_SWPMI1CLKSOURCE_HSI:
1964  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1965  {
1966  frequency = HSI_VALUE;
1967  }
1968  break;
1969  default:
1970  /* No clock source, frequency default init at 0 */
1971  break;
1972  }
1973 
1974  break;
1975  }
1976 
1977 #endif /* SWPMI1 */
1978 
1979 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1980 
1981  case RCC_PERIPHCLK_OSPI:
1982  {
1983  /* Get the current OctoSPI clock source */
1984  srcclk = __HAL_RCC_GET_OSPI_SOURCE();
1985 
1986  switch(srcclk)
1987  {
1988  case RCC_OSPICLKSOURCE_SYSCLK:
1989  frequency = HAL_RCC_GetSysClockFreq();
1990  break;
1991  case RCC_OSPICLKSOURCE_MSI:
1992  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
1993  {
1994  /*MSI frequency range in HZ*/
1995  frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
1996  }
1997  break;
1998  case RCC_OSPICLKSOURCE_PLL:
1999  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
2000  {
2001  if(HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
2002  {
2003  /* f(PLL Source) * PLLN / PLLM */
2004  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
2005  pllvco = ((pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
2006  /* f(PLL48M1CLK) = f(VCO input) / PLLQ */
2007  frequency = (pllvco / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U));
2008  }
2009  }
2010  break;
2011  default:
2012  /* No clock source, frequency default init at 0 */
2013  break;
2014  }
2015 
2016  break;
2017  }
2018 
2019 #endif /* OCTOSPI1 || OCTOSPI2 */
2020 
2021  default:
2022  break;
2023  }
2024  }
2025 
2026  return(frequency);
2027 }
2028 
2048 #if defined(RCC_PLLSAI1_SUPPORT)
2049 
2056 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
2057 {
2058  uint32_t tickstart;
2059  HAL_StatusTypeDef status = HAL_OK;
2060 
2061  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
2062  assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source));
2063  assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M));
2064  assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N));
2065  assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P));
2066  assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q));
2067  assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R));
2068  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut));
2069 
2070  /* Disable the PLLSAI1 */
2071  __HAL_RCC_PLLSAI1_DISABLE();
2072 
2073  /* Get Start Tick*/
2074  tickstart = HAL_GetTick();
2075 
2076  /* Wait till PLLSAI1 is ready to be updated */
2077  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
2078  {
2079  if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
2080  {
2081  status = HAL_TIMEOUT;
2082  break;
2083  }
2084  }
2085 
2086  if(status == HAL_OK)
2087  {
2088 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
2089  /* Configure the PLLSAI1 Multiplication factor N */
2090  /* Configure the PLLSAI1 Division factors M, P, Q and R */
2091  __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
2092 #else
2093  /* Configure the PLLSAI1 Multiplication factor N */
2094  /* Configure the PLLSAI1 Division factors P, Q and R */
2095  __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R);
2096 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
2097  /* Configure the PLLSAI1 Clock output(s) */
2098  __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut);
2099 
2100  /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
2101  __HAL_RCC_PLLSAI1_ENABLE();
2102 
2103  /* Get Start Tick*/
2104  tickstart = HAL_GetTick();
2105 
2106  /* Wait till PLLSAI1 is ready */
2107  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
2108  {
2109  if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
2110  {
2111  status = HAL_TIMEOUT;
2112  break;
2113  }
2114  }
2115  }
2116 
2117  return status;
2118 }
2119 
2124 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
2125 {
2126  uint32_t tickstart;
2127  HAL_StatusTypeDef status = HAL_OK;
2128 
2129  /* Disable the PLLSAI1 */
2130  __HAL_RCC_PLLSAI1_DISABLE();
2131 
2132  /* Get Start Tick*/
2133  tickstart = HAL_GetTick();
2134 
2135  /* Wait till PLLSAI1 is ready */
2136  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
2137  {
2138  if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
2139  {
2140  status = HAL_TIMEOUT;
2141  break;
2142  }
2143  }
2144 
2145  /* Disable the PLLSAI1 Clock outputs */
2146  __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN);
2147 
2148  /* Reset PLL source to save power if no PLLs on */
2149 #if defined(RCC_PLLSAI2_SUPPORT)
2150  if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI2RDY)) == 0U)
2151  {
2152  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
2153  }
2154 #else
2155  if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
2156  {
2157  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
2158  }
2159 #endif /* RCC_PLLSAI2_SUPPORT */
2160 
2161  return status;
2162 }
2163 
2164 #endif /* RCC_PLLSAI1_SUPPORT */
2165 
2166 #if defined(RCC_PLLSAI2_SUPPORT)
2167 
2174 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
2175 {
2176  uint32_t tickstart;
2177  HAL_StatusTypeDef status = HAL_OK;
2178 
2179  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
2180  assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source));
2181  assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M));
2182  assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N));
2183  assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P));
2184 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
2185  assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q));
2186 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
2187  assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R));
2188  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut));
2189 
2190  /* Disable the PLLSAI2 */
2191  __HAL_RCC_PLLSAI2_DISABLE();
2192 
2193  /* Get Start Tick*/
2194  tickstart = HAL_GetTick();
2195 
2196  /* Wait till PLLSAI2 is ready to be updated */
2197  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
2198  {
2199  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
2200  {
2201  status = HAL_TIMEOUT;
2202  break;
2203  }
2204  }
2205 
2206  if(status == HAL_OK)
2207  {
2208 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
2209  /* Configure the PLLSAI2 Multiplication factor N */
2210  /* Configure the PLLSAI2 Division factors M, P, Q and R */
2211  __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);
2212 #elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
2213  /* Configure the PLLSAI2 Multiplication factor N */
2214  /* Configure the PLLSAI2 Division factors M, P and R */
2215  __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
2216 #elif defined(RCC_PLLSAI2Q_DIV_SUPPORT)
2217  /* Configure the PLLSAI2 Multiplication factor N */
2218  /* Configure the PLLSAI2 Division factors P, Q and R */
2219  __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R);
2220 #else
2221  /* Configure the PLLSAI2 Multiplication factor N */
2222  /* Configure the PLLSAI2 Division factors P and R */
2223  __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R);
2224 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
2225  /* Configure the PLLSAI2 Clock output(s) */
2226  __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut);
2227 
2228  /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
2229  __HAL_RCC_PLLSAI2_ENABLE();
2230 
2231  /* Get Start Tick*/
2232  tickstart = HAL_GetTick();
2233 
2234  /* Wait till PLLSAI2 is ready */
2235  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
2236  {
2237  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
2238  {
2239  status = HAL_TIMEOUT;
2240  break;
2241  }
2242  }
2243  }
2244 
2245  return status;
2246 }
2247 
2252 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
2253 {
2254  uint32_t tickstart;
2255  HAL_StatusTypeDef status = HAL_OK;
2256 
2257  /* Disable the PLLSAI2 */
2258  __HAL_RCC_PLLSAI2_DISABLE();
2259 
2260  /* Get Start Tick*/
2261  tickstart = HAL_GetTick();
2262 
2263  /* Wait till PLLSAI2 is ready */
2264  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
2265  {
2266  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
2267  {
2268  status = HAL_TIMEOUT;
2269  break;
2270  }
2271  }
2272 
2273  /* Disable the PLLSAI2 Clock outputs */
2274 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
2275  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
2276 #else
2277  __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN);
2278 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
2279 
2280  /* Reset PLL source to save power if no PLLs on */
2281  if(READ_BIT(RCC->CR, (RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY)) == 0U)
2282  {
2283  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
2284  }
2285 
2286  return status;
2287 }
2288 
2289 #endif /* RCC_PLLSAI2_SUPPORT */
2290 
2301 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
2302 {
2303  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
2304 
2305  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
2306 }
2307 
2319 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
2320 {
2321  assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
2322 
2323  __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
2324 }
2325 
2333 void HAL_RCCEx_EnableLSECSS(void)
2334 {
2335  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
2336 }
2337 
2343 void HAL_RCCEx_DisableLSECSS(void)
2344 {
2345  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
2346 
2347  /* Disable LSE CSS IT if any */
2348  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
2349 }
2350 
2356 void HAL_RCCEx_EnableLSECSS_IT(void)
2357 {
2358  /* Enable LSE CSS */
2359  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
2360 
2361  /* Enable LSE CSS IT */
2362  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
2363 
2364  /* Enable IT on EXTI Line 19 */
2365  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
2366  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
2367 }
2368 
2373 void HAL_RCCEx_LSECSS_IRQHandler(void)
2374 {
2375  /* Check RCC LSE CSSF flag */
2376  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
2377  {
2378  /* RCC LSE Clock Security System interrupt user callback */
2379  HAL_RCCEx_LSECSS_Callback();
2380 
2381  /* Clear RCC LSE CSS pending bit */
2382  __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
2383  }
2384 }
2385 
2390 __weak void HAL_RCCEx_LSECSS_Callback(void)
2391 {
2392  /* NOTE : This function should not be modified, when the callback is needed,
2393  the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
2394  */
2395 }
2396 
2405 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
2406 {
2407  GPIO_InitTypeDef GPIO_InitStruct;
2408  FlagStatus pwrclkchanged = RESET;
2409  FlagStatus backupchanged = RESET;
2410 
2411  /* Check the parameters */
2412  assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
2413 
2414  /* LSCO Pin Clock Enable */
2415  __LSCO_CLK_ENABLE();
2416 
2417  /* Configue the LSCO pin in analog mode */
2418  GPIO_InitStruct.Pin = LSCO_PIN;
2419  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
2420  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
2421  GPIO_InitStruct.Pull = GPIO_NOPULL;
2422  HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
2423 
2424  /* Update LSCOSEL clock source in Backup Domain control register */
2425  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
2426  {
2427  __HAL_RCC_PWR_CLK_ENABLE();
2428  pwrclkchanged = SET;
2429  }
2430  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
2431  {
2432  HAL_PWR_EnableBkUpAccess();
2433  backupchanged = SET;
2434  }
2435 
2436  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
2437 
2438  if(backupchanged == SET)
2439  {
2440  HAL_PWR_DisableBkUpAccess();
2441  }
2442  if(pwrclkchanged == SET)
2443  {
2444  __HAL_RCC_PWR_CLK_DISABLE();
2445  }
2446 }
2447 
2452 void HAL_RCCEx_DisableLSCO(void)
2453 {
2454  FlagStatus pwrclkchanged = RESET;
2455  FlagStatus backupchanged = RESET;
2456 
2457  /* Update LSCOEN bit in Backup Domain control register */
2458  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
2459  {
2460  __HAL_RCC_PWR_CLK_ENABLE();
2461  pwrclkchanged = SET;
2462  }
2463  if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
2464  {
2465  /* Enable access to the backup domain */
2466  HAL_PWR_EnableBkUpAccess();
2467  backupchanged = SET;
2468  }
2469 
2470  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2471 
2472  /* Restore previous configuration */
2473  if(backupchanged == SET)
2474  {
2475  /* Disable access to the backup domain */
2476  HAL_PWR_DisableBkUpAccess();
2477  }
2478  if(pwrclkchanged == SET)
2479  {
2480  __HAL_RCC_PWR_CLK_DISABLE();
2481  }
2482 }
2483 
2490 void HAL_RCCEx_EnableMSIPLLMode(void)
2491 {
2492  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
2493 }
2494 
2500 void HAL_RCCEx_DisableMSIPLLMode(void)
2501 {
2502  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
2503 }
2504 
2509 #if defined(CRS)
2510 
2580 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
2581 {
2582  uint32_t value; /* no init needed */
2583 
2584  /* Check the parameters */
2585  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
2586  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
2587  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
2588  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
2589  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
2590  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
2591 
2592  /* CONFIGURATION */
2593 
2594  /* Before configuration, reset CRS registers to their default values*/
2595  __HAL_RCC_CRS_FORCE_RESET();
2596  __HAL_RCC_CRS_RELEASE_RESET();
2597 
2598  /* Set the SYNCDIV[2:0] bits according to Prescaler value */
2599  /* Set the SYNCSRC[1:0] bits according to Source value */
2600  /* Set the SYNCSPOL bit according to Polarity value */
2601  value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
2602  /* Set the RELOAD[15:0] bits according to ReloadValue value */
2603  value |= pInit->ReloadValue;
2604  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
2605  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
2606  WRITE_REG(CRS->CFGR, value);
2607 
2608  /* Adjust HSI48 oscillator smooth trimming */
2609  /* Set the TRIM[6:0] bits for STM32L412xx/L422xx or TRIM[5:0] bits otherwise
2610  according to RCC_CRS_HSI48CalibrationValue value */
2611  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
2612 
2613  /* START AUTOMATIC SYNCHRONIZATION*/
2614 
2615  /* Enable Automatic trimming & Frequency error counter */
2616  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
2617 }
2618 
2623 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
2624 {
2625  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
2626 }
2627 
2633 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
2634 {
2635  /* Check the parameter */
2636  assert_param(pSynchroInfo != (void *)NULL);
2637 
2638  /* Get the reload value */
2639  pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
2640 
2641  /* Get HSI48 oscillator smooth trimming */
2642  pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
2643 
2644  /* Get Frequency error capture */
2645  pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
2646 
2647  /* Get Frequency error direction */
2648  pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
2649 }
2650 
2666 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
2667 {
2668  uint32_t crsstatus = RCC_CRS_NONE;
2669  uint32_t tickstart;
2670 
2671  /* Get timeout */
2672  tickstart = HAL_GetTick();
2673 
2674  /* Wait for CRS flag or timeout detection */
2675  do
2676  {
2677  if(Timeout != HAL_MAX_DELAY)
2678  {
2679  if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
2680  {
2681  crsstatus = RCC_CRS_TIMEOUT;
2682  }
2683  }
2684  /* Check CRS SYNCOK flag */
2685  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
2686  {
2687  /* CRS SYNC event OK */
2688  crsstatus |= RCC_CRS_SYNCOK;
2689 
2690  /* Clear CRS SYNC event OK bit */
2691  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
2692  }
2693 
2694  /* Check CRS SYNCWARN flag */
2695  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
2696  {
2697  /* CRS SYNC warning */
2698  crsstatus |= RCC_CRS_SYNCWARN;
2699 
2700  /* Clear CRS SYNCWARN bit */
2701  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
2702  }
2703 
2704  /* Check CRS TRIM overflow flag */
2705  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
2706  {
2707  /* CRS SYNC Error */
2708  crsstatus |= RCC_CRS_TRIMOVF;
2709 
2710  /* Clear CRS Error bit */
2711  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
2712  }
2713 
2714  /* Check CRS Error flag */
2715  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
2716  {
2717  /* CRS SYNC Error */
2718  crsstatus |= RCC_CRS_SYNCERR;
2719 
2720  /* Clear CRS Error bit */
2721  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
2722  }
2723 
2724  /* Check CRS SYNC Missed flag */
2725  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
2726  {
2727  /* CRS SYNC Missed */
2728  crsstatus |= RCC_CRS_SYNCMISS;
2729 
2730  /* Clear CRS SYNC Missed bit */
2731  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
2732  }
2733 
2734  /* Check CRS Expected SYNC flag */
2735  if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
2736  {
2737  /* frequency error counter reached a zero value */
2738  __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
2739  }
2740  } while(RCC_CRS_NONE == crsstatus);
2741 
2742  return crsstatus;
2743 }
2744 
2749 void HAL_RCCEx_CRS_IRQHandler(void)
2750 {
2751  uint32_t crserror = RCC_CRS_NONE;
2752  /* Get current IT flags and IT sources values */
2753  uint32_t itflags = READ_REG(CRS->ISR);
2754  uint32_t itsources = READ_REG(CRS->CR);
2755 
2756  /* Check CRS SYNCOK flag */
2757  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
2758  {
2759  /* Clear CRS SYNC event OK flag */
2760  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
2761 
2762  /* user callback */
2763  HAL_RCCEx_CRS_SyncOkCallback();
2764  }
2765  /* Check CRS SYNCWARN flag */
2766  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
2767  {
2768  /* Clear CRS SYNCWARN flag */
2769  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
2770 
2771  /* user callback */
2772  HAL_RCCEx_CRS_SyncWarnCallback();
2773  }
2774  /* Check CRS Expected SYNC flag */
2775  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
2776  {
2777  /* frequency error counter reached a zero value */
2778  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
2779 
2780  /* user callback */
2781  HAL_RCCEx_CRS_ExpectedSyncCallback();
2782  }
2783  /* Check CRS Error flags */
2784  else
2785  {
2786  if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
2787  {
2788  if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
2789  {
2790  crserror |= RCC_CRS_SYNCERR;
2791  }
2792  if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
2793  {
2794  crserror |= RCC_CRS_SYNCMISS;
2795  }
2796  if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
2797  {
2798  crserror |= RCC_CRS_TRIMOVF;
2799  }
2800 
2801  /* Clear CRS Error flags */
2802  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
2803 
2804  /* user error callback */
2805  HAL_RCCEx_CRS_ErrorCallback(crserror);
2806  }
2807  }
2808 }
2809 
2814 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
2815 {
2816  /* NOTE : This function should not be modified, when the callback is needed,
2817  the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
2818  */
2819 }
2820 
2825 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
2826 {
2827  /* NOTE : This function should not be modified, when the callback is needed,
2828  the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
2829  */
2830 }
2831 
2836 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
2837 {
2838  /* NOTE : This function should not be modified, when the callback is needed,
2839  the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
2840  */
2841 }
2842 
2852 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
2853 {
2854  /* Prevent unused argument(s) compilation warning */
2855  UNUSED(Error);
2856 
2857  /* NOTE : This function should not be modified, when the callback is needed,
2858  the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
2859  */
2860 }
2861 
2866 #endif /* CRS */
2867 
2876 #if defined(RCC_PLLSAI1_SUPPORT)
2877 
2888 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
2889 {
2890  uint32_t tickstart;
2891  HAL_StatusTypeDef status = HAL_OK;
2892 
2893  /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */
2894  /* P, Q and R dividers are verified in each specific divider case below */
2895  assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source));
2896  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
2897  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
2898  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
2899 
2900  /* Check that PLLSAI1 clock source and divider M can be applied */
2901  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
2902  {
2903  /* PLL clock source and divider M already set, check that no request for change */
2904  if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
2905  ||
2906  (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
2907 #if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
2908  ||
2909  (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
2910 #endif
2911  )
2912  {
2913  status = HAL_ERROR;
2914  }
2915  }
2916  else
2917  {
2918  /* Check PLLSAI1 clock source availability */
2919  switch(PllSai1->PLLSAI1Source)
2920  {
2921  case RCC_PLLSOURCE_MSI:
2922  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
2923  {
2924  status = HAL_ERROR;
2925  }
2926  break;
2927  case RCC_PLLSOURCE_HSI:
2928  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
2929  {
2930  status = HAL_ERROR;
2931  }
2932  break;
2933  case RCC_PLLSOURCE_HSE:
2934  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
2935  {
2936  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
2937  {
2938  status = HAL_ERROR;
2939  }
2940  }
2941  break;
2942  default:
2943  status = HAL_ERROR;
2944  break;
2945  }
2946 
2947  if(status == HAL_OK)
2948  {
2949 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
2950  /* Set PLLSAI1 clock source */
2951  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
2952 #else
2953  /* Set PLLSAI1 clock source and divider M */
2954  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
2955 #endif
2956  }
2957  }
2958 
2959  if(status == HAL_OK)
2960  {
2961  /* Disable the PLLSAI1 */
2962  __HAL_RCC_PLLSAI1_DISABLE();
2963 
2964  /* Get Start Tick*/
2965  tickstart = HAL_GetTick();
2966 
2967  /* Wait till PLLSAI1 is ready to be updated */
2968  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
2969  {
2970  if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
2971  {
2972  status = HAL_TIMEOUT;
2973  break;
2974  }
2975  }
2976 
2977  if(status == HAL_OK)
2978  {
2979  if(Divider == DIVIDER_P_UPDATE)
2980  {
2981  assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P));
2982 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
2983 
2984  /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/
2985 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
2986  MODIFY_REG(RCC->PLLSAI1CFGR,
2987  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M,
2988  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
2989  (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) |
2990  ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
2991 #else
2992  MODIFY_REG(RCC->PLLSAI1CFGR,
2993  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M,
2994  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
2995  ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) |
2996  ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
2997 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
2998 
2999 #else
3000  /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
3001 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
3002  MODIFY_REG(RCC->PLLSAI1CFGR,
3003  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
3004  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
3005  (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
3006 #else
3007  MODIFY_REG(RCC->PLLSAI1CFGR,
3008  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,
3009  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
3010  ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
3011 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
3012 
3013 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
3014  }
3015  else if(Divider == DIVIDER_Q_UPDATE)
3016  {
3017  assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q));
3018 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
3019  /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/
3020  MODIFY_REG(RCC->PLLSAI1CFGR,
3021  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M,
3022  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
3023  (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
3024  ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
3025 #else
3026  /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
3027  MODIFY_REG(RCC->PLLSAI1CFGR,
3028  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
3029  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
3030  (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos));
3031 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
3032  }
3033  else
3034  {
3035  assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R));
3036 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
3037  /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/
3038  MODIFY_REG(RCC->PLLSAI1CFGR,
3039  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M,
3040  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
3041  (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
3042  ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
3043 #else
3044  /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
3045  MODIFY_REG(RCC->PLLSAI1CFGR,
3046  RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
3047  (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
3048  (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
3049 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
3050  }
3051 
3052  /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
3053  __HAL_RCC_PLLSAI1_ENABLE();
3054 
3055  /* Get Start Tick*/
3056  tickstart = HAL_GetTick();
3057 
3058  /* Wait till PLLSAI1 is ready */
3059  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
3060  {
3061  if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
3062  {
3063  status = HAL_TIMEOUT;
3064  break;
3065  }
3066  }
3067 
3068  if(status == HAL_OK)
3069  {
3070  /* Configure the PLLSAI1 Clock output(s) */
3071  __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
3072  }
3073  }
3074  }
3075 
3076  return status;
3077 }
3078 
3079 #endif /* RCC_PLLSAI1_SUPPORT */
3080 
3081 #if defined(RCC_PLLSAI2_SUPPORT)
3082 
3093 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
3094 {
3095  uint32_t tickstart;
3096  HAL_StatusTypeDef status = HAL_OK;
3097 
3098  /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */
3099  /* P, Q and R dividers are verified in each specific divider case below */
3100  assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source));
3101  assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
3102  assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
3103  assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
3104 
3105  /* Check that PLLSAI2 clock source and divider M can be applied */
3106  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
3107  {
3108  /* PLL clock source and divider M already set, check that no request for change */
3109  if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
3110  ||
3111  (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
3112 #if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3113  ||
3114  (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
3115 #endif
3116  )
3117  {
3118  status = HAL_ERROR;
3119  }
3120  }
3121  else
3122  {
3123  /* Check PLLSAI2 clock source availability */
3124  switch(PllSai2->PLLSAI2Source)
3125  {
3126  case RCC_PLLSOURCE_MSI:
3127  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
3128  {
3129  status = HAL_ERROR;
3130  }
3131  break;
3132  case RCC_PLLSOURCE_HSI:
3133  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
3134  {
3135  status = HAL_ERROR;
3136  }
3137  break;
3138  case RCC_PLLSOURCE_HSE:
3139  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
3140  {
3141  if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
3142  {
3143  status = HAL_ERROR;
3144  }
3145  }
3146  break;
3147  default:
3148  status = HAL_ERROR;
3149  break;
3150  }
3151 
3152  if(status == HAL_OK)
3153  {
3154 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3155  /* Set PLLSAI2 clock source */
3156  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
3157 #else
3158  /* Set PLLSAI2 clock source and divider M */
3159  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
3160 #endif
3161  }
3162  }
3163 
3164  if(status == HAL_OK)
3165  {
3166  /* Disable the PLLSAI2 */
3167  __HAL_RCC_PLLSAI2_DISABLE();
3168 
3169  /* Get Start Tick*/
3170  tickstart = HAL_GetTick();
3171 
3172  /* Wait till PLLSAI2 is ready to be updated */
3173  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
3174  {
3175  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
3176  {
3177  status = HAL_TIMEOUT;
3178  break;
3179  }
3180  }
3181 
3182  if(status == HAL_OK)
3183  {
3184  if(Divider == DIVIDER_P_UPDATE)
3185  {
3186  assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P));
3187 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3188 
3189  /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/
3190 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
3191  MODIFY_REG(RCC->PLLSAI2CFGR,
3192  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M,
3193  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3194  (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) |
3195  ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
3196 #else
3197  MODIFY_REG(RCC->PLLSAI2CFGR,
3198  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M,
3199  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3200  ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) |
3201  ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
3202 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
3203 
3204 #else
3205  /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/
3206 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
3207  MODIFY_REG(RCC->PLLSAI2CFGR,
3208  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
3209  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3210  (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
3211 #else
3212  MODIFY_REG(RCC->PLLSAI2CFGR,
3213  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,
3214  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3215  ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos));
3216 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
3217 
3218 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
3219  }
3220 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
3221  else if(Divider == DIVIDER_Q_UPDATE)
3222  {
3223  assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q));
3224 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3225  /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/
3226  MODIFY_REG(RCC->PLLSAI2CFGR,
3227  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M,
3228  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3229  (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) |
3230  ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
3231 #else
3232  /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/
3233  MODIFY_REG(RCC->PLLSAI2CFGR,
3234  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
3235  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3236  (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos));
3237 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
3238  }
3239 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
3240  else
3241  {
3242  assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R));
3243 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3244  /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/
3245  MODIFY_REG(RCC->PLLSAI2CFGR,
3246  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M,
3247  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3248  (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
3249  ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
3250 #else
3251  /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
3252  MODIFY_REG(RCC->PLLSAI2CFGR,
3253  RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
3254  (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
3255  (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
3256 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
3257  }
3258 
3259  /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
3260  __HAL_RCC_PLLSAI2_ENABLE();
3261 
3262  /* Get Start Tick*/
3263  tickstart = HAL_GetTick();
3264 
3265  /* Wait till PLLSAI2 is ready */
3266  while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
3267  {
3268  if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
3269  {
3270  status = HAL_TIMEOUT;
3271  break;
3272  }
3273  }
3274 
3275  if(status == HAL_OK)
3276  {
3277  /* Configure the PLLSAI2 Clock output(s) */
3278  __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
3279  }
3280  }
3281  }
3282 
3283  return status;
3284 }
3285 
3286 #endif /* RCC_PLLSAI2_SUPPORT */
3287 
3288 #if defined(SAI1)
3289 
3290 static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)
3291 {
3292  uint32_t frequency = 0U;
3293  uint32_t srcclk = 0U;
3294  uint32_t pllvco, plln; /* no init needed */
3295 #if defined(RCC_PLLP_SUPPORT)
3296  uint32_t pllp = 0U;
3297 #endif /* RCC_PLLP_SUPPORT */
3298 
3299  /* Handle SAIs */
3300  if(PeriphClk == RCC_PERIPHCLK_SAI1)
3301  {
3302  srcclk = __HAL_RCC_GET_SAI1_SOURCE();
3303  if(srcclk == RCC_SAI1CLKSOURCE_PIN)
3304  {
3305  frequency = EXTERNAL_SAI1_CLOCK_VALUE;
3306  }
3307  /* Else, PLL clock output to check below */
3308  }
3309 #if defined(SAI2)
3310  else
3311  {
3312  if(PeriphClk == RCC_PERIPHCLK_SAI2)
3313  {
3314  srcclk = __HAL_RCC_GET_SAI2_SOURCE();
3315  if(srcclk == RCC_SAI2CLKSOURCE_PIN)
3316  {
3317  frequency = EXTERNAL_SAI2_CLOCK_VALUE;
3318  }
3319  /* Else, PLL clock output to check below */
3320  }
3321  }
3322 #endif /* SAI2 */
3323 
3324  if(frequency == 0U)
3325  {
3326  pllvco = InputFrequency;
3327 
3328 #if defined(SAI2)
3329  if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
3330  {
3331  if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U)
3332  {
3333  /* f(PLL Source) / PLLM */
3334  pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
3335  /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
3336  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
3337 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3338  pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
3339 #endif
3340  if(pllp == 0U)
3341  {
3342  if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
3343  {
3344  pllp = 17U;
3345  }
3346  else
3347  {
3348  pllp = 7U;
3349  }
3350  }
3351  frequency = (pllvco * plln) / pllp;
3352  }
3353  }
3354  else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
3355  {
3356  if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)
3357  {
3358 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
3359  /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
3360  /* f(PLLSAI1 Source) / PLLSAI1M */
3361  pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
3362 #else
3363  /* f(PLL Source) / PLLM */
3364  pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
3365 #endif
3366  /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
3367  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
3368 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
3369  pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
3370 #endif
3371  if(pllp == 0U)
3372  {
3373  if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)
3374  {
3375  pllp = 17U;
3376  }
3377  else
3378  {
3379  pllp = 7U;
3380  }
3381  }
3382  frequency = (pllvco * plln) / pllp;
3383  }
3384  }
3385 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
3386  else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI))
3387  {
3388  if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
3389  {
3390  frequency = HSI_VALUE;
3391  }
3392  }
3393 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
3394 
3395 #else
3396  if(srcclk == RCC_SAI1CLKSOURCE_PLL)
3397  {
3398  if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U)
3399  {
3400  /* f(PLL Source) / PLLM */
3401  pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
3402  /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
3403  plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
3404 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3405  pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
3406 #endif
3407  if(pllp == 0U)
3408  {
3409  if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
3410  {
3411  pllp = 17U;
3412  }
3413  else
3414  {
3415  pllp = 7U;
3416  }
3417  }
3418  frequency = (pllvco * plln) / pllp;
3419  }
3420  else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
3421  {
3422  /* HSI automatically selected as clock source if PLLs not enabled */
3423  frequency = HSI_VALUE;
3424  }
3425  else
3426  {
3427  /* No clock source, frequency default init at 0 */
3428  }
3429  }
3430  else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
3431  {
3432  if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U)
3433  {
3434 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
3435  /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
3436  /* f(PLLSAI1 Source) / PLLSAI1M */
3437  pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
3438 #else
3439  /* f(PLL Source) / PLLM */
3440  pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
3441 #endif
3442  /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
3443  plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
3444 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
3445  pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
3446 #endif
3447  if(pllp == 0U)
3448  {
3449  if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)
3450  {
3451  pllp = 17U;
3452  }
3453  else
3454  {
3455  pllp = 7U;
3456  }
3457  }
3458  frequency = (pllvco * plln) / pllp;
3459  }
3460  else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
3461  {
3462  /* HSI automatically selected as clock source if PLLs not enabled */
3463  frequency = HSI_VALUE;
3464  }
3465  else
3466  {
3467  /* No clock source, frequency default init at 0 */
3468  }
3469  }
3470 #endif /* SAI2 */
3471 
3472 #if defined(RCC_PLLSAI2_SUPPORT)
3473 
3474  else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
3475  {
3476  if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U)
3477  {
3478 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3479  /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */
3480  /* f(PLLSAI2 Source) / PLLSAI2M */
3481  pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));
3482 #else
3483  /* f(PLL Source) / PLLM */
3484  pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
3485 #endif
3486  /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
3487  plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
3488 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
3489  pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos;
3490 #endif
3491  if(pllp == 0U)
3492  {
3493  if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U)
3494  {
3495  pllp = 17U;
3496  }
3497  else
3498  {
3499  pllp = 7U;
3500  }
3501  }
3502  frequency = (pllvco * plln) / pllp;
3503  }
3504  }
3505 
3506 #endif /* RCC_PLLSAI2_SUPPORT */
3507 
3508  else
3509  {
3510  /* No clock source, frequency default init at 0 */
3511  }
3512  }
3513 
3514 
3515  return frequency;
3516 }
3517 
3518 #endif /* SAI1 */
3519 
3528 #endif /* HAL_RCC_MODULE_ENABLED */
3529 
3537 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3538 
RCC_PLLSAI2InitTypeDef::PLLSAI2ClockOut
uint32_t PLLSAI2ClockOut
Definition: stm32l4xx_hal_rcc_ex.h:112
RCC_CRSInitTypeDef::ErrorLimitValue
uint32_t ErrorLimitValue
Definition: stm32l4xx_hal_rcc_ex.h:292
RCC_PLLSAI2InitTypeDef
PLLSAI2 Clock structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:84
HAL_RCCEx_CRS_ExpectedSyncCallback
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2836
RCC_PeriphCLKInitTypeDef::I2c2ClockSelection
uint32_t I2c2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:172
RCC_PeriphCLKInitTypeDef::OspiClockSelection
uint32_t OspiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:263
HAL_RCCEx_EnableLSCO
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
Definition: stm32l4xx_hal_rcc_ex.c:2405
RCC_PLLSAI2InitTypeDef::PLLSAI2Source
uint32_t PLLSAI2Source
Definition: stm32l4xx_hal_rcc_ex.h:87
RCC_CRSSynchroInfoTypeDef::ReloadValue
uint32_t ReloadValue
Definition: stm32l4xx_hal_rcc_ex.h:306
HAL_RCCEx_DisablePLLSAI2
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
Disable PLLISAI2.
Definition: stm32l4xx_hal_rcc_ex.c:2252
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:123
RCC_PeriphCLKInitTypeDef::Uart4ClockSelection
uint32_t Uart4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:152
RCC_CRSSynchroInfoTypeDef::FreqErrorCapture
uint32_t FreqErrorCapture
Definition: stm32l4xx_hal_rcc_ex.h:312
RCC_PeriphCLKInitTypeDef::Sai2ClockSelection
uint32_t Sai2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:200
RCC_CRSInitTypeDef::Polarity
uint32_t Polarity
Definition: stm32l4xx_hal_rcc_ex.h:285
RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition: stm32l4xx_hal_rcc_ex.h:309
RCC_PLLSAI2InitTypeDef::PLLSAI2P
uint32_t PLLSAI2P
Definition: stm32l4xx_hal_rcc_ex.h:101
stm32l4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
Generate the software synchronization event.
Definition: stm32l4xx_hal_rcc_ex.c:2623
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:223
HAL_RCCEx_EnablePLLSAI1
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
Definition: stm32l4xx_hal_rcc_ex.c:2056
PeriphClk
__STATIC_INLINE void uint32_t PeriphClk
Definition: stm32l4xx_ll_lpuart.h:1431
RCC_PeriphCLKInitTypeDef::I2c1ClockSelection
uint32_t I2c1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:167
HAL_RCCEx_CRS_SyncOkCallback
void HAL_RCCEx_CRS_SyncOkCallback(void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2814
RCC_PeriphCLKInitTypeDef::I2c3ClockSelection
uint32_t I2c3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:177
HAL_RCCEx_CRSWaitSynchronization
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
Wait for CRS Synchronization status.
Definition: stm32l4xx_hal_rcc_ex.c:2666
RCC_PeriphCLKInitTypeDef::PLLSAI1
RCC_PLLSAI1InitTypeDef PLLSAI1
Definition: stm32l4xx_hal_rcc_ex.h:127
HAL_RCCEx_EnablePLLSAI2
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
Enable PLLSAI2.
Definition: stm32l4xx_hal_rcc_ex.c:2174
RCC_PLLSAI2InitTypeDef::PLLSAI2Q
uint32_t PLLSAI2Q
Definition: stm32l4xx_hal_rcc_ex.h:105
HAL_PWR_DisableBkUpAccess
void HAL_PWR_DisableBkUpAccess(void)
Disable access to the backup domain (RTC registers, RTC backup data registers).
Definition: stm32l4xx_hal_pwr.c:115
HAL_RCCEx_CRS_IRQHandler
void HAL_RCCEx_CRS_IRQHandler(void)
Handle the Clock Recovery System interrupt request.
Definition: stm32l4xx_hal_rcc_ex.c:2749
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:182
HAL_GetTick
uint32_t HAL_GetTick(void)
Provide a tick value in millisecond.
Definition: stm32l4xx_hal.c:337
RCC_CRSInitTypeDef::ReloadValue
uint32_t ReloadValue
Definition: stm32l4xx_hal_rcc_ex.h:288
RCC_CRSInitTypeDef
RCC_CRS Init structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:277
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
Return the PCLK2 frequency.
Definition: stm32l4xx_hal_rcc.c:1457
HAL_RCCEx_LSECSS_IRQHandler
void HAL_RCCEx_LSECSS_IRQHandler(void)
Handle the RCC LSE Clock Security System interrupt request.
Definition: stm32l4xx_hal_rcc_ex.c:2373
HAL_RCCEx_DisableLSCO
void HAL_RCCEx_DisableLSCO(void)
Disable the Low Speed clock output.
Definition: stm32l4xx_hal_rcc_ex.c:2452
CLEAR_BIT
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE)
RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:229
RCC_CRSInitTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition: stm32l4xx_hal_rcc_ex.h:295
HAL_RCCEx_CRS_ErrorCallback
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2852
RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:164
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:121
RCC_PLLSAI2InitTypeDef::PLLSAI2R
uint32_t PLLSAI2R
Definition: stm32l4xx_hal_rcc_ex.h:109
HAL_PWR_EnableBkUpAccess
void HAL_PWR_EnableBkUpAccess(void)
Enable access to the backup domain (RTC registers, RTC backup data registers).
Definition: stm32l4xx_hal_pwr.c:105
RCC_PLLSAI2InitTypeDef::PLLSAI2N
uint32_t PLLSAI2N
Definition: stm32l4xx_hal_rcc_ex.h:98
HAL_OK
return HAL_OK
Definition: stm32l4xx_hal_rtc_ex.c:885
RCC_PeriphCLKInitTypeDef::Usart1ClockSelection
uint32_t Usart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:137
RCC_PLLSAI2InitTypeDef::PLLSAI2M
uint32_t PLLSAI2M
Definition: stm32l4xx_hal_rcc_ex.h:91
HAL_RCCEx_WakeUpStopCLKConfig
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
Definition: stm32l4xx_hal_rcc_ex.c:2301
RCC_PeriphCLKInitTypeDef::Uart5ClockSelection
uint32_t Uart5ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:159
RCC_PeriphCLKInitTypeDef::Dfsdm1AudioClockSelection
uint32_t Dfsdm1AudioClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:240
HAL_RCCEx_DisableLSECSS
void HAL_RCCEx_DisableLSECSS(void)
Disable the LSE Clock Security System.
Definition: stm32l4xx_hal_rcc_ex.c:2343
RCC_CRSSynchroInfoTypeDef::FreqErrorDirection
uint32_t FreqErrorDirection
Definition: stm32l4xx_hal_rcc_ex.h:316
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:236
RCCEx_PLLSAI2_Config
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s)...
Definition: stm32l4xx_hal_rcc_ex.c:3093
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_Perip...
Definition: stm32l4xx_hal_rcc_ex.c:196
RCC_PeriphCLKInitTypeDef::Usart2ClockSelection
uint32_t Usart2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:140
RCCEx_PLLSAI1_Config
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s)...
Definition: stm32l4xx_hal_rcc_ex.c:2888
HAL_GPIO_Init
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
Definition: stm32l4xx_hal_gpio.c:172
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
Definition: stm32l4xx_hal_rcc_ex.c:826
HAL_RCCEx_DisablePLLSAI1
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
Disable PLLSAI1.
Definition: stm32l4xx_hal_rcc_ex.c:2124
HAL_RCCEx_DisableMSIPLLMode
void HAL_RCCEx_DisableMSIPLLMode(void)
Disable the PLL-mode of the MSI.
Definition: stm32l4xx_hal_rcc_ex.c:2500
RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:190
RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:304
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:187
HAL_RCCEx_EnableLSECSS_IT
void HAL_RCCEx_EnableLSECSS_IT(void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
Definition: stm32l4xx_hal_rcc_ex.c:2356
HAL_RCCEx_StandbyMSIRangeConfig
void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
Configure the MSI range after standby mode.
Definition: stm32l4xx_hal_rcc_ex.c:2319
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:268
RCC_PeriphCLKInitTypeDef::LtdcClockSelection
uint32_t LtdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:249
RCC_CRSInitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32l4xx_hal_rcc_ex.h:279
HAL_RCCEx_EnableMSIPLLMode
void HAL_RCCEx_EnableMSIPLLMode(void)
Enable the PLL-mode of the MSI.
Definition: stm32l4xx_hal_rcc_ex.c:2490
HAL_RCCEx_LSECSS_Callback
void HAL_RCCEx_LSECSS_Callback(void)
RCCEx LSE Clock Security System interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2390
endif
ADC handle Structure definition.
Definition: stm32l4xx_hal_adc.h:360
RCC_CRSInitTypeDef::Source
uint32_t Source
Definition: stm32l4xx_hal_rcc_ex.h:282
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
Return the SYSCLK frequency.
Definition: stm32l4xx_hal_rcc.c:1346
MODIFY_REG
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL,(uint32_t) WakeUpClock)
RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection
uint32_t Sdmmc1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:214
RCCEx_GetSAIxPeriphCLKFreq
static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)
Definition: stm32l4xx_hal_rcc_ex.c:3290
RCC_PeriphCLKInitTypeDef::DsiClockSelection
uint32_t DsiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:256
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.
Definition: stm32l4xx_hal_rcc_ex.c:1152
HAL_RCCEx_CRSGetSynchronizationInfo
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
Definition: stm32l4xx_hal_rcc_ex.c:2633
RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:207
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
Return the PCLK1 frequency.
Definition: stm32l4xx_hal_rcc.c:1445
RCC_PeriphCLKInitTypeDef::PLLSAI2
RCC_PLLSAI2InitTypeDef PLLSAI2
Definition: stm32l4xx_hal_rcc_ex.h:132
HAL_RCCEx_CRSConfig
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
Definition: stm32l4xx_hal_rcc_ex.c:2580
HAL_RCCEx_CRS_SyncWarnCallback
void HAL_RCCEx_CRS_SyncWarnCallback(void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2825
RCC_PeriphCLKInitTypeDef::Usart3ClockSelection
uint32_t Usart3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:145
assert_param
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock))
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:194
HAL_RCCEx_EnableLSECSS
void HAL_RCCEx_EnableLSECSS(void)
Enable the LSE Clock Security System.
Definition: stm32l4xx_hal_rcc_ex.c:2333
RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:219