STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_rcc_ex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L4xx_HAL_RCC_EX_H
22 #define __STM32L4xx_HAL_RCC_EX_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
40 
45 #if defined(RCC_PLLSAI1_SUPPORT)
46 
49 typedef struct
50 {
51 
52  uint32_t PLLSAI1Source;
55 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
56  uint32_t PLLSAI1M;
58 #else
59  uint32_t PLLSAI1M;
61 #endif
62 
63  uint32_t PLLSAI1N;
66  uint32_t PLLSAI1P;
69  uint32_t PLLSAI1Q;
72  uint32_t PLLSAI1R;
75  uint32_t PLLSAI1ClockOut;
77 }RCC_PLLSAI1InitTypeDef;
78 #endif /* RCC_PLLSAI1_SUPPORT */
79 
80 #if defined(RCC_PLLSAI2_SUPPORT)
81 
84 typedef struct
85 {
86 
87  uint32_t PLLSAI2Source;
90 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
91  uint32_t PLLSAI2M;
93 #else
94  uint32_t PLLSAI2M;
96 #endif
97 
98  uint32_t PLLSAI2N;
101  uint32_t PLLSAI2P;
104 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
105  uint32_t PLLSAI2Q;
107 #endif
108 
109  uint32_t PLLSAI2R;
112  uint32_t PLLSAI2ClockOut;
114 }RCC_PLLSAI2InitTypeDef;
115 
116 #endif /* RCC_PLLSAI2_SUPPORT */
117 
121 typedef struct
122 {
123  uint32_t PeriphClockSelection;
125 #if defined(RCC_PLLSAI1_SUPPORT)
126 
127  RCC_PLLSAI1InitTypeDef PLLSAI1;
129 #endif /* RCC_PLLSAI1_SUPPORT */
130 #if defined(RCC_PLLSAI2_SUPPORT)
131 
132  RCC_PLLSAI2InitTypeDef PLLSAI2;
135 #endif /* RCC_PLLSAI2_SUPPORT */
136 
137  uint32_t Usart1ClockSelection;
140  uint32_t Usart2ClockSelection;
143 #if defined(USART3)
144 
145  uint32_t Usart3ClockSelection;
148 #endif /* USART3 */
149 
150 #if defined(UART4)
151 
152  uint32_t Uart4ClockSelection;
155 #endif /* UART4 */
156 
157 #if defined(UART5)
158 
159  uint32_t Uart5ClockSelection;
162 #endif /* UART5 */
163 
164  uint32_t Lpuart1ClockSelection;
167  uint32_t I2c1ClockSelection;
170 #if defined(I2C2)
171 
172  uint32_t I2c2ClockSelection;
175 #endif /* I2C2 */
176 
177  uint32_t I2c3ClockSelection;
180 #if defined(I2C4)
181 
182  uint32_t I2c4ClockSelection;
185 #endif /* I2C4 */
186 
187  uint32_t Lptim1ClockSelection;
190  uint32_t Lptim2ClockSelection;
192 #if defined(SAI1)
193 
194  uint32_t Sai1ClockSelection;
196 #endif /* SAI1 */
197 
198 #if defined(SAI2)
199 
200  uint32_t Sai2ClockSelection;
203 #endif /* SAI2 */
204 
205 #if defined(USB_OTG_FS) || defined(USB)
206 
207  uint32_t UsbClockSelection;
210 #endif /* USB_OTG_FS || USB */
211 
212 #if defined(SDMMC1)
213 
214  uint32_t Sdmmc1ClockSelection;
217 #endif /* SDMMC1 */
218 
219  uint32_t RngClockSelection;
222 #if !defined(STM32L412xx) && !defined(STM32L422xx)
223  uint32_t AdcClockSelection;
225 #endif /* !STM32L412xx && !STM32L422xx */
226 
227 #if defined(SWPMI1)
228 
229  uint32_t Swpmi1ClockSelection;
232 #endif /* SWPMI1 */
233 
234 #if defined(DFSDM1_Filter0)
235 
236  uint32_t Dfsdm1ClockSelection;
239 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
240  uint32_t Dfsdm1AudioClockSelection;
243 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
244 
245 #endif /* DFSDM1_Filter0 */
246 
247 #if defined(LTDC)
248 
249  uint32_t LtdcClockSelection;
252 #endif /* LTDC */
253 
254 #if defined(DSI)
255 
256  uint32_t DsiClockSelection;
259 #endif /* DSI */
260 
261 #if defined(OCTOSPI1) || defined(OCTOSPI2)
262 
263  uint32_t OspiClockSelection;
266 #endif
267 
268  uint32_t RTCClockSelection;
270 }RCC_PeriphCLKInitTypeDef;
271 
272 #if defined(CRS)
273 
277 typedef struct
278 {
279  uint32_t Prescaler;
282  uint32_t Source;
285  uint32_t Polarity;
288  uint32_t ReloadValue;
292  uint32_t ErrorLimitValue;
295  uint32_t HSI48CalibrationValue;
299 }RCC_CRSInitTypeDef;
300 
304 typedef struct
305 {
306  uint32_t ReloadValue;
309  uint32_t HSI48CalibrationValue;
312  uint32_t FreqErrorCapture;
316  uint32_t FreqErrorDirection;
321 }RCC_CRSSynchroInfoTypeDef;
322 
323 #endif /* CRS */
324 
328 /* Exported constants --------------------------------------------------------*/
336 #define RCC_LSCOSOURCE_LSI 0x00000000U
337 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL
345 #define RCC_PERIPHCLK_USART1 0x00000001U
346 #define RCC_PERIPHCLK_USART2 0x00000002U
347 #if defined(USART3)
348 #define RCC_PERIPHCLK_USART3 0x00000004U
349 #endif
350 #if defined(UART4)
351 #define RCC_PERIPHCLK_UART4 0x00000008U
352 #endif
353 #if defined(UART5)
354 #define RCC_PERIPHCLK_UART5 0x00000010U
355 #endif
356 #define RCC_PERIPHCLK_LPUART1 0x00000020U
357 #define RCC_PERIPHCLK_I2C1 0x00000040U
358 #if defined(I2C2)
359 #define RCC_PERIPHCLK_I2C2 0x00000080U
360 #endif
361 #define RCC_PERIPHCLK_I2C3 0x00000100U
362 #define RCC_PERIPHCLK_LPTIM1 0x00000200U
363 #define RCC_PERIPHCLK_LPTIM2 0x00000400U
364 #if defined(SAI1)
365 #define RCC_PERIPHCLK_SAI1 0x00000800U
366 #endif
367 #if defined(SAI2)
368 #define RCC_PERIPHCLK_SAI2 0x00001000U
369 #endif
370 #if defined(USB_OTG_FS) || defined(USB)
371 #define RCC_PERIPHCLK_USB 0x00002000U
372 #endif
373 #define RCC_PERIPHCLK_ADC 0x00004000U
374 #if defined(SWPMI1)
375 #define RCC_PERIPHCLK_SWPMI1 0x00008000U
376 #endif
377 #if defined(DFSDM1_Filter0)
378 #define RCC_PERIPHCLK_DFSDM1 0x00010000U
379 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
380 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U
381 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
382 #endif
383 #define RCC_PERIPHCLK_RTC 0x00020000U
384 #define RCC_PERIPHCLK_RNG 0x00040000U
385 #if defined(SDMMC1)
386 #define RCC_PERIPHCLK_SDMMC1 0x00080000U
387 #endif
388 #if defined(I2C4)
389 #define RCC_PERIPHCLK_I2C4 0x00100000U
390 #endif
391 #if defined(LTDC)
392 #define RCC_PERIPHCLK_LTDC 0x00400000U
393 #endif
394 #if defined(DSI)
395 #define RCC_PERIPHCLK_DSI 0x00800000U
396 #endif
397 #if defined(OCTOSPI1) || defined(OCTOSPI2)
398 #define RCC_PERIPHCLK_OSPI 0x01000000U
399 #endif
400 
408 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
409 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
410 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
411 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
412 
419 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
420 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
421 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
422 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
423 
427 #if defined(USART3)
428 
431 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
432 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
433 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
434 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
435 
438 #endif /* USART3 */
439 
440 #if defined(UART4)
441 
444 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
445 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
446 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
447 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
448 
451 #endif /* UART4 */
452 
453 #if defined(UART5)
454 
457 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
458 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
459 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
460 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
461 
464 #endif /* UART5 */
465 
469 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
470 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
471 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
472 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
473 
480 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
481 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
482 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
483 
487 #if defined(I2C2)
488 
491 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
492 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
493 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
494 
497 #endif /* I2C2 */
498 
502 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
503 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
504 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
505 
509 #if defined(I2C4)
510 
513 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
514 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
515 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
516 
519 #endif /* I2C4 */
520 
521 #if defined(SAI1)
522 
525 #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U
526 #if defined(RCC_PLLSAI2_SUPPORT)
527 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
528 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0
529 #else
530 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
531 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
532 #endif /* RCC_PLLSAI2_SUPPORT */
533 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
534 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1
535 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)
536 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2
537 #else
538 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
539 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
540 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
541 
544 #endif /* SAI1 */
545 
546 #if defined(SAI2)
547 
550 #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U
551 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
552 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0
553 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1
554 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)
555 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2
556 #else
557 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
558 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
559 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
560 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
561 
564 #endif /* SAI2 */
565 
569 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
570 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
571 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
572 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
573 
580 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
581 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
582 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
583 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
584 
588 #if defined(SDMMC1)
589 
592 #if defined(RCC_HSI48_SUPPORT)
593 #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U
594 #else
595 #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U
596 #endif /* RCC_HSI48_SUPPORT */
597 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
598 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
599 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
600 #if defined(RCC_CCIPR2_SDMMCSEL)
601 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL
602 #endif /* RCC_CCIPR2_SDMMCSEL */
603 
606 #endif /* SDMMC1 */
607 
611 #if defined(RCC_HSI48_SUPPORT)
612 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U
613 #else
614 #define RCC_RNGCLKSOURCE_NONE 0x00000000U
615 #endif /* RCC_HSI48_SUPPORT */
616 #if defined(RCC_PLLSAI1_SUPPORT)
617 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
618 #endif /* RCC_PLLSAI1_SUPPORT */
619 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
620 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
621 
625 #if defined(USB_OTG_FS) || defined(USB)
626 
629 #if defined(RCC_HSI48_SUPPORT)
630 #define RCC_USBCLKSOURCE_HSI48 0x00000000U
631 #else
632 #define RCC_USBCLKSOURCE_NONE 0x00000000U
633 #endif /* RCC_HSI48_SUPPORT */
634 #if defined(RCC_PLLSAI1_SUPPORT)
635 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
636 #endif /* RCC_PLLSAI1_SUPPORT */
637 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
638 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
639 
642 #endif /* USB_OTG_FS || USB */
643 
647 #define RCC_ADCCLKSOURCE_NONE 0x00000000U
648 #if defined(RCC_PLLSAI1_SUPPORT)
649 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
650 #endif /* RCC_PLLSAI1_SUPPORT */
651 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
652 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
653 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
654 #if defined(RCC_CCIPR_ADCSEL)
655 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
656 #else
657 #define RCC_ADCCLKSOURCE_SYSCLK 0x30000000U
658 #endif /* RCC_CCIPR_ADCSEL */
659 
663 #if defined(SWPMI1)
664 
667 #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U
668 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
669 
672 #endif /* SWPMI1 */
673 
674 #if defined(DFSDM1_Filter0)
675 
678 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
679 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
680 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL
681 #else
682 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
683 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
684 
688 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
689 
692 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U
693 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0
694 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1
695 
698 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
699 #endif /* DFSDM1_Filter0 */
700 
701 #if defined(LTDC)
702 
705 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U
706 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0
707 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1
708 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR
709 
712 #endif /* LTDC */
713 
714 #if defined(DSI)
715 
718 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
719 #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL
720 
723 #endif /* DSI */
724 
725 #if defined(OCTOSPI1) || defined(OCTOSPI2)
726 
729 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U
730 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0
731 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1
732 
735 #endif /* OCTOSPI1 || OCTOSPI2 */
736 
740 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19
745 #if defined(CRS)
746 
750 #define RCC_CRS_NONE 0x00000000U
751 #define RCC_CRS_TIMEOUT 0x00000001U
752 #define RCC_CRS_SYNCOK 0x00000002U
753 #define RCC_CRS_SYNCWARN 0x00000004U
754 #define RCC_CRS_SYNCERR 0x00000008U
755 #define RCC_CRS_SYNCMISS 0x00000010U
756 #define RCC_CRS_TRIMOVF 0x00000020U
757 
764 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U
765 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0
766 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1
774 #define RCC_CRS_SYNC_DIV1 0x00000000U
775 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0
776 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1
777 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)
778 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2
779 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)
780 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)
781 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV
789 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U
790 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL
798 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
807 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U
815 #if defined(STM32L412xx) || defined(STM32L422xx)
816 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
819 #else
820 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
823 #endif
824 
831 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U
832 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR
840 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE
841 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE
842 #define RCC_CRS_IT_ERR CRS_CR_ERRIE
843 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE
844 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE
845 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE
846 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE
855 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF
856 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF
857 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF
858 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF
859 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR
860 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS
861 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF
867 #endif /* CRS */
868 
873 /* Exported macros -----------------------------------------------------------*/
878 #if defined(RCC_PLLSAI1_SUPPORT)
879 
913 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
914 
915 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
916 
917 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
918  MODIFY_REG(RCC->PLLSAI1CFGR, \
919  (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
920  RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \
921  ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \
922  ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
923  ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
924  ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
925  ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))
926 
927 #else
928 
929 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
930  MODIFY_REG(RCC->PLLSAI1CFGR, \
931  (RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
932  RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \
933  ((((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \
934  ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
935  ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
936  ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
937  (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))
938 
939 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
940 
941 #else
942 
943 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
944 
945 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
946  MODIFY_REG(RCC->PLLSAI1CFGR, \
947  (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
948  RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1PDIV), \
949  (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
950  ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
951  ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
952  ((uint32_t)(__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))
953 
954 #else
955 
956 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
957  MODIFY_REG(RCC->PLLSAI1CFGR, \
958  (RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | \
959  RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R), \
960  (((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
961  ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
962  ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
963  (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)))
964 
965 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
966 
967 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
968 
984 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
985  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
986 
987 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
988 
1001 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \
1002  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
1003 
1004 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1005 
1019 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1020 
1021 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
1022  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
1023 
1024 #else
1025 
1026 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
1027  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
1028 
1029 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1030 
1043 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
1044  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
1045 
1058 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
1059  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
1060 
1067 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
1068 
1069 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
1070 
1085 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
1086 
1087 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
1088 
1100 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
1101 
1102 #endif /* RCC_PLLSAI1_SUPPORT */
1103 
1104 #if defined(RCC_PLLSAI2_SUPPORT)
1105 
1140 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1141 
1142 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
1143 
1144 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \
1145  MODIFY_REG(RCC->PLLSAI2CFGR, \
1146  (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
1147  RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
1148  ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
1149  ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
1150  ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \
1151  ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
1152  ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
1153 
1154 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1155 
1156 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
1157  MODIFY_REG(RCC->PLLSAI2CFGR, \
1158  (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
1159  RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
1160  ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
1161  ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
1162  ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
1163  ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
1164 
1165 # else
1166 
1167 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
1168  MODIFY_REG(RCC->PLLSAI2CFGR, \
1169  (RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
1170  RCC_PLLSAI2CFGR_PLLSAI2R), \
1171  ((((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
1172  ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
1173  ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
1174  (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))
1175 
1176 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
1177 
1178 #else
1179 
1180 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
1181 
1182 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \
1183  MODIFY_REG(RCC->PLLSAI2CFGR, \
1184  (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
1185  RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
1186  (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
1187  ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \
1188  ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
1189  ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
1190 
1191 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1192 
1193 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
1194  MODIFY_REG(RCC->PLLSAI2CFGR, \
1195  (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
1196  RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
1197  (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
1198  ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
1199  ((uint32_t)(__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
1200 
1201 # else
1202 
1203 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
1204  MODIFY_REG(RCC->PLLSAI2CFGR, \
1205  (RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | \
1206  RCC_PLLSAI2CFGR_PLLSAI2R), \
1207  (((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
1208  ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
1209  (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)))
1210 
1211 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
1212 
1213 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
1214 
1215 
1231 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
1232  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
1233 
1234 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1235 
1248 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \
1249  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)
1250 
1251 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
1252 
1265 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
1266  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
1267 
1268 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
1269 
1282 #define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \
1283  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
1284 
1285 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
1286 
1299 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
1300  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
1301 
1308 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
1309 
1310 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
1311 
1336 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
1337 
1338 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
1339 
1361 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
1362 
1363 #endif /* RCC_PLLSAI2_SUPPORT */
1364 
1365 #if defined(SAI1)
1366 
1388 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1389 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
1390  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__))
1391 #else
1392 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
1393  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
1394 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1395 
1409 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1410 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))
1411 #else
1412 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
1413 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1414 
1415 #endif /* SAI1 */
1416 
1417 #if defined(SAI2)
1418 
1434 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1435 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
1436  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__))
1437 #else
1438 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
1439  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))
1440 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1441 
1449 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1450 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))
1451 #else
1452 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))
1453 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1454 
1455 #endif /* SAI2 */
1456 
1466 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
1467  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
1468 
1475 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
1476 
1477 #if defined(I2C2)
1478 
1488 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
1489  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
1490 
1497 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
1498 
1499 #endif /* I2C2 */
1500 
1510 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
1511  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
1512 
1519 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
1520 
1521 #if defined(I2C4)
1522 
1532 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
1533  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
1534 
1541 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
1542 
1543 #endif /* I2C4 */
1544 
1545 
1556 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
1557  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
1558 
1566 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
1567 
1578 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
1579  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
1580 
1588 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
1589 
1590 #if defined(USART3)
1591 
1602 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
1603  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
1604 
1612 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
1613 
1614 #endif /* USART3 */
1615 
1616 #if defined(UART4)
1617 
1628 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
1629  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
1630 
1638 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
1639 
1640 #endif /* UART4 */
1641 
1642 #if defined(UART5)
1643 
1654 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
1655  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
1656 
1664 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
1665 
1666 #endif /* UART5 */
1667 
1678 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
1679  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
1680 
1688 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
1689 
1700 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
1701  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
1702 
1710 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
1711 
1722 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
1723  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))
1724 
1732 #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))
1733 
1734 #if defined(SDMMC1)
1735 
1767 #if defined(RCC_CCIPR2_SDMMCSEL)
1768 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
1769  do \
1770  { \
1771  if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \
1772  { \
1773  SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
1774  } \
1775  else \
1776  { \
1777  CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
1778  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \
1779  } \
1780  } while(0)
1781 #else
1782 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
1783  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))
1784 #endif /* RCC_CCIPR2_SDMMCSEL */
1785 
1806 #if defined(RCC_CCIPR2_SDMMCSEL)
1807 #define __HAL_RCC_GET_SDMMC1_SOURCE() \
1808  ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
1809 #else
1810 #define __HAL_RCC_GET_SDMMC1_SOURCE() \
1811  (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
1812 #endif /* RCC_CCIPR2_SDMMCSEL */
1813 
1814 #endif /* SDMMC1 */
1815 
1833 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
1834  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
1835 
1848 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
1849 
1850 #if defined(USB_OTG_FS) || defined(USB)
1851 
1869 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
1870  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
1871 
1884 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
1885 
1886 #endif /* USB_OTG_FS || USB */
1887 
1888 #if defined(RCC_CCIPR_ADCSEL)
1889 
1901 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
1902  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))
1903 
1913 #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))
1914 #else
1915 
1921 #define __HAL_RCC_GET_ADC_SOURCE() ((__HAL_RCC_ADC_IS_CLK_ENABLED() != 0U) ? RCC_ADCCLKSOURCE_SYSCLK : RCC_ADCCLKSOURCE_NONE)
1922 
1923 #endif /* RCC_CCIPR_ADCSEL */
1924 
1925 #if defined(SWPMI1)
1926 
1934 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
1935  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))
1936 
1942 #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))
1943 
1944 #endif /* SWPMI1 */
1945 
1946 #if defined(DFSDM1_Filter0)
1947 
1954 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1955 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
1956  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
1957 #else
1958 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
1959  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
1960 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1961 
1967 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1968 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))
1969 #else
1970 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))
1971 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1972 
1973 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
1974 
1983 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
1984  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__))
1985 
1992 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))
1993 
1994 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1995 
1996 #endif /* DFSDM1_Filter0 */
1997 
1998 #if defined(LTDC)
1999 
2009 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \
2010  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__))
2011 
2019 #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))
2020 
2021 #endif /* LTDC */
2022 
2023 #if defined(DSI)
2024 
2032 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \
2033  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__))
2034 
2040 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))
2041 
2042 #endif /* DSI */
2043 
2044 #if defined(OCTOSPI1) || defined(OCTOSPI2)
2045 
2054 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \
2055  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__))
2056 
2063 #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))
2064 
2065 #endif /* OCTOSPI1 || OCTOSPI2 */
2066 
2071 #if defined(RCC_PLLSAI1_SUPPORT)
2072 
2076 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
2077 
2081 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
2082 
2086 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
2087 
2091 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
2092 
2096 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
2097 
2098 #endif /* RCC_PLLSAI1_SUPPORT */
2099 
2100 #if defined(RCC_PLLSAI2_SUPPORT)
2101 
2105 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
2106 
2110 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
2111 
2115 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
2116 
2120 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
2121 
2125 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
2126 
2127 #endif /* RCC_PLLSAI2_SUPPORT */
2128 
2129 
2134 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
2135 
2140 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
2141 
2146 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
2147 
2152 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
2153 
2154 
2159 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
2160 
2161 
2166 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
2167 
2168 
2173 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
2174 
2179 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
2180 
2185 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
2186  do { \
2187  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
2188  __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
2189  } while(0)
2190 
2195 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
2196  do { \
2197  __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
2198  __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
2199  } while(0)
2200 
2205 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
2206 
2211 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
2212 
2217 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
2218 
2219 
2220 #if defined(CRS)
2221 
2232 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
2233 
2244 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
2245 
2255 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
2256 
2268 /* CRS IT Error Mask */
2269 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
2270 
2271 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
2272  if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
2273  { \
2274  WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
2275  } \
2276  else \
2277  { \
2278  WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
2279  } \
2280  } while(0)
2281 
2295 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
2296 
2312 /* CRS Flag Error Mask */
2313 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
2314 
2315 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
2316  if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
2317  { \
2318  WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
2319  } \
2320  else \
2321  { \
2322  WRITE_REG(CRS->ICR, (__FLAG__)); \
2323  } \
2324  } while(0)
2325 
2326 #endif /* CRS */
2327 
2332 #if defined(CRS)
2333 
2342 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
2343 
2348 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
2349 
2355 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
2356 
2361 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
2362 
2373 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
2374 
2379 #endif /* CRS */
2380 
2385 /* Exported functions --------------------------------------------------------*/
2394 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
2395 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
2396 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
2397 
2405 #if defined(RCC_PLLSAI1_SUPPORT)
2406 
2407 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
2408 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
2409 
2410 #endif /* RCC_PLLSAI1_SUPPORT */
2411 
2412 #if defined(RCC_PLLSAI2_SUPPORT)
2413 
2414 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
2415 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
2416 
2417 #endif /* RCC_PLLSAI2_SUPPORT */
2418 
2419 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
2420 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
2421 void HAL_RCCEx_EnableLSECSS(void);
2422 void HAL_RCCEx_DisableLSECSS(void);
2423 void HAL_RCCEx_EnableLSECSS_IT(void);
2424 void HAL_RCCEx_LSECSS_IRQHandler(void);
2425 void HAL_RCCEx_LSECSS_Callback(void);
2426 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
2427 void HAL_RCCEx_DisableLSCO(void);
2428 void HAL_RCCEx_EnableMSIPLLMode(void);
2429 void HAL_RCCEx_DisableMSIPLLMode(void);
2430 
2435 #if defined(CRS)
2436 
2441 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
2442 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
2443 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
2444 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
2445 void HAL_RCCEx_CRS_IRQHandler(void);
2446 void HAL_RCCEx_CRS_SyncOkCallback(void);
2447 void HAL_RCCEx_CRS_SyncWarnCallback(void);
2448 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
2449 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
2450 
2455 #endif /* CRS */
2456 
2461 /* Private macros ------------------------------------------------------------*/
2466 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
2467  ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
2468 
2469 #if defined(STM32L412xx) || defined(STM32L422xx)
2470 
2471 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2472  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2473  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2474  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2475  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2476  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2477  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2478  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2479  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2480  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2481  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2482  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2483  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2484  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
2485 
2486 #elif defined(STM32L431xx)
2487 
2488 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2489  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2490  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2491  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2492  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2493  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2494  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2495  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2496  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2497  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2498  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2499  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2500  (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
2501  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2502  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2503  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2504 
2505 #elif defined(STM32L432xx) || defined(STM32L442xx)
2506 
2507 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2508  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2509  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2510  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2511  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2512  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2513  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2514  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2515  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2516  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2517  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2518  (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
2519  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2520  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
2521 
2522 #elif defined(STM32L433xx) || defined(STM32L443xx)
2523 
2524 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2525  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2526  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2527  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2528  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2529  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2530  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2531  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2532  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2533  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2534  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2535  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2536  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2537  (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
2538  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2539  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2540  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2541 
2542 #elif defined(STM32L451xx)
2543 
2544 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2545  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2546  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2547  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2548  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2549  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2550  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2551  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2552  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2553  (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2554  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2555  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2556  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2557  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2558  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2559  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2560  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2561  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2562 
2563 #elif defined(STM32L452xx) || defined(STM32L462xx)
2564 
2565 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2566  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2567  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2568  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2569  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2570  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2571  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2572  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2573  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2574  (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2575  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2576  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2577  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2578  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2579  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2580  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2581  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2582  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2583  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2584 
2585 #elif defined(STM32L471xx)
2586 
2587 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2588  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2589  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2590  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2591  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2592  (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2593  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2594  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2595  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2596  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2597  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2598  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2599  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2600  (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2601  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2602  (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
2603  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2604  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2605  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2606  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2607 
2608 #elif defined(STM32L496xx) || defined(STM32L4A6xx)
2609 
2610 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2611  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2612  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2613  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2614  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2615  (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2616  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2617  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2618  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2619  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2620  (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2621  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2622  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2623  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2624  (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2625  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2626  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2627  (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
2628  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2629  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2630  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2631  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2632 
2633 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx)
2634 
2635 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2636  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2637  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2638  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2639  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2640  (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2641  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2642  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2643  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2644  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2645  (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2646  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2647  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2648  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2649  (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2650  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2651  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2652  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2653  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
2654  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2655  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2656  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
2657  (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI))
2658 
2659 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx)
2660 
2661 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2662  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2663  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2664  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2665  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2666  (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2667  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2668  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2669  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2670  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2671  (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2672  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2673  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2674  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2675  (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2676  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2677  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2678  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2679  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
2680  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2681  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2682  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
2683  (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
2684  (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
2685 
2686 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx)
2687 
2688 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2689  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2690  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2691  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2692  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2693  (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2694  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2695  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2696  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2697  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2698  (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
2699  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2700  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2701  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2702  (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2703  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2704  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2705  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2706  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
2707  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2708  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2709  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
2710  (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
2711  (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
2712  (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI))
2713 
2714 #else
2715 
2716 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
2717  ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
2718  (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
2719  (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
2720  (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
2721  (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
2722  (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
2723  (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
2724  (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
2725  (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
2726  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
2727  (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
2728  (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
2729  (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
2730  (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
2731  (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
2732  (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
2733  (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
2734  (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
2735  (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
2736  (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
2737 
2738 #endif /* STM32L412xx || STM32L422xx */
2739 
2740 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
2741  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
2742  ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
2743  ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
2744  ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
2745 
2746 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
2747  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
2748  ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
2749  ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
2750  ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
2751 
2752 #if defined(USART3)
2753 
2754 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
2755  (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
2756  ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
2757  ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
2758  ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
2759 
2760 #endif /* USART3 */
2761 
2762 #if defined(UART4)
2763 
2764 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
2765  (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
2766  ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
2767  ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
2768  ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
2769 
2770 #endif /* UART4 */
2771 
2772 #if defined(UART5)
2773 
2774 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
2775  (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
2776  ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
2777  ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
2778  ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
2779 
2780 #endif /* UART5 */
2781 
2782 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
2783  (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
2784  ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
2785  ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
2786  ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
2787 
2788 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
2789  (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
2790  ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
2791  ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
2792 
2793 #if defined(I2C2)
2794 
2795 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
2796  (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
2797  ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
2798  ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
2799 
2800 #endif /* I2C2 */
2801 
2802 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
2803  (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
2804  ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
2805  ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
2806 
2807 #if defined(I2C4)
2808 
2809 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
2810  (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
2811  ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
2812  ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
2813 
2814 #endif /* I2C4 */
2815 
2816 #if defined(RCC_PLLSAI2_SUPPORT)
2817 
2818 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
2819 #define IS_RCC_SAI1CLK(__SOURCE__) \
2820  (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
2821  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
2822  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
2823  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
2824  ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
2825 #else
2826 #define IS_RCC_SAI1CLK(__SOURCE__) \
2827  (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
2828  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
2829  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
2830  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
2831 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
2832 
2833 #elif defined(RCC_PLLSAI1_SUPPORT)
2834 
2835 #define IS_RCC_SAI1CLK(__SOURCE__) \
2836  (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
2837  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
2838  ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
2839 
2840 #endif /* RCC_PLLSAI2_SUPPORT */
2841 
2842 #if defined(RCC_PLLSAI2_SUPPORT)
2843 
2844 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
2845 #define IS_RCC_SAI2CLK(__SOURCE__) \
2846  (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
2847  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
2848  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
2849  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
2850  ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
2851 #else
2852 #define IS_RCC_SAI2CLK(__SOURCE__) \
2853  (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
2854  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
2855  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
2856  ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
2857 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
2858 
2859 #endif /* RCC_PLLSAI2_SUPPORT */
2860 
2861 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
2862  (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
2863  ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
2864  ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
2865  ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
2866 
2867 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
2868  (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
2869  ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
2870  ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
2871  ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
2872 
2873 #if defined(SDMMC1)
2874 #if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL)
2875 
2876 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
2877  (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \
2878  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
2879  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
2880  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
2881  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
2882 
2883 #elif defined(RCC_HSI48_SUPPORT)
2884 
2885 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
2886  (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
2887  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
2888  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
2889  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
2890 #else
2891 
2892 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
2893  (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
2894  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
2895  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
2896  ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
2897 
2898 #endif /* RCC_HSI48_SUPPORT */
2899 #endif /* SDMMC1 */
2900 
2901 #if defined(RCC_HSI48_SUPPORT)
2902 
2903 #if defined(RCC_PLLSAI1_SUPPORT)
2904 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
2905  (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
2906  ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
2907  ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
2908  ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
2909 #else
2910 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
2911  (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
2912  ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
2913  ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
2914 #endif /* RCC_PLLSAI1_SUPPORT */
2915 
2916 #else
2917 
2918 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
2919  (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
2920  ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
2921  ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
2922  ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
2923 
2924 #endif /* RCC_HSI48_SUPPORT */
2925 
2926 #if defined(USB_OTG_FS) || defined(USB)
2927 #if defined(RCC_HSI48_SUPPORT)
2928 
2929 #if defined(RCC_PLLSAI1_SUPPORT)
2930 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
2931  (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
2932  ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
2933  ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
2934  ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
2935 #else
2936 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
2937  (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
2938  ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
2939  ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
2940 #endif /* RCC_PLLSAI1_SUPPORT */
2941 
2942 #else
2943 
2944 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
2945  (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
2946  ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
2947  ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
2948  ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
2949 
2950 #endif /* RCC_HSI48_SUPPORT */
2951 #endif /* USB_OTG_FS || USB */
2952 
2953 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
2954 
2955 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
2956  (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
2957  ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
2958  ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
2959  ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
2960 
2961 #else
2962 
2963 #if defined(RCC_PLLSAI1_SUPPORT)
2964 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
2965  (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
2966  ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
2967  ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
2968 #else
2969 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
2970  (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
2971  ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
2972 #endif /* RCC_PLLSAI1_SUPPORT */
2973 
2974 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
2975 
2976 #if defined(SWPMI1)
2977 
2978 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
2979  (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \
2980  ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
2981 
2982 #endif /* SWPMI1 */
2983 
2984 #if defined(DFSDM1_Filter0)
2985 
2986 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
2987  (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
2988  ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
2989 
2990 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
2991 
2992 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \
2993  (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
2994  ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \
2995  ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))
2996 
2997 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
2998 
2999 #endif /* DFSDM1_Filter0 */
3000 
3001 #if defined(LTDC)
3002 
3003 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
3004  (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \
3005  ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \
3006  ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \
3007  ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16))
3008 
3009 #endif /* LTDC */
3010 
3011 #if defined(DSI)
3012 
3013 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \
3014  (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \
3015  ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2))
3016 
3017 #endif /* DSI */
3018 
3019 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3020 
3021 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
3022  (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
3023  ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \
3024  ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))
3025 
3026 #endif /* OCTOSPI1 || OCTOSPI2 */
3027 
3028 #if defined(RCC_PLLSAI1_SUPPORT)
3029 
3030 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
3031 
3032 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
3033 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
3034 #else
3035 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
3036 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
3037 
3038 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
3039 
3040 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
3041 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
3042 #else
3043 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
3044 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
3045 
3046 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
3047  ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
3048 
3049 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
3050  ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
3051 
3052 #endif /* RCC_PLLSAI1_SUPPORT */
3053 
3054 #if defined(RCC_PLLSAI2_SUPPORT)
3055 
3056 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
3057 
3058 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
3059 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
3060 #else
3061 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
3062 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
3063 
3064 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
3065 
3066 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
3067 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
3068 #else
3069 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
3070 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
3071 
3072 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
3073 #define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
3074  ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
3075 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
3076 
3077 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
3078  ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
3079 
3080 #endif /* RCC_PLLSAI2_SUPPORT */
3081 
3082 #if defined(CRS)
3083 
3084 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
3085  ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
3086  ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
3087 
3088 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
3089  ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
3090  ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
3091  ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
3092 
3093 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
3094  ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
3095 
3096 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
3097 
3098 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
3099 
3100 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
3101 
3102 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
3103  ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
3104 
3105 #endif /* CRS */
3106 
3119 #ifdef __cplusplus
3120 }
3121 #endif
3122 
3123 #endif /* __STM32L4xx_HAL_RCC_EX_H */
3124 
3125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_PLLSAI2InitTypeDef::PLLSAI2ClockOut
uint32_t PLLSAI2ClockOut
Definition: stm32l4xx_hal_rcc_ex.h:112
RCC_CRSInitTypeDef::ErrorLimitValue
uint32_t ErrorLimitValue
Definition: stm32l4xx_hal_rcc_ex.h:292
RCC_PLLSAI2InitTypeDef
PLLSAI2 Clock structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:84
HAL_RCCEx_CRS_ExpectedSyncCallback
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
RCCEx Clock Recovery System Expected SYNC interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2836
RCC_PeriphCLKInitTypeDef::I2c2ClockSelection
uint32_t I2c2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:172
RCC_PeriphCLKInitTypeDef::OspiClockSelection
uint32_t OspiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:263
HAL_RCCEx_EnableLSCO
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
Select the Low Speed clock source to output on LSCO pin (PA2).
Definition: stm32l4xx_hal_rcc_ex.c:2405
RCC_PLLSAI2InitTypeDef::PLLSAI2Source
uint32_t PLLSAI2Source
Definition: stm32l4xx_hal_rcc_ex.h:87
RCC_CRSSynchroInfoTypeDef::ReloadValue
uint32_t ReloadValue
Definition: stm32l4xx_hal_rcc_ex.h:306
HAL_RCCEx_DisablePLLSAI2
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void)
Disable PLLISAI2.
Definition: stm32l4xx_hal_rcc_ex.c:2252
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:123
RCC_PeriphCLKInitTypeDef::Uart4ClockSelection
uint32_t Uart4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:152
RCC_CRSSynchroInfoTypeDef::FreqErrorCapture
uint32_t FreqErrorCapture
Definition: stm32l4xx_hal_rcc_ex.h:312
RCC_PeriphCLKInitTypeDef::Sai2ClockSelection
uint32_t Sai2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:200
RCC_CRSInitTypeDef::Polarity
uint32_t Polarity
Definition: stm32l4xx_hal_rcc_ex.h:285
RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition: stm32l4xx_hal_rcc_ex.h:309
RCC_PLLSAI2InitTypeDef::PLLSAI2P
uint32_t PLLSAI2P
Definition: stm32l4xx_hal_rcc_ex.h:101
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
Generate the software synchronization event.
Definition: stm32l4xx_hal_rcc_ex.c:2623
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:223
HAL_RCCEx_EnablePLLSAI1
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
Enable PLLSAI1.
Definition: stm32l4xx_hal_rcc_ex.c:2056
PeriphClk
__STATIC_INLINE void uint32_t PeriphClk
Definition: stm32l4xx_ll_lpuart.h:1431
RCC_PeriphCLKInitTypeDef::I2c1ClockSelection
uint32_t I2c1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:167
HAL_RCCEx_CRS_SyncOkCallback
void HAL_RCCEx_CRS_SyncOkCallback(void)
RCCEx Clock Recovery System SYNCOK interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2814
RCC_PeriphCLKInitTypeDef::I2c3ClockSelection
uint32_t I2c3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:177
HAL_RCCEx_CRSWaitSynchronization
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
Wait for CRS Synchronization status.
Definition: stm32l4xx_hal_rcc_ex.c:2666
RCC_PeriphCLKInitTypeDef::PLLSAI1
RCC_PLLSAI1InitTypeDef PLLSAI1
Definition: stm32l4xx_hal_rcc_ex.h:127
HAL_RCCEx_EnablePLLSAI2
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
Enable PLLSAI2.
Definition: stm32l4xx_hal_rcc_ex.c:2174
RCC_PLLSAI2InitTypeDef::PLLSAI2Q
uint32_t PLLSAI2Q
Definition: stm32l4xx_hal_rcc_ex.h:105
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_RCCEx_CRS_IRQHandler
void HAL_RCCEx_CRS_IRQHandler(void)
Handle the Clock Recovery System interrupt request.
Definition: stm32l4xx_hal_rcc_ex.c:2749
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:182
RCC_CRSInitTypeDef::ReloadValue
uint32_t ReloadValue
Definition: stm32l4xx_hal_rcc_ex.h:288
RCC_CRSInitTypeDef
RCC_CRS Init structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:277
HAL_RCCEx_LSECSS_IRQHandler
void HAL_RCCEx_LSECSS_IRQHandler(void)
Handle the RCC LSE Clock Security System interrupt request.
Definition: stm32l4xx_hal_rcc_ex.c:2373
HAL_RCCEx_DisableLSCO
void HAL_RCCEx_DisableLSCO(void)
Disable the Low Speed clock output.
Definition: stm32l4xx_hal_rcc_ex.c:2452
RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:229
RCC_CRSInitTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition: stm32l4xx_hal_rcc_ex.h:295
HAL_RCCEx_CRS_ErrorCallback
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
RCCEx Clock Recovery System Error interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2852
RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:164
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:121
RCC_PLLSAI2InitTypeDef::PLLSAI2R
uint32_t PLLSAI2R
Definition: stm32l4xx_hal_rcc_ex.h:109
RCC_PLLSAI2InitTypeDef::PLLSAI2N
uint32_t PLLSAI2N
Definition: stm32l4xx_hal_rcc_ex.h:98
RCC_PeriphCLKInitTypeDef::Usart1ClockSelection
uint32_t Usart1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:137
RCC_PLLSAI2InitTypeDef::PLLSAI2M
uint32_t PLLSAI2M
Definition: stm32l4xx_hal_rcc_ex.h:91
HAL_RCCEx_WakeUpStopCLKConfig
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
Definition: stm32l4xx_hal_rcc_ex.c:2301
RCC_PeriphCLKInitTypeDef::Uart5ClockSelection
uint32_t Uart5ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:159
RCC_PeriphCLKInitTypeDef::Dfsdm1AudioClockSelection
uint32_t Dfsdm1AudioClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:240
HAL_RCCEx_DisableLSECSS
void HAL_RCCEx_DisableLSECSS(void)
Disable the LSE Clock Security System.
Definition: stm32l4xx_hal_rcc_ex.c:2343
RCC_CRSSynchroInfoTypeDef::FreqErrorDirection
uint32_t FreqErrorDirection
Definition: stm32l4xx_hal_rcc_ex.h:316
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:236
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_Perip...
Definition: stm32l4xx_hal_rcc_ex.c:196
RCC_PeriphCLKInitTypeDef::Usart2ClockSelection
uint32_t Usart2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:140
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
Definition: stm32l4xx_hal_rcc_ex.c:826
HAL_RCCEx_DisablePLLSAI1
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
Disable PLLSAI1.
Definition: stm32l4xx_hal_rcc_ex.c:2124
HAL_RCCEx_DisableMSIPLLMode
void HAL_RCCEx_DisableMSIPLLMode(void)
Disable the PLL-mode of the MSI.
Definition: stm32l4xx_hal_rcc_ex.c:2500
RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:190
RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition.
Definition: stm32l4xx_hal_rcc_ex.h:304
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:187
HAL_RCCEx_EnableLSECSS_IT
void HAL_RCCEx_EnableLSECSS_IT(void)
Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
Definition: stm32l4xx_hal_rcc_ex.c:2356
HAL_RCCEx_StandbyMSIRangeConfig
void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
Configure the MSI range after standby mode.
Definition: stm32l4xx_hal_rcc_ex.c:2319
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:268
RCC_PeriphCLKInitTypeDef::LtdcClockSelection
uint32_t LtdcClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:249
RCC_CRSInitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32l4xx_hal_rcc_ex.h:279
HAL_RCCEx_EnableMSIPLLMode
void HAL_RCCEx_EnableMSIPLLMode(void)
Enable the PLL-mode of the MSI.
Definition: stm32l4xx_hal_rcc_ex.c:2490
HAL_RCCEx_LSECSS_Callback
void HAL_RCCEx_LSECSS_Callback(void)
RCCEx LSE Clock Security System interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2390
RCC_CRSInitTypeDef::Source
uint32_t Source
Definition: stm32l4xx_hal_rcc_ex.h:282
RCC_PeriphCLKInitTypeDef::Sdmmc1ClockSelection
uint32_t Sdmmc1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:214
RCC_PeriphCLKInitTypeDef::DsiClockSelection
uint32_t DsiClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:256
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.
Definition: stm32l4xx_hal_rcc_ex.c:1152
HAL_RCCEx_CRSGetSynchronizationInfo
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
Return synchronization info.
Definition: stm32l4xx_hal_rcc_ex.c:2633
RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:207
RCC_PeriphCLKInitTypeDef::PLLSAI2
RCC_PLLSAI2InitTypeDef PLLSAI2
Definition: stm32l4xx_hal_rcc_ex.h:132
HAL_RCCEx_CRSConfig
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
Start automatic synchronization for polling mode.
Definition: stm32l4xx_hal_rcc_ex.c:2580
HAL_RCCEx_CRS_SyncWarnCallback
void HAL_RCCEx_CRS_SyncWarnCallback(void)
RCCEx Clock Recovery System SYNCWARN interrupt callback.
Definition: stm32l4xx_hal_rcc_ex.c:2825
RCC_PeriphCLKInitTypeDef::Usart3ClockSelection
uint32_t Usart3ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:145
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:194
HAL_RCCEx_EnableLSECSS
void HAL_RCCEx_EnableLSECSS(void)
Enable the LSE Clock Security System.
Definition: stm32l4xx_hal_rcc_ex.c:2333
RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Definition: stm32l4xx_hal_rcc_ex.h:219