TIM Private Functions

Functions
void	TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
	Time Base configuration. More...
void	TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
	Configure the TI1 as Input. More...
void	TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
	Timer Output Compare 2 configuration. More...
void	TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
	Configures the TIMx External Trigger (ETR). More...
void	TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Delay Pulse complete callback. More...
void	TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Delay Pulse half complete callback. More...
void	TIM_DMAError (DMA_HandleTypeDef *hdma)
	TIM DMA error callback. More...
void	TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Capture complete callback. More...
void	TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Capture half complete callback. More...
void	TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
	Enables or disables the TIM Capture Compare Channel x. More...
void	TIM_ResetCallback (TIM_HandleTypeDef *htim)
	Reset interrupt callbacks to the legacy weak callbacks. More...
static void	TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
	Timer Output Compare 1 configuration. More...
static void	TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
	Timer Output Compare 3 configuration. More...
static void	TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
	Timer Output Compare 4 configuration. More...
static void	TIM_OC5_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
	Timer Output Compare 5 configuration. More...
static void	TIM_OC6_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
	Timer Output Compare 6 configuration. More...
static void	TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
	Configure the Polarity and Filter for TI1. More...
static void	TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
	Configure the TI2 as Input. More...
static void	TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
	Configure the Polarity and Filter for TI2. More...
static void	TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
	Configure the TI3 as Input. More...
static void	TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
	Configure the TI4 as Input. More...
static void	TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
	Selects the Input Trigger source. More...
static void	TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Period Elapse complete callback. More...
static void	TIM_DMAPeriodElapsedHalfCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Period Elapse half complete callback. More...
static void	TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Trigger callback. More...
static void	TIM_DMATriggerHalfCplt (DMA_HandleTypeDef *hdma)
	TIM DMA Trigger half complete callback. More...
static HAL_StatusTypeDef	TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
	Slave Timer configuration function. More...

Detailed Description

Function Documentation

TIM_Base_SetConfig()

void TIM_Base_SetConfig	(	TIM_TypeDef *	TIMx,
		TIM_Base_InitTypeDef *	Structure
	)

Time Base configuration.

Parameters

TIMx	TIM peripheral
Structure	TIM Base configuration structure

Return values

None

Definition at line 5951 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);

  TIMx->CR1 = tmpcr1;

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
}

TIM_CCxChannelCmd()

void TIM_CCxChannelCmd	(	TIM_TypeDef *	TIMx,
		uint32_t	Channel,
		uint32_t	ChannelState
	)

Enables or disables the TIM Capture Compare Channel x.

Parameters

TIMx	to select the TIM peripheral
Channel	specifies the TIM Channel This parameter can be one of the following values: TIM_CHANNEL_1: TIM Channel 1 TIM_CHANNEL_2: TIM Channel 2 TIM_CHANNEL_3: TIM Channel 3 TIM_CHANNEL_4: TIM Channel 4 TIM_CHANNEL_5: TIM Channel 5 selected TIM_CHANNEL_6: TIM Channel 6 selected
ChannelState	specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.

Return values

None

Definition at line 6848 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmp;

  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  assert_param(IS_TIM_CHANNELS(Channel));

  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */

  /* Reset the CCxE Bit */
  TIMx->CCER &= ~tmp;

  /* Set or reset the CCxE Bit */
  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}

TIM_DMACaptureCplt()

void TIM_DMACaptureCplt

(

DMA_HandleTypeDef *

hdma

)

TIM DMA Capture complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5796 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  }
  else
  {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->IC_CaptureCallback(htim);
#else
  HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

TIM_DMACaptureHalfCplt()

void TIM_DMACaptureHalfCplt

(

DMA_HandleTypeDef *

hdma

)

TIM DMA Capture half complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5837 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  }
  else
  {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->IC_CaptureHalfCpltCallback(htim);
#else
  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

TIM_DMADelayPulseCplt()

void TIM_DMADelayPulseCplt

(

DMA_HandleTypeDef *

hdma

)

TIM DMA Delay Pulse complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5714 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  }
  else
  {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PWM_PulseFinishedCallback(htim);
#else
  HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

TIM_DMADelayPulseHalfCplt()

void TIM_DMADelayPulseHalfCplt

(

DMA_HandleTypeDef *

hdma

)

TIM DMA Delay Pulse half complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5755 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  }
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  }
  else
  {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PWM_PulseFinishedHalfCpltCallback(htim);
#else
  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

TIM_DMAError()

void TIM_DMAError

(

DMA_HandleTypeDef *

hdma

)

TIM DMA error callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5696 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->ErrorCallback(htim);
#else
  HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

TIM_DMAPeriodElapsedCplt()

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef *  hdma )

static

TIM DMA Period Elapse complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5878 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PeriodElapsedCallback(htim);
#else
  HAL_TIM_PeriodElapsedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

TIM_DMAPeriodElapsedHalfCplt()

static void TIM_DMAPeriodElapsedHalfCplt ( DMA_HandleTypeDef *  hdma )

static

TIM DMA Period Elapse half complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5896 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PeriodElapsedHalfCpltCallback(htim);
#else
  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

TIM_DMATriggerCplt()

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef *  hdma )

static

TIM DMA Trigger callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5914 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->TriggerCallback(htim);
#else
  HAL_TIM_TriggerCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

TIM_DMATriggerHalfCplt()

static void TIM_DMATriggerHalfCplt ( DMA_HandleTypeDef *  hdma )

static

TIM DMA Trigger half complete callback.

Parameters

hdma	pointer to DMA handle.

Return values

None

Definition at line 5932 of file stm32l4xx_hal_tim.c.

{
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->TriggerHalfCpltCallback(htim);
#else
  HAL_TIM_TriggerHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

TIM_ETR_SetConfig()

void TIM_ETR_SetConfig	(	TIM_TypeDef *	TIMx,
		uint32_t	TIM_ExtTRGPrescaler,
		uint32_t	TIM_ExtTRGPolarity,
		uint32_t	ExtTRGFilter
	)

Configures the TIMx External Trigger (ETR).

Parameters

TIMx	to select the TIM peripheral
TIM_ExtTRGPrescaler	The external Trigger Prescaler. This parameter can be one of the following values: TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity	The external Trigger Polarity. This parameter can be one of the following values: TIM_ETRPOLARITY_INVERTED: active low or falling edge active. TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
ExtTRGFilter	External Trigger Filter. This parameter must be a value between 0x00 and 0x0F

Return values

None

Definition at line 6816 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
}

TIM_ITRx_SetConfig()

static void TIM_ITRx_SetConfig ( TIM_TypeDef *  TIMx, uint32_t  InputTriggerSource  )

static

Selects the Input Trigger source.

Parameters

TIMx	to select the TIM peripheral
InputTriggerSource	The Input Trigger source. This parameter can be one of the following values: TIM_TS_ITR0: Internal Trigger 0 TIM_TS_ITR1: Internal Trigger 1 TIM_TS_ITR2: Internal Trigger 2 TIM_TS_ITR3: Internal Trigger 3 TIM_TS_TI1F_ED: TI1 Edge Detector TIM_TS_TI1FP1: Filtered Timer Input 1 TIM_TS_TI2FP2: Filtered Timer Input 2 TIM_TS_ETRF: External Trigger input

Return values

None

Definition at line 6786 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
}

TIM_OC1_SetConfig()

static void TIM_OC1_SetConfig ( TIM_TypeDef *  TIMx, TIM_OC_InitTypeDef *  OC_Config  )

static

Timer Output Compare 1 configuration.

Parameters

TIMx	to select the TIM peripheral
OC_Config	The ouput configuration structure

Return values

None

Definition at line 5999 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~TIM_CCMR1_OC1M;
  tmpccmrx &= ~TIM_CCMR1_CC1S;
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC1P;
  /* Set the Output Compare Polarity */
  tmpccer |= OC_Config->OCPolarity;

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
  {
    /* Check parameters */
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC1NP;
    /* Set the Output N Polarity */
    tmpccer |= OC_Config->OCNPolarity;
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC1NE;
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
  {
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS1;
    tmpcr2 &= ~TIM_CR2_OIS1N;
    /* Set the Output Idle state */
    tmpcr2 |= OC_Config->OCIdleState;
    /* Set the Output N Idle state */
    tmpcr2 |= OC_Config->OCNIdleState;
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

TIM_OC2_SetConfig()

void TIM_OC2_SetConfig	(	TIM_TypeDef *	TIMx,
		TIM_OC_InitTypeDef *	OC_Config
	)

Timer Output Compare 2 configuration.

Parameters

TIMx	to select the TIM peripheral
OC_Config	The ouput configuration structure

Return values

None

Definition at line 6074 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR1_OC2M;
  tmpccmrx &= ~TIM_CCMR1_CC2S;

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC2P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 4U);

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
  {
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC2NP;
    /* Set the Output N Polarity */
    tmpccer |= (OC_Config->OCNPolarity << 4U);
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC2NE;

  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
  {
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS2;
    tmpcr2 &= ~TIM_CR2_OIS2N;
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 2U);
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR2 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

TIM_OC3_SetConfig()

static void TIM_OC3_SetConfig ( TIM_TypeDef *  TIMx, TIM_OC_InitTypeDef *  OC_Config  )

static

Timer Output Compare 3 configuration.

Parameters

TIMx	to select the TIM peripheral
OC_Config	The ouput configuration structure

Return values

None

Definition at line 6150 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 3: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC3M;
  tmpccmrx &= ~TIM_CCMR2_CC3S;
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC3P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 8U);

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
  {
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC3NP;
    /* Set the Output N Polarity */
    tmpccer |= (OC_Config->OCNPolarity << 8U);
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC3NE;
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
  {
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS3;
    tmpcr2 &= ~TIM_CR2_OIS3N;
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 4U);
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR3 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

TIM_OC4_SetConfig()

static void TIM_OC4_SetConfig ( TIM_TypeDef *  TIMx, TIM_OC_InitTypeDef *  OC_Config  )

static

Timer Output Compare 4 configuration.

Parameters

TIMx	to select the TIM peripheral
OC_Config	The ouput configuration structure

Return values

None

Definition at line 6224 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC4M;
  tmpccmrx &= ~TIM_CCMR2_CC4S;

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC4P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 12U);

  if (IS_TIM_BREAK_INSTANCE(TIMx))
  {
    /* Check parameters */
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS4;

    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 6U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR4 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

TIM_OC5_SetConfig()

static void TIM_OC5_SetConfig ( TIM_TypeDef *  TIMx, TIM_OC_InitTypeDef *  OC_Config  )

static

Timer Output Compare 5 configuration.

Parameters

TIMx	to select the TIM peripheral
OC_Config	The ouput configuration structure

Return values

None

Definition at line 6284 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the output: Reset the CCxE Bit */
  TIMx->CCER &= ~TIM_CCER_CC5E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR3;

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~(TIM_CCMR3_OC5M);
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC5P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 16U);

  if (IS_TIM_BREAK_INSTANCE(TIMx))
  {
    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS5;
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 8U);
  }
  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR3 */
  TIMx->CCMR3 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR5 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

TIM_OC6_SetConfig()

static void TIM_OC6_SetConfig ( TIM_TypeDef *  TIMx, TIM_OC_InitTypeDef *  OC_Config  )

static

Timer Output Compare 6 configuration.

Parameters

TIMx	to select the TIM peripheral
OC_Config	The ouput configuration structure

Return values

None

Definition at line 6337 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the output: Reset the CCxE Bit */
  TIMx->CCER &= ~TIM_CCER_CC6E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR3;

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~(TIM_CCMR3_OC6M);
  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);

  /* Reset the Output Polarity level */
  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 20U);

  if (IS_TIM_BREAK_INSTANCE(TIMx))
  {
    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS6;
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 10U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR3 */
  TIMx->CCMR3 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR6 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

TIM_ResetCallback()

void TIM_ResetCallback

(

TIM_HandleTypeDef *

htim

)

Reset interrupt callbacks to the legacy weak callbacks.

Parameters

htim	pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.

Return values

None

Definition at line 6872 of file stm32l4xx_hal_tim.c.

{
  /* Reset the TIM callback to the legacy weak callbacks */
  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
}

TIM_SlaveTimer_SetConfig()

static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig ( TIM_HandleTypeDef *  htim, TIM_SlaveConfigTypeDef *  sSlaveConfig  )

static

Slave Timer configuration function.

Parameters

htim	TIM handle
sSlaveConfig	Slave timer configuration

Return values

None

Definition at line 6391 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpsmcr;
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;

  /* Reset the Trigger Selection Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
  /* Set the Input Trigger source */
  tmpsmcr |= sSlaveConfig->InputTrigger;

  /* Reset the slave mode Bits */
  tmpsmcr &= ~TIM_SMCR_SMS;
  /* Set the slave mode */
  tmpsmcr |= sSlaveConfig->SlaveMode;

  /* Write to TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;

  /* Configure the trigger prescaler, filter, and polarity */
  switch (sSlaveConfig->InputTrigger)
  {
    case TIM_TS_ETRF:
    {
      /* Check the parameters */
      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
      /* Configure the ETR Trigger source */
      TIM_ETR_SetConfig(htim->Instance,
                        sSlaveConfig->TriggerPrescaler,
                        sSlaveConfig->TriggerPolarity,
                        sSlaveConfig->TriggerFilter);
      break;
    }

    case TIM_TS_TI1F_ED:
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
      {
        return HAL_ERROR;
      }

      /* Disable the Channel 1: Reset the CC1E Bit */
      tmpccer = htim->Instance->CCER;
      htim->Instance->CCER &= ~TIM_CCER_CC1E;
      tmpccmr1 = htim->Instance->CCMR1;

      /* Set the filter */
      tmpccmr1 &= ~TIM_CCMR1_IC1F;
      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);

      /* Write to TIMx CCMR1 and CCER registers */
      htim->Instance->CCMR1 = tmpccmr1;
      htim->Instance->CCER = tmpccer;
      break;
    }

    case TIM_TS_TI1FP1:
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

      /* Configure TI1 Filter and Polarity */
      TIM_TI1_ConfigInputStage(htim->Instance,
                               sSlaveConfig->TriggerPolarity,
                               sSlaveConfig->TriggerFilter);
      break;
    }

    case TIM_TS_TI2FP2:
    {
      /* Check the parameters */
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

      /* Configure TI2 Filter and Polarity */
      TIM_TI2_ConfigInputStage(htim->Instance,
                               sSlaveConfig->TriggerPolarity,
                               sSlaveConfig->TriggerFilter);
      break;
    }

    case TIM_TS_ITR0:
    case TIM_TS_ITR1:
    case TIM_TS_ITR2:
    case TIM_TS_ITR3:
    {
      /* Check the parameter */
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
      break;
    }

    default:
      break;
  }
  return HAL_OK;
}

TIM_TI1_ConfigInputStage()

static void TIM_TI1_ConfigInputStage ( TIM_TypeDef *  TIMx, uint32_t  TIM_ICPolarity, uint32_t  TIM_ICFilter  )

static

Configure the Polarity and Filter for TI1.

Parameters

TIMx	to select the TIM peripheral.
TIM_ICPolarity	The Input Polarity. This parameter can be one of the following values: TIM_ICPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter	Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.

Return values

None

Definition at line 6569 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
  TIMx->CCER &= ~TIM_CCER_CC1E;
  tmpccmr1 = TIMx->CCMR1;

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
  tmpccmr1 |= (TIM_ICFilter << 4U);

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  tmpccer |= TIM_ICPolarity;

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
  TIMx->CCER = tmpccer;
}

TIM_TI1_SetConfig()

void TIM_TI1_SetConfig	(	TIM_TypeDef *	TIMx,
		uint32_t	TIM_ICPolarity,
		uint32_t	TIM_ICSelection,
		uint32_t	TIM_ICFilter
	)

Configure the TI1 as Input.

Parameters

TIMx	to select the TIM peripheral.
TIM_ICPolarity	The Input Polarity. This parameter can be one of the following values: TIM_ICPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection	specifies the input to be used. This parameter can be one of the following values: TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter	Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.

Return values

None

Note

TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 6522 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;
  tmpccmr1 = TIMx->CCMR1;
  tmpccer = TIMx->CCER;

  /* Select the Input */
  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
  {
    tmpccmr1 &= ~TIM_CCMR1_CC1S;
    tmpccmr1 |= TIM_ICSelection;
  }
  else
  {
    tmpccmr1 |= TIM_CCMR1_CC1S_0;
  }

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
  TIMx->CCER = tmpccer;
}

TIM_TI2_ConfigInputStage()

static void TIM_TI2_ConfigInputStage ( TIM_TypeDef *  TIMx, uint32_t  TIM_ICPolarity, uint32_t  TIM_ICFilter  )

static

Configure the Polarity and Filter for TI2.

Parameters

TIMx	to select the TIM peripheral.
TIM_ICPolarity	The Input Polarity. This parameter can be one of the following values: TIM_ICPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE
TIM_ICFilter	Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.

Return values

None

Definition at line 6652 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
  tmpccmr1 = TIMx->CCMR1;
  tmpccer = TIMx->CCER;

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
  tmpccmr1 |= (TIM_ICFilter << 12U);

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  tmpccer |= (TIM_ICPolarity << 4U);

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
  TIMx->CCER = tmpccer;
}

TIM_TI2_SetConfig()

static void TIM_TI2_SetConfig ( TIM_TypeDef *  TIMx, uint32_t  TIM_ICPolarity, uint32_t  TIM_ICSelection, uint32_t  TIM_ICFilter  )

static

Configure the TI2 as Input.

Parameters

TIMx	to select the TIM peripheral
TIM_ICPolarity	The Input Polarity. This parameter can be one of the following values: TIM_ICPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection	specifies the input to be used. This parameter can be one of the following values: TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter	Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.

Return values

None

Note

TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 6612 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
  tmpccmr1 = TIMx->CCMR1;
  tmpccer = TIMx->CCER;

  /* Select the Input */
  tmpccmr1 &= ~TIM_CCMR1_CC2S;
  tmpccmr1 |= (TIM_ICSelection << 8U);

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
  TIMx->CCER = tmpccer;
}

TIM_TI3_SetConfig()

static void TIM_TI3_SetConfig ( TIM_TypeDef *  TIMx, uint32_t  TIM_ICPolarity, uint32_t  TIM_ICSelection, uint32_t  TIM_ICFilter  )

static

Configure the TI3 as Input.

Parameters

TIMx	to select the TIM peripheral
TIM_ICPolarity	The Input Polarity. This parameter can be one of the following values: TIM_ICPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection	specifies the input to be used. This parameter can be one of the following values: TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter	Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.

Return values

None

Note

TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 6695 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 3: Reset the CC3E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;
  tmpccmr2 = TIMx->CCMR2;
  tmpccer = TIMx->CCER;

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC3S;
  tmpccmr2 |= TIM_ICSelection;

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC3F;
  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);

  /* Select the Polarity and set the CC3E Bit */
  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
  TIMx->CCER = tmpccer;
}

TIM_TI4_SetConfig()

static void TIM_TI4_SetConfig ( TIM_TypeDef *  TIMx, uint32_t  TIM_ICPolarity, uint32_t  TIM_ICSelection, uint32_t  TIM_ICFilter  )

static

Configure the TI4 as Input.

Parameters

TIMx	to select the TIM peripheral
TIM_ICPolarity	The Input Polarity. This parameter can be one of the following values: TIM_ICPOLARITY_RISING TIM_ICPOLARITY_FALLING TIM_ICPOLARITY_BOTHEDGE
TIM_ICSelection	specifies the input to be used. This parameter can be one of the following values: TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter	Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.

Note

TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Return values

None

Definition at line 6743 of file stm32l4xx_hal_tim.c.

{
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;
  tmpccmr2 = TIMx->CCMR2;
  tmpccer = TIMx->CCER;

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC4S;
  tmpccmr2 |= (TIM_ICSelection << 8U);

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC4F;
  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);

  /* Select the Polarity and set the CC4E Bit */
  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
  TIMx->CCER = tmpccer ;
}