STM32L4xx_HAL_Driver  1.14.0
stm32l4xx_hal_tim.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_HAL_TIM_H
22 #define STM32L4xx_HAL_TIM_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Prescaler;
52  uint32_t CounterMode;
55  uint32_t Period;
59  uint32_t ClockDivision;
62  uint32_t RepetitionCounter;
71  uint32_t AutoReloadPreload;
73 } TIM_Base_InitTypeDef;
74 
78 typedef struct
79 {
80  uint32_t OCMode;
83  uint32_t Pulse;
86  uint32_t OCPolarity;
89  uint32_t OCNPolarity;
93  uint32_t OCFastMode;
98  uint32_t OCIdleState;
102  uint32_t OCNIdleState;
105 } TIM_OC_InitTypeDef;
106 
110 typedef struct
111 {
112  uint32_t OCMode;
115  uint32_t Pulse;
118  uint32_t OCPolarity;
121  uint32_t OCNPolarity;
125  uint32_t OCIdleState;
129  uint32_t OCNIdleState;
133  uint32_t ICPolarity;
136  uint32_t ICSelection;
139  uint32_t ICFilter;
141 } TIM_OnePulse_InitTypeDef;
142 
146 typedef struct
147 {
148  uint32_t ICPolarity;
151  uint32_t ICSelection;
154  uint32_t ICPrescaler;
157  uint32_t ICFilter;
159 } TIM_IC_InitTypeDef;
160 
164 typedef struct
165 {
166  uint32_t EncoderMode;
169  uint32_t IC1Polarity;
172  uint32_t IC1Selection;
175  uint32_t IC1Prescaler;
178  uint32_t IC1Filter;
181  uint32_t IC2Polarity;
184  uint32_t IC2Selection;
187  uint32_t IC2Prescaler;
190  uint32_t IC2Filter;
192 } TIM_Encoder_InitTypeDef;
193 
197 typedef struct
198 {
199  uint32_t ClockSource;
201  uint32_t ClockPolarity;
203  uint32_t ClockPrescaler;
205  uint32_t ClockFilter;
207 } TIM_ClockConfigTypeDef;
208 
212 typedef struct
213 {
214  uint32_t ClearInputState;
216  uint32_t ClearInputSource;
218  uint32_t ClearInputPolarity;
220  uint32_t ClearInputPrescaler;
222  uint32_t ClearInputFilter;
224 } TIM_ClearInputConfigTypeDef;
225 
231 typedef struct
232 {
233  uint32_t MasterOutputTrigger;
235  uint32_t MasterOutputTrigger2;
237  uint32_t MasterSlaveMode;
239 } TIM_MasterConfigTypeDef;
240 
244 typedef struct
245 {
246  uint32_t SlaveMode;
248  uint32_t InputTrigger;
250  uint32_t TriggerPolarity;
252  uint32_t TriggerPrescaler;
254  uint32_t TriggerFilter;
257 } TIM_SlaveConfigTypeDef;
258 
264 typedef struct
265 {
266  uint32_t OffStateRunMode;
268  uint32_t OffStateIDLEMode;
270  uint32_t LockLevel;
272  uint32_t DeadTime;
274  uint32_t BreakState;
276  uint32_t BreakPolarity;
278  uint32_t BreakFilter;
280  uint32_t Break2State;
282  uint32_t Break2Polarity;
284  uint32_t Break2Filter;
286  uint32_t AutomaticOutput;
288 } TIM_BreakDeadTimeConfigTypeDef;
289 
293 typedef enum
294 {
295  HAL_TIM_STATE_RESET = 0x00U,
296  HAL_TIM_STATE_READY = 0x01U,
297  HAL_TIM_STATE_BUSY = 0x02U,
298  HAL_TIM_STATE_TIMEOUT = 0x03U,
299  HAL_TIM_STATE_ERROR = 0x04U
300 } HAL_TIM_StateTypeDef;
301 
305 typedef enum
306 {
307  HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
308  HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
309  HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
310  HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
311  HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U,
312  HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U,
313  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
314 } HAL_TIM_ActiveChannel;
315 
319 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
320 typedef struct __TIM_HandleTypeDef
321 #else
322 typedef struct
323 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
324 {
325  TIM_TypeDef *Instance;
326  TIM_Base_InitTypeDef Init;
327  HAL_TIM_ActiveChannel Channel;
328  DMA_HandleTypeDef *hdma[7];
330  HAL_LockTypeDef Lock;
331  __IO HAL_TIM_StateTypeDef State;
333 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
334  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
335  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
336  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
337  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
338  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
339  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
340  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
341  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
342  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
343  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
344  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
345  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
346  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
347  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
348  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);
349  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
350  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);
351  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
352  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);
353  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
354  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);
355  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);
356  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
357  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);
358  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);
359  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
360  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);
361  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);
362 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
363 } TIM_HandleTypeDef;
364 
365 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
366 
369 typedef enum
370 {
371  HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U
372  ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U
373  ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U
374  ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U
375  ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U
376  ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U
377  ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U
378  ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U
379  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U
380  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U
381  ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU
382  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU
383  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU
384  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU
385  ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU
386  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU
387  ,HAL_TIM_TRIGGER_CB_ID = 0x10U
388  ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U
390  ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U
391  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U
392  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U
393  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U
394  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U
395  ,HAL_TIM_ERROR_CB_ID = 0x17U
396  ,HAL_TIM_COMMUTATION_CB_ID = 0x18U
397  ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U
398  ,HAL_TIM_BREAK_CB_ID = 0x1AU
399  ,HAL_TIM_BREAK2_CB_ID = 0x1BU
400 } HAL_TIM_CallbackIDTypeDef;
401 
405 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);
407 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
408 
412 /* End of exported types -----------------------------------------------------*/
413 
414 /* Exported constants --------------------------------------------------------*/
422 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
423 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
424 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U
432 #define TIM_DMABASE_CR1 0x00000000U
433 #define TIM_DMABASE_CR2 0x00000001U
434 #define TIM_DMABASE_SMCR 0x00000002U
435 #define TIM_DMABASE_DIER 0x00000003U
436 #define TIM_DMABASE_SR 0x00000004U
437 #define TIM_DMABASE_EGR 0x00000005U
438 #define TIM_DMABASE_CCMR1 0x00000006U
439 #define TIM_DMABASE_CCMR2 0x00000007U
440 #define TIM_DMABASE_CCER 0x00000008U
441 #define TIM_DMABASE_CNT 0x00000009U
442 #define TIM_DMABASE_PSC 0x0000000AU
443 #define TIM_DMABASE_ARR 0x0000000BU
444 #define TIM_DMABASE_RCR 0x0000000CU
445 #define TIM_DMABASE_CCR1 0x0000000DU
446 #define TIM_DMABASE_CCR2 0x0000000EU
447 #define TIM_DMABASE_CCR3 0x0000000FU
448 #define TIM_DMABASE_CCR4 0x00000010U
449 #define TIM_DMABASE_BDTR 0x00000011U
450 #define TIM_DMABASE_DCR 0x00000012U
451 #define TIM_DMABASE_DMAR 0x00000013U
452 #define TIM_DMABASE_OR1 0x00000014U
453 #define TIM_DMABASE_CCMR3 0x00000015U
454 #define TIM_DMABASE_CCR5 0x00000016U
455 #define TIM_DMABASE_CCR6 0x00000017U
456 #define TIM_DMABASE_OR2 0x00000018U
457 #define TIM_DMABASE_OR3 0x00000019U
458 
465 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
466 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
467 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
468 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
469 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
470 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
471 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
472 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
473 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
481 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
482 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
483 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
491 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
492 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U
500 #define TIM_ETRPRESCALER_DIV1 0x00000000U
501 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
502 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
503 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
511 #define TIM_COUNTERMODE_UP 0x00000000U
512 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
513 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
514 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
515 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
523 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
524 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
525 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
533 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
534 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
542 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
543 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
552 #define TIM_OCFAST_DISABLE 0x00000000U
553 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
561 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
562 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
570 #define TIM_OCPOLARITY_HIGH 0x00000000U
571 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P
579 #define TIM_OCNPOLARITY_HIGH 0x00000000U
580 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
588 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1
589 #define TIM_OCIDLESTATE_RESET 0x00000000U
597 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
598 #define TIM_OCNIDLESTATE_RESET 0x00000000U
606 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
607 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
608 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
616 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
618 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
620 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
628 #define TIM_ICPSC_DIV1 0x00000000U
629 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
630 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
631 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
639 #define TIM_OPMODE_SINGLE TIM_CR1_OPM
640 #define TIM_OPMODE_REPETITIVE 0x00000000U
648 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
649 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
650 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
658 #define TIM_IT_UPDATE TIM_DIER_UIE
659 #define TIM_IT_CC1 TIM_DIER_CC1IE
660 #define TIM_IT_CC2 TIM_DIER_CC2IE
661 #define TIM_IT_CC3 TIM_DIER_CC3IE
662 #define TIM_IT_CC4 TIM_DIER_CC4IE
663 #define TIM_IT_COM TIM_DIER_COMIE
664 #define TIM_IT_TRIGGER TIM_DIER_TIE
665 #define TIM_IT_BREAK TIM_DIER_BIE
673 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
674 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
682 #define TIM_DMA_UPDATE TIM_DIER_UDE
683 #define TIM_DMA_CC1 TIM_DIER_CC1DE
684 #define TIM_DMA_CC2 TIM_DIER_CC2DE
685 #define TIM_DMA_CC3 TIM_DIER_CC3DE
686 #define TIM_DMA_CC4 TIM_DIER_CC4DE
687 #define TIM_DMA_COM TIM_DIER_COMDE
688 #define TIM_DMA_TRIGGER TIM_DIER_TDE
696 #define TIM_FLAG_UPDATE TIM_SR_UIF
697 #define TIM_FLAG_CC1 TIM_SR_CC1IF
698 #define TIM_FLAG_CC2 TIM_SR_CC2IF
699 #define TIM_FLAG_CC3 TIM_SR_CC3IF
700 #define TIM_FLAG_CC4 TIM_SR_CC4IF
701 #define TIM_FLAG_CC5 TIM_SR_CC5IF
702 #define TIM_FLAG_CC6 TIM_SR_CC6IF
703 #define TIM_FLAG_COM TIM_SR_COMIF
704 #define TIM_FLAG_TRIGGER TIM_SR_TIF
705 #define TIM_FLAG_BREAK TIM_SR_BIF
706 #define TIM_FLAG_BREAK2 TIM_SR_B2IF
707 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
708 #define TIM_FLAG_CC1OF TIM_SR_CC1OF
709 #define TIM_FLAG_CC2OF TIM_SR_CC2OF
710 #define TIM_FLAG_CC3OF TIM_SR_CC3OF
711 #define TIM_FLAG_CC4OF TIM_SR_CC4OF
719 #define TIM_CHANNEL_1 0x00000000U
720 #define TIM_CHANNEL_2 0x00000004U
721 #define TIM_CHANNEL_3 0x00000008U
722 #define TIM_CHANNEL_4 0x0000000CU
723 #define TIM_CHANNEL_5 0x00000010U
724 #define TIM_CHANNEL_6 0x00000014U
725 #define TIM_CHANNEL_ALL 0x0000003CU
733 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
734 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
735 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
736 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
737 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
738 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
739 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
740 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
741 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
742 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
750 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
751 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
752 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
753 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
754 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
762 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
763 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
764 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
765 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
773 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
774 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
782 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
783 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
784 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
785 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
793 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR
794 #define TIM_OSSR_DISABLE 0x00000000U
802 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI
803 #define TIM_OSSI_DISABLE 0x00000000U
810 #define TIM_LOCKLEVEL_OFF 0x00000000U
811 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
812 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
813 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
821 #define TIM_BREAK_ENABLE TIM_BDTR_BKE
822 #define TIM_BREAK_DISABLE 0x00000000U
830 #define TIM_BREAKPOLARITY_LOW 0x00000000U
831 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
839 #define TIM_BREAK2_DISABLE 0x00000000U
840 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E
848 #define TIM_BREAK2POLARITY_LOW 0x00000000U
849 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
857 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
858 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
867 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
868 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
869 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
870 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
871 
878 #define TIM_TRGO_RESET 0x00000000U
879 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0
880 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1
881 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
882 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2
883 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
884 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
885 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
893 #define TIM_TRGO2_RESET 0x00000000U
894 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
895 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
896 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
897 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
898 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
899 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)
900 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
901 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
902 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)
903 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)
904 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
905 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)
906 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)
907 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)
908 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)
916 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
917 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
925 #define TIM_SLAVEMODE_DISABLE 0x00000000U
926 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
927 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
928 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
929 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
930 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
938 #define TIM_OCMODE_TIMING 0x00000000U
939 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
940 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
941 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
942 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
943 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
944 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
945 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
946 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
947 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
948 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
949 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
950 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
951 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M
959 #define TIM_TS_ITR0 0x00000000U
960 #define TIM_TS_ITR1 TIM_SMCR_TS_0
961 #define TIM_TS_ITR2 TIM_SMCR_TS_1
962 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
963 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2
964 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
965 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
966 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
967 #define TIM_TS_NONE 0x0000FFFFU
975 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
976 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
977 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
978 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
979 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
987 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
988 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
989 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
990 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
998 #define TIM_TI1SELECTION_CH1 0x00000000U
999 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
1007 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
1008 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
1009 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
1010 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
1011 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
1012 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
1013 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
1014 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
1015 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
1016 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
1017 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
1018 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
1019 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
1020 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
1021 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
1022 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
1023 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
1024 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
1032 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
1033 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
1034 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
1035 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
1036 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
1037 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
1038 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
1046 #define TIM_CCx_ENABLE 0x00000001U
1047 #define TIM_CCx_DISABLE 0x00000000U
1048 #define TIM_CCxN_ENABLE 0x00000004U
1049 #define TIM_CCxN_DISABLE 0x00000000U
1057 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
1058 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
1059 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL
1060 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
1068 /* End of exported constants -------------------------------------------------*/
1069 
1070 /* Exported macros -----------------------------------------------------------*/
1079 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1080 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1081  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1082  (__HANDLE__)->Base_MspInitCallback = NULL; \
1083  (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1084  (__HANDLE__)->IC_MspInitCallback = NULL; \
1085  (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1086  (__HANDLE__)->OC_MspInitCallback = NULL; \
1087  (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1088  (__HANDLE__)->PWM_MspInitCallback = NULL; \
1089  (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1090  (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1091  (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1092  (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1093  (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1094  (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1095  (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1096  } while(0)
1097 #else
1098 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1099 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1100 
1106 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1107 
1113 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1114 
1120 #define __HAL_TIM_DISABLE(__HANDLE__) \
1121  do { \
1122  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1123  { \
1124  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1125  { \
1126  (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1127  } \
1128  } \
1129  } while(0)
1130 
1137 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1138  do { \
1139  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1140  { \
1141  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1142  { \
1143  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1144  } \
1145  } \
1146  } while(0)
1147 
1154 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1155 
1170 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1171 
1186 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1187 
1201 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1202 
1216 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1217 
1240 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1241 
1264 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1265 
1281 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1282  == (__INTERRUPT__)) ? SET : RESET)
1283 
1298 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1299 
1307 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1308 
1315 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1316 
1323 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1324 
1330 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1331 
1338 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1339  do{ \
1340  (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1341  (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1342  } while(0)
1343 
1349 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1350 
1361 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1362  do{ \
1363  (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1364  (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1365  (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1366  } while(0)
1367 
1376 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1377 
1395 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1396  do{ \
1397  TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1398  TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1399  } while(0)
1400 
1416 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1417  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1418  ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1419  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1420  (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1421 
1436 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1437  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1438  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1439  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1440  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1441  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1442  ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1443 
1457 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1458  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1459  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1460  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1461  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1462  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1463  ((__HANDLE__)->Instance->CCR6))
1464 
1478 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1479  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1480  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1481  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1482  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1483  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1484  ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1485 
1499 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1500  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
1501  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
1502  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
1503  ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
1504  ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
1505  ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
1506 
1515 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1516 
1528 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1529 
1545 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1546  do{ \
1547  TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1548  TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1549  }while(0)
1550 
1554 /* End of exported macros ----------------------------------------------------*/
1555 
1556 /* Private constants ---------------------------------------------------------*/
1560 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1561  channels have been disabled */
1562 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1563 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1564 
1567 /* End of private constants --------------------------------------------------*/
1568 
1569 /* Private macros ------------------------------------------------------------*/
1573 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
1574  ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
1575  ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1576 
1577 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1578  ((__BASE__) == TIM_DMABASE_CR2) || \
1579  ((__BASE__) == TIM_DMABASE_SMCR) || \
1580  ((__BASE__) == TIM_DMABASE_DIER) || \
1581  ((__BASE__) == TIM_DMABASE_SR) || \
1582  ((__BASE__) == TIM_DMABASE_EGR) || \
1583  ((__BASE__) == TIM_DMABASE_CCMR1) || \
1584  ((__BASE__) == TIM_DMABASE_CCMR2) || \
1585  ((__BASE__) == TIM_DMABASE_CCER) || \
1586  ((__BASE__) == TIM_DMABASE_CNT) || \
1587  ((__BASE__) == TIM_DMABASE_PSC) || \
1588  ((__BASE__) == TIM_DMABASE_ARR) || \
1589  ((__BASE__) == TIM_DMABASE_RCR) || \
1590  ((__BASE__) == TIM_DMABASE_CCR1) || \
1591  ((__BASE__) == TIM_DMABASE_CCR2) || \
1592  ((__BASE__) == TIM_DMABASE_CCR3) || \
1593  ((__BASE__) == TIM_DMABASE_CCR4) || \
1594  ((__BASE__) == TIM_DMABASE_BDTR) || \
1595  ((__BASE__) == TIM_DMABASE_OR1) || \
1596  ((__BASE__) == TIM_DMABASE_CCMR3) || \
1597  ((__BASE__) == TIM_DMABASE_CCR5) || \
1598  ((__BASE__) == TIM_DMABASE_CCR6) || \
1599  ((__BASE__) == TIM_DMABASE_OR2) || \
1600  ((__BASE__) == TIM_DMABASE_OR3))
1601 
1602 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1603 
1604 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1605  ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1606  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1607  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1608  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1609 
1610 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1611  ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1612  ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1613 
1614 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1615  ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1616 
1617 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1618  ((__STATE__) == TIM_OCFAST_ENABLE))
1619 
1620 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1621  ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1622 
1623 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1624  ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1625 
1626 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1627  ((__STATE__) == TIM_OCIDLESTATE_RESET))
1628 
1629 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1630  ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1631 
1632 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1633  ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1634  ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1635 
1636 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1637  ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1638  ((__SELECTION__) == TIM_ICSELECTION_TRC))
1639 
1640 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1641  ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1642  ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1643  ((__PRESCALER__) == TIM_ICPSC_DIV8))
1644 
1645 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1646  ((__MODE__) == TIM_OPMODE_REPETITIVE))
1647 
1648 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1649  ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1650  ((__MODE__) == TIM_ENCODERMODE_TI12))
1651 
1652 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1653 
1654 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1655  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1656  ((__CHANNEL__) == TIM_CHANNEL_3) || \
1657  ((__CHANNEL__) == TIM_CHANNEL_4) || \
1658  ((__CHANNEL__) == TIM_CHANNEL_5) || \
1659  ((__CHANNEL__) == TIM_CHANNEL_6) || \
1660  ((__CHANNEL__) == TIM_CHANNEL_ALL))
1661 
1662 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1663  ((__CHANNEL__) == TIM_CHANNEL_2))
1664 
1665 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1666  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1667  ((__CHANNEL__) == TIM_CHANNEL_3))
1668 
1669 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1670  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1671  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1672  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1673  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1674  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1675  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1676  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1677  ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1678  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1679 
1680 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1681  ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1682  ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1683  ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1684  ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1685 
1686 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1687  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1688  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1689  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1690 
1691 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1692 
1693 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1694  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1695 
1696 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1697  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1698  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1699  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1700 
1701 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1702 
1703 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1704  ((__STATE__) == TIM_OSSR_DISABLE))
1705 
1706 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1707  ((__STATE__) == TIM_OSSI_DISABLE))
1708 
1709 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1710  ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1711  ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1712  ((__LEVEL__) == TIM_LOCKLEVEL_3))
1713 
1714 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1715 
1716 
1717 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1718  ((__STATE__) == TIM_BREAK_DISABLE))
1719 
1720 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1721  ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1722 
1723 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1724  ((__STATE__) == TIM_BREAK2_DISABLE))
1725 
1726 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1727  ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1728 
1729 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1730  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1731 
1732 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1733 
1734 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1735  ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1736  ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1737  ((__SOURCE__) == TIM_TRGO_OC1) || \
1738  ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1739  ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1740  ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1741  ((__SOURCE__) == TIM_TRGO_OC4REF))
1742 
1743 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1744  ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1745  ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1746  ((__SOURCE__) == TIM_TRGO2_OC1) || \
1747  ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1748  ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1749  ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1750  ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1751  ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1752  ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1753  ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1754  ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1755  ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1756  ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1757  ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1758  ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1759  ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1760 
1761 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1762  ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1763 
1764 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1765  ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1766  ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1767  ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1768  ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1769  ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1770 
1771 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1772  ((__MODE__) == TIM_OCMODE_PWM2) || \
1773  ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1774  ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1775  ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1776  ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1777 
1778 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1779  ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1780  ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1781  ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1782  ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1783  ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1784  ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1785  ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
1786 
1787 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1788  ((__SELECTION__) == TIM_TS_ITR1) || \
1789  ((__SELECTION__) == TIM_TS_ITR2) || \
1790  ((__SELECTION__) == TIM_TS_ITR3) || \
1791  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1792  ((__SELECTION__) == TIM_TS_TI1FP1) || \
1793  ((__SELECTION__) == TIM_TS_TI2FP2) || \
1794  ((__SELECTION__) == TIM_TS_ETRF))
1795 
1796 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1797  ((__SELECTION__) == TIM_TS_ITR1) || \
1798  ((__SELECTION__) == TIM_TS_ITR2) || \
1799  ((__SELECTION__) == TIM_TS_ITR3) || \
1800  ((__SELECTION__) == TIM_TS_NONE))
1801 
1802 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1803  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1804  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1805  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1806  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1807 
1808 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1809  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1810  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1811  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1812 
1813 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1814 
1815 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1816  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1817 
1818 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1819  ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1820  ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1821  ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1822  ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1823  ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1824  ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1825  ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1826  ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1827  ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1828  ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1829  ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1830  ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1831  ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1832  ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1833  ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1834  ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1835  ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1836 
1837 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1838 
1839 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
1840 
1841 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
1842  ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
1843  ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \
1844  ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
1845 
1846 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
1847  ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1848 
1849 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1850  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1851  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1852  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1853  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1854 
1855 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1856  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1857  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1858  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1859  ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1860 
1861 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1862  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1863  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1864  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1865  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1866 
1867 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1868  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1869  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1870  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1871  ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
1872 
1876 /* End of private macros -----------------------------------------------------*/
1877 
1878 /* Include TIM HAL Extended module */
1879 #include "stm32l4xx_hal_tim_ex.h"
1880 
1881 /* Exported functions --------------------------------------------------------*/
1890 /* Time Base functions ********************************************************/
1891 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1892 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1893 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1894 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1895 /* Blocking mode: Polling */
1896 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1897 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1898 /* Non-Blocking mode: Interrupt */
1899 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1900 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1901 /* Non-Blocking mode: DMA */
1902 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1903 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1912 /* Timer Output Compare functions *********************************************/
1913 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1914 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1915 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1916 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1917 /* Blocking mode: Polling */
1918 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1919 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1920 /* Non-Blocking mode: Interrupt */
1921 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1922 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1923 /* Non-Blocking mode: DMA */
1924 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1925 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1934 /* Timer PWM functions ********************************************************/
1935 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1936 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1937 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1938 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1939 /* Blocking mode: Polling */
1940 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1941 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1942 /* Non-Blocking mode: Interrupt */
1943 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1944 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1945 /* Non-Blocking mode: DMA */
1946 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1947 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1956 /* Timer Input Capture functions **********************************************/
1957 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1958 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1959 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1960 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1961 /* Blocking mode: Polling */
1962 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1963 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1964 /* Non-Blocking mode: Interrupt */
1965 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1966 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1967 /* Non-Blocking mode: DMA */
1968 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1969 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1978 /* Timer One Pulse functions **************************************************/
1979 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1980 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1981 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1982 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1983 /* Blocking mode: Polling */
1984 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1985 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1986 /* Non-Blocking mode: Interrupt */
1987 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1988 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1997 /* Timer Encoder functions ****************************************************/
1998 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
1999 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2000 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2001 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2002 /* Blocking mode: Polling */
2003 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2004 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2005 /* Non-Blocking mode: Interrupt */
2006 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2007 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2008 /* Non-Blocking mode: DMA */
2009 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2010  uint32_t *pData2, uint16_t Length);
2011 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2020 /* Interrupt Handler functions ***********************************************/
2021 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2030 /* Control functions *********************************************************/
2031 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2032 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2033 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2034 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2035  uint32_t OutputChannel, uint32_t InputChannel);
2036 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
2037  uint32_t Channel);
2038 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2039 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2040 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2041 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2042 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2043  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2044 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2045 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2046  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2047 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2048 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2049 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2058 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2059 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2060 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2061 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2062 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2063 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2064 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2065 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2066 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2067 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2068 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2069 
2070 /* Callbacks Register/UnRegister functions ***********************************/
2071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2072 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2073  pTIM_CallbackTypeDef pCallback);
2074 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2075 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2076 
2085 /* Peripheral State functions ************************************************/
2086 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2087 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2088 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2089 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2090 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2091 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2099 /* End of exported functions -------------------------------------------------*/
2100 
2101 /* Private functions----------------------------------------------------------*/
2105 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2106 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2107 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2108 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2109  uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2110 
2111 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
2112 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2113 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2114 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2115 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2116 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2117 
2118 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2119 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2120 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2121 
2125 /* End of private functions --------------------------------------------------*/
2126 
2135 #ifdef __cplusplus
2136 }
2137 #endif
2138 
2139 #endif /* STM32L4xx_HAL_TIM_H */
2140 
2141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
TIM_OC_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32l4xx_hal_tim.h:102
HAL_TIM_Base_Start_IT
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:439
endif::State
__IO HAL_TIM_StateTypeDef State
Definition: stm32l4xx_hal_tim.h:331
HAL_TIM_OnePulse_Init
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDe...
Definition: stm32l4xx_hal_tim.c:2294
HAL_TIM_Encoder_Init
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and initialize the associated handle.
Definition: stm32l4xx_hal_tim.c:2607
TIM_BreakDeadTimeConfigTypeDef::Break2Filter
uint32_t Break2Filter
Definition: stm32l4xx_hal_tim.h:284
HAL_TIM_Base_Stop_IT
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:465
TIM_SlaveConfigTypeDef::InputTrigger
uint32_t InputTrigger
Definition: stm32l4xx_hal_tim.h:248
TIM_BreakDeadTimeConfigTypeDef::BreakPolarity
uint32_t BreakPolarity
Definition: stm32l4xx_hal_tim.h:276
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
PWM Pulse finished half complete callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5052
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition: stm32l4xx_hal_tim.h:305
TIM_Base_InitTypeDef::AutoReloadPreload
uint32_t AutoReloadPreload
Definition: stm32l4xx_hal_tim.h:71
TIM_OnePulse_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32l4xx_hal_tim.h:136
HAL_TIM_ACTIVE_CHANNEL_6
Definition: stm32l4xx_hal_tim.h:312
TIM_Encoder_InitTypeDef::IC1Polarity
uint32_t IC1Polarity
Definition: stm32l4xx_hal_tim.h:169
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition: stm32l4xx_hal_tim.h:197
HAL_TIM_PWM_DeInit
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
Definition: stm32l4xx_hal_tim.c:1229
TIM_OC_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32l4xx_hal_tim.h:83
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:47
HAL_TIM_IC_Start_DMA
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
Definition: stm32l4xx_hal_tim.c:2064
HAL_TIM_OnePulse_Stop
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
Definition: stm32l4xx_hal_tim.c:2459
TIM_Base_InitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Definition: stm32l4xx_hal_tim.h:62
HAL_TIM_CallbackIDTypeDef
HAL_TIM_CallbackIDTypeDef
HAL TIM Callback ID enumeration definition.
Definition: stm32l4xx_hal_tim.h:369
HAL_TIM_Base_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
Definition: stm32l4xx_hal_tim.c:545
TIM_IC_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32l4xx_hal_tim.h:148
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32l4xx_hal_dma.h:113
HAL_TIM_IC_CAPTURE_HALF_CB_ID
Definition: stm32l4xx_hal_tim.h:391
TIM_Base_InitTypeDef::ClockDivision
uint32_t ClockDivision
Definition: stm32l4xx_hal_tim.h:59
HAL_TIM_ENCODER_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:381
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:164
HAL_TIM_STATE_TIMEOUT
Definition: stm32l4xx_hal_tim.h:298
HAL_TIM_DMABurst_ReadStart
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
Definition: stm32l4xx_hal_tim.c:4168
endif::Instance
TIM_TypeDef * Instance
Definition: stm32l4xx_hal_tim.h:325
TIM_TI1_SetConfig
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
Definition: stm32l4xx_hal_tim.c:6522
HAL_TIM_PWM_PulseFinishedCallback
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5037
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:146
TIM_OnePulse_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32l4xx_hal_tim.h:133
TIM_Base_SetConfig
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
Definition: stm32l4xx_hal_tim.c:5951
TIM_ResetCallback
void TIM_ResetCallback(TIM_HandleTypeDef *htim)
Reset interrupt callbacks to the legacy weak callbacks.
Definition: stm32l4xx_hal_tim.c:6872
HAL_TIM_OnePulse_Stop_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:2537
TIM_Encoder_InitTypeDef::IC2Filter
uint32_t IC2Filter
Definition: stm32l4xx_hal_tim.h:190
HAL_TIM_PWM_MspDeInit
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
Definition: stm32l4xx_hal_tim.c:1280
TIM_ClearInputConfigTypeDef::ClearInputSource
uint32_t ClearInputSource
Definition: stm32l4xx_hal_tim.h:216
HAL_TIM_UnRegisterCallback
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
Unregister a TIM callback TIM callback is redirected to the weak predefined callback.
Definition: stm32l4xx_hal_tim.c:5392
HAL_TIM_OC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
Definition: stm32l4xx_hal_tim.c:1080
HAL_TIM_ReadCapturedValue
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
Definition: stm32l4xx_hal_tim.c:4878
TIM_OC_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32l4xx_hal_tim.h:98
HAL_TIM_IC_MspDeInit
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
Definition: stm32l4xx_hal_tim.c:1858
TIM_SlaveConfigTypeDef::SlaveMode
uint32_t SlaveMode
Definition: stm32l4xx_hal_tim.h:246
TIM_DMADelayPulseCplt
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
Definition: stm32l4xx_hal_tim.c:5714
HAL_TIM_ErrorCallback
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
Timer error callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5097
HAL_TIM_Base_Start
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
Definition: stm32l4xx_hal_tim.c:387
HAL_TIM_OnePulse_Start
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
Definition: stm32l4xx_hal_tim.c:2423
HAL_TIM_IRQHandler
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
Definition: stm32l4xx_hal_tim.c:3178
endif::Channel
HAL_TIM_ActiveChannel Channel
Definition: stm32l4xx_hal_tim.h:327
HAL_TIM_PWM_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:377
stm32l4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_TIM_COMMUTATION_CB_ID
Definition: stm32l4xx_hal_tim.h:396
HAL_TIM_Encoder_Stop
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
Definition: stm32l4xx_hal_tim.c:2827
HAL_TIM_Base_Init
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and...
Definition: stm32l4xx_hal_tim.c:268
HAL_TIM_Encoder_Start_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
Definition: stm32l4xx_hal_tim.c:2873
HAL_TIM_IC_CaptureHalfCpltCallback
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
Input Capture half complete callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5022
HAL_TIM_OC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitT...
Definition: stm32l4xx_hal_tim.c:3408
HAL_TIM_OC_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:376
TIM_SlaveConfigTypeDef::TriggerPrescaler
uint32_t TriggerPrescaler
Definition: stm32l4xx_hal_tim.h:252
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:231
HAL_TIM_Encoder_DeInit
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
Definition: stm32l4xx_hal_tim.c:2712
TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode
uint32_t OffStateIDLEMode
Definition: stm32l4xx_hal_tim.h:268
HAL_TIM_IC_Start_IT
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
Definition: stm32l4xx_hal_tim.c:1937
TIM_DMADelayPulseHalfCplt
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse half complete callback.
Definition: stm32l4xx_hal_tim.c:5755
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:244
TIM_OnePulse_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32l4xx_hal_tim.h:115
HAL_TIM_IC_Init
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTy...
Definition: stm32l4xx_hal_tim.c:1755
TIM_Encoder_InitTypeDef::IC1Prescaler
uint32_t IC1Prescaler
Definition: stm32l4xx_hal_tim.h:175
HAL_TIM_ACTIVE_CHANNEL_4
Definition: stm32l4xx_hal_tim.h:310
HAL_TIM_PWM_MspInit
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
Definition: stm32l4xx_hal_tim.c:1265
TIM_ClockConfigTypeDef::ClockSource
uint32_t ClockSource
Definition: stm32l4xx_hal_tim.h:199
HAL_TIM_PWM_PULSE_FINISHED_CB_ID
Definition: stm32l4xx_hal_tim.h:393
HAL_TIM_STATE_READY
Definition: stm32l4xx_hal_tim.h:296
HAL_TIM_Encoder_GetState
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode handle state.
Definition: stm32l4xx_hal_tim.c:5674
HAL_TIM_OnePulse_MspDeInit
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
Definition: stm32l4xx_hal_tim.c:2404
TIM_SlaveConfigTypeDef::TriggerFilter
uint32_t TriggerFilter
Definition: stm32l4xx_hal_tim.h:254
TIM_ClearInputConfigTypeDef::ClearInputPrescaler
uint32_t ClearInputPrescaler
Definition: stm32l4xx_hal_tim.h:220
HAL_TIM_ACTIVE_CHANNEL_2
Definition: stm32l4xx_hal_tim.h:308
HAL_TIM_ACTIVE_CHANNEL_CLEARED
Definition: stm32l4xx_hal_tim.h:313
HAL_TIM_IC_MspInit
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
Definition: stm32l4xx_hal_tim.c:1843
TIM_Encoder_InitTypeDef::IC2Prescaler
uint32_t IC2Prescaler
Definition: stm32l4xx_hal_tim.h:187
HAL_TIM_IC_Stop_DMA
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
Definition: stm32l4xx_hal_tim.c:2199
TIM_BreakDeadTimeConfigTypeDef::BreakState
uint32_t BreakState
Definition: stm32l4xx_hal_tim.h:274
TIM_Encoder_InitTypeDef::IC2Polarity
uint32_t IC2Polarity
Definition: stm32l4xx_hal_tim.h:181
HAL_TIM_Encoder_MspInit
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
Definition: stm32l4xx_hal_tim.c:2748
HAL_TIM_OC_Start_DMA
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
Definition: stm32l4xx_hal_tim.c:938
HAL_TIM_OC_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:375
HAL_TIM_GenerateEvent
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
Definition: stm32l4xx_hal_tim.c:4411
TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition.
Definition: stm32l4xx_hal_tim.h:212
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:110
HAL_TIM_SlaveConfigSynchro_IT
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
Definition: stm32l4xx_hal_tim.c:4835
TIM_DMAError
void TIM_DMAError(DMA_HandleTypeDef *hdma)
TIM DMA error callback.
Definition: stm32l4xx_hal_tim.c:5696
HAL_TIM_ACTIVE_CHANNEL_3
Definition: stm32l4xx_hal_tim.h:309
TIM_BreakDeadTimeConfigTypeDef::Break2Polarity
uint32_t Break2Polarity
Definition: stm32l4xx_hal_tim.h:282
HAL_TIM_ConfigClockSource
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
Definition: stm32l4xx_hal_tim.c:4611
TIM_SlaveConfigTypeDef::TriggerPolarity
uint32_t TriggerPolarity
Definition: stm32l4xx_hal_tim.h:250
HAL_TIM_PWM_Init
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and ...
Definition: stm32l4xx_hal_tim.c:1177
HAL_TIM_OC_GetState
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
Return the TIM OC handle state.
Definition: stm32l4xx_hal_tim.c:5634
HAL_TIM_BREAK2_CB_ID
Definition: stm32l4xx_hal_tim.h:399
TIM_OC_InitTypeDef::OCFastMode
uint32_t OCFastMode
Definition: stm32l4xx_hal_tim.h:93
HAL_TIM_BREAK_CB_ID
Definition: stm32l4xx_hal_tim.h:398
TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput
uint32_t AutomaticOutput
Definition: stm32l4xx_hal_tim.h:286
HAL_TIM_ACTIVE_CHANNEL_5
Definition: stm32l4xx_hal_tim.h:311
HAL_TIM_Base_MspDeInit
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
Definition: stm32l4xx_hal_tim.c:371
TIM_DMACaptureHalfCplt
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
TIM DMA Capture half complete callback.
Definition: stm32l4xx_hal_tim.c:5837
HAL_TIM_IC_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:373
HAL_TIM_OnePulse_ConfigChannel
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_Init...
Definition: stm32l4xx_hal_tim.c:3752
HAL_TIM_STATE_BUSY
Definition: stm32l4xx_hal_tim.h:297
HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:383
pTIM_CallbackTypeDef
void(* pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim)
HAL TIM Callback pointer definition.
Definition: stm32l4xx_hal_tim.h:405
HAL_TIM_PWM_Stop
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
Definition: stm32l4xx_hal_tim.c:1343
HAL_TIM_OnePulse_GetState
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode handle state.
Definition: stm32l4xx_hal_tim.c:5664
HAL_TIM_Encoder_Stop_IT
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
Definition: stm32l4xx_hal_tim.c:2923
HAL_TIM_COMMUTATION_HALF_CB_ID
Definition: stm32l4xx_hal_tim.h:397
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32l4xx_hal_tim.h:293
TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode
uint32_t OffStateRunMode
Definition: stm32l4xx_hal_tim.h:266
TIM_MasterConfigTypeDef::MasterSlaveMode
uint32_t MasterSlaveMode
Definition: stm32l4xx_hal_tim.h:237
HAL_TIM_OC_Stop_IT
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:870
HAL_TIM_BASE_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:371
TIM_OnePulse_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32l4xx_hal_tim.h:112
TIM_DMACaptureCplt
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
Definition: stm32l4xx_hal_tim.c:5796
HAL_TIM_OC_MspDeInit
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
Definition: stm32l4xx_hal_tim.c:703
HAL_TIM_SlaveConfigSynchro
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
Definition: stm32l4xx_hal_tim.c:4795
HAL_TIM_TRIGGER_CB_ID
Definition: stm32l4xx_hal_tim.h:387
HAL_TIM_PWM_Stop_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
Definition: stm32l4xx_hal_tim.c:1658
HAL_TIM_PWM_GetState
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
Return the TIM PWM handle state.
Definition: stm32l4xx_hal_tim.c:5644
TIM_Base_InitTypeDef::Period
uint32_t Period
Definition: stm32l4xx_hal_tim.h:55
TIM_ETR_SetConfig
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
Definition: stm32l4xx_hal_tim.c:6816
HAL_TIM_PWM_Start
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
Definition: stm32l4xx_hal_tim.c:1303
HAL_TIM_Encoder_Start
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
Definition: stm32l4xx_hal_tim.c:2783
HAL_TIM_IC_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:374
HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:384
HAL_TIM_OnePulse_DeInit
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
Definition: stm32l4xx_hal_tim.c:2353
HAL_TIM_STATE_RESET
Definition: stm32l4xx_hal_tim.h:295
HAL_TIM_TRIGGER_HALF_CB_ID
Definition: stm32l4xx_hal_tim.h:388
HAL_TIM_OC_DELAY_ELAPSED_CB_ID
Definition: stm32l4xx_hal_tim.h:392
TIM_OnePulse_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32l4xx_hal_tim.h:121
TIM_OnePulse_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32l4xx_hal_tim.h:139
HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:380
HAL_TIM_OC_Start_IT
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:798
HAL_TIM_Base_Stop
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
Definition: stm32l4xx_hal_tim.c:416
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32l4xx_hal_def.h:50
TIM_Base_InitTypeDef::CounterMode
uint32_t CounterMode
Definition: stm32l4xx_hal_tim.h:52
endif::Init
TIM_Base_InitTypeDef Init
Definition: stm32l4xx_hal_tim.h:326
HAL_TIM_IC_GetState
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
Return the TIM Input Capture handle state.
Definition: stm32l4xx_hal_tim.c:5654
TIM_Encoder_InitTypeDef::IC2Selection
uint32_t IC2Selection
Definition: stm32l4xx_hal_tim.h:184
HAL_TIM_IC_Stop
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
Definition: stm32l4xx_hal_tim.c:1911
HAL_TIM_IC_ConfigChannel
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTy...
Definition: stm32l4xx_hal_tim.c:3508
stm32l4xx_hal_tim_ex.h
Header file of TIM HAL Extended module.
HAL_TIM_OC_Stop
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
Definition: stm32l4xx_hal_tim.c:766
HAL_TIM_Encoder_Start_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
Definition: stm32l4xx_hal_tim.c:2977
TIM_OC_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32l4xx_hal_tim.h:80
TIM_BreakDeadTimeConfigTypeDef::LockLevel
uint32_t LockLevel
Definition: stm32l4xx_hal_tim.h:270
TIM_IC_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32l4xx_hal_tim.h:151
TIM_ClockConfigTypeDef::ClockPolarity
uint32_t ClockPolarity
Definition: stm32l4xx_hal_tim.h:201
TIM_OC_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32l4xx_hal_tim.h:86
HAL_TIM_ONE_PULSE_MSPINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:379
HAL_TIM_IC_Stop_IT
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
Definition: stm32l4xx_hal_tim.c:2002
HAL_TIM_PWM_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:378
TIM_CCxChannelCmd
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
Definition: stm32l4xx_hal_tim.c:6848
TIM_BreakDeadTimeConfigTypeDef::Break2State
uint32_t Break2State
Definition: stm32l4xx_hal_tim.h:280
HAL_TIM_DMABurst_ReadStop
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
Definition: stm32l4xx_hal_tim.c:4332
HAL_TIM_OC_MspInit
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
Definition: stm32l4xx_hal_tim.c:688
HAL_TIM_OC_DelayElapsedCallback
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
Output Compare callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:4992
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:78
HAL_TIM_Base_Start_DMA
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
Definition: stm32l4xx_hal_tim.c:486
HAL_TIM_Encoder_Stop_DMA
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
Definition: stm32l4xx_hal_tim.c:3112
TIM_OC_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32l4xx_hal_tim.h:89
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32l4xx_hal_tim.h:264
HAL_TIM_PeriodElapsedCallback
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
Period elapsed callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:4962
HAL_TIM_IC_CAPTURE_CB_ID
Definition: stm32l4xx_hal_tim.h:390
HAL_TIM_ACTIVE_CHANNEL_1
Definition: stm32l4xx_hal_tim.h:307
HAL_TIM_Base_GetState
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
Return the TIM Base handle state.
Definition: stm32l4xx_hal_tim.c:5624
HAL_TIM_PWM_Start_IT
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:1378
HAL_TIM_PERIOD_ELAPSED_CB_ID
Definition: stm32l4xx_hal_tim.h:385
HAL_TIM_OnePulse_MspInit
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
Definition: stm32l4xx_hal_tim.c:2389
TIM_Base_InitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32l4xx_hal_tim.h:49
endif
ADC handle Structure definition.
Definition: stm32l4xx_hal_adc.h:360
TIM_ClearInputConfigTypeDef::ClearInputPolarity
uint32_t ClearInputPolarity
Definition: stm32l4xx_hal_tim.h:218
TIM_ClockConfigTypeDef::ClockFilter
uint32_t ClockFilter
Definition: stm32l4xx_hal_tim.h:205
HAL_TIM_IC_CaptureCallback
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
Input Capture callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5007
HAL_TIM_IC_DeInit
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
Definition: stm32l4xx_hal_tim.c:1807
TIM_Encoder_InitTypeDef::EncoderMode
uint32_t EncoderMode
Definition: stm32l4xx_hal_tim.h:166
TIM_ClearInputConfigTypeDef::ClearInputFilter
uint32_t ClearInputFilter
Definition: stm32l4xx_hal_tim.h:222
TIM_ClockConfigTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32l4xx_hal_tim.h:203
HAL_TIM_OC_Init
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and...
Definition: stm32l4xx_hal_tim.c:600
HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID
Definition: stm32l4xx_hal_tim.h:386
TIM_OnePulse_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32l4xx_hal_tim.h:129
HAL_TIM_TriggerHalfCpltCallback
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
Hall Trigger detection half complete callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5082
HAL_TIM_BASE_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:372
TIM_OC2_SetConfig
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Timer Output Compare 2 configuration.
Definition: stm32l4xx_hal_tim.c:6074
HAL_TIM_OC_Start
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
Definition: stm32l4xx_hal_tim.c:726
TIM_MasterConfigTypeDef::MasterOutputTrigger
uint32_t MasterOutputTrigger
Definition: stm32l4xx_hal_tim.h:233
TIM_IC_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32l4xx_hal_tim.h:157
TIM_BreakDeadTimeConfigTypeDef::BreakFilter
uint32_t BreakFilter
Definition: stm32l4xx_hal_tim.h:278
TIM_HandleTypeDef
struct __TIM_HandleTypeDef else typedef struct endif TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
HAL_TIM_DMABurst_WriteStop
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
Definition: stm32l4xx_hal_tim.c:4066
HAL_TIM_OnePulse_Start_IT
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:2495
HAL_TIM_STATE_ERROR
Definition: stm32l4xx_hal_tim.h:299
HAL_TIM_ERROR_CB_ID
Definition: stm32l4xx_hal_tim.h:395
HAL_TIM_PWM_Stop_IT
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
Definition: stm32l4xx_hal_tim.c:1449
HAL_TIM_ConfigOCrefClear
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
Definition: stm32l4xx_hal_tim.c:4450
TIM_OnePulse_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32l4xx_hal_tim.h:125
TIM_OnePulse_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32l4xx_hal_tim.h:118
HAL_TIM_IC_Start
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
Definition: stm32l4xx_hal_tim.c:1879
HAL_TIM_ENCODER_MSPDEINIT_CB_ID
Definition: stm32l4xx_hal_tim.h:382
HAL_TIM_Base_MspInit
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
Definition: stm32l4xx_hal_tim.c:356
HAL_TIM_PWM_Start_DMA
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
Definition: stm32l4xx_hal_tim.c:1517
HAL_TIM_Base_DeInit
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
Definition: stm32l4xx_hal_tim.c:320
HAL_TIM_RegisterCallback
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
Register a User TIM callback to be used instead of the weak predefined callback.
Definition: stm32l4xx_hal_tim.c:5144
HAL_TIM_PeriodElapsedHalfCpltCallback
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
Period elapsed half complete callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:4977
HAL_TIM_OC_DeInit
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
Definition: stm32l4xx_hal_tim.c:652
HAL_TIM_TriggerCallback
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non-blocking mode.
Definition: stm32l4xx_hal_tim.c:5067
TIM_Encoder_InitTypeDef::IC1Selection
uint32_t IC1Selection
Definition: stm32l4xx_hal_tim.h:172
HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID
Definition: stm32l4xx_hal_tim.h:394
TIM_Encoder_InitTypeDef::IC1Filter
uint32_t IC1Filter
Definition: stm32l4xx_hal_tim.h:178
HAL_TIM_ConfigTI1Input
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1...
Definition: stm32l4xx_hal_tim.c:4763
else
else
Definition: stm32l4xx_ll_lpuart.h:1488
HAL_TIM_PWM_ConfigChannel
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
Definition: stm32l4xx_hal_tim.c:3607
TIM_MasterConfigTypeDef::MasterOutputTrigger2
uint32_t MasterOutputTrigger2
Definition: stm32l4xx_hal_tim.h:235
HAL_TIM_DMABurst_WriteStart
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
Definition: stm32l4xx_hal_tim.c:3897
TIM_IC_InitTypeDef::ICPrescaler
uint32_t ICPrescaler
Definition: stm32l4xx_hal_tim.h:154
TIM_BreakDeadTimeConfigTypeDef::DeadTime
uint32_t DeadTime
Definition: stm32l4xx_hal_tim.h:272
HAL_TIM_Encoder_MspDeInit
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
Definition: stm32l4xx_hal_tim.c:2763
TIM_ClearInputConfigTypeDef::ClearInputState
uint32_t ClearInputState
Definition: stm32l4xx_hal_tim.h:214