RCC Private functions

Functions
uint32_t	RCC_GetSystemClockFreq (void)
	Return SYSTEM clock frequency. More...
uint32_t	RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
	Return HCLK clock frequency. More...
uint32_t	RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
	Return PCLK1 clock frequency. More...
uint32_t	RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
	Return PCLK2 clock frequency. More...
uint32_t	RCC_PLL_GetFreqDomain_SYS (void)
	Return PLL clock frequency used for system domain. More...
uint32_t	RCC_PLL_GetFreqDomain_SAI (void)
	Return PLL clock frequency used for SAI domain. More...
uint32_t	RCC_PLL_GetFreqDomain_48M (void)
	Return PLL clock frequency used for 48 MHz domain. More...
uint32_t	RCC_PLLSAI1_GetFreqDomain_SAI (void)
	Return PLLSAI1 clock frequency used for SAI domain. More...
uint32_t	RCC_PLLSAI1_GetFreqDomain_48M (void)
	Return PLLSAI1 clock frequency used for 48Mhz domain. More...
uint32_t	RCC_PLLSAI1_GetFreqDomain_ADC (void)
	Return PLLSAI1 clock frequency used for ADC domain. More...
uint32_t	RCC_PLLSAI2_GetFreqDomain_SAI (void)
	Return PLLSAI2 clock frequency used for SAI domain. More...
uint32_t	RCC_PLLSAI2_GetFreqDomain_LTDC (void)
	Return PLLSAI2 clock frequency used for LTDC domain. More...
uint32_t	RCC_PLLSAI2_GetFreqDomain_ADC (void)
	Return PLLSAI2 clock frequency used for ADC domain. More...
uint32_t	RCC_PLLSAI2_GetFreqDomain_DSI (void)
	Return PLL clock frequency used for DSI clock. More...

Detailed Description

Function Documentation

RCC_GetHCLKClockFreq()

uint32_t RCC_GetHCLKClockFreq

(

uint32_t

SYSCLK_Frequency

)

Return HCLK clock frequency.

Parameters

SYSCLK_Frequency

SYSCLK clock frequency

Return values

HCLK	clock frequency (in Hz)

Definition at line 1500 of file stm32l4xx_ll_rcc.c.

{
  /* HCLK clock frequency */
  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
}

RCC_GetPCLK1ClockFreq()

uint32_t RCC_GetPCLK1ClockFreq

(

uint32_t

HCLK_Frequency

)

Return PCLK1 clock frequency.

Parameters

HCLK_Frequency

HCLK clock frequency

Return values

PCLK1

clock frequency (in Hz)

Definition at line 1511 of file stm32l4xx_ll_rcc.c.

{
  /* PCLK1 clock frequency */
  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
}

RCC_GetPCLK2ClockFreq()

uint32_t RCC_GetPCLK2ClockFreq

(

uint32_t

HCLK_Frequency

)

Return PCLK2 clock frequency.

Parameters

HCLK_Frequency

HCLK clock frequency

Return values

PCLK2

clock frequency (in Hz)

Definition at line 1522 of file stm32l4xx_ll_rcc.c.

{
  /* PCLK2 clock frequency */
  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
}

RCC_GetSystemClockFreq()

uint32_t RCC_GetSystemClockFreq

(

void

)

Return SYSTEM clock frequency.

Return values

SYSTEM

clock frequency (in Hz)

Definition at line 1458 of file stm32l4xx_ll_rcc.c.

{
  uint32_t frequency;

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (LL_RCC_GetSysClkSource())
  {
    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
      frequency = HSI_VALUE;
      break;

    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
      frequency = HSE_VALUE;
      break;

    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
      frequency = RCC_PLL_GetFreqDomain_SYS();
      break;

    default:
      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }

  return frequency;
}

RCC_PLL_GetFreqDomain_48M()

uint32_t RCC_PLL_GetFreqDomain_48M

(

void

)

Return PLL clock frequency used for 48 MHz domain.

Return values

PLL	clock frequency (in Hz)

Definition at line 1616 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
     48M Domain clock = PLL_VCO / PLLQ
  */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
}

RCC_PLL_GetFreqDomain_SAI()

uint32_t RCC_PLL_GetFreqDomain_SAI

(

void

)

Return PLL clock frequency used for SAI domain.

Return values

PLL	clock frequency (in Hz)

Definition at line 1574 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
     SAI Domain clock = PLL_VCO / PLLP
  */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
}

RCC_PLL_GetFreqDomain_SYS()

uint32_t RCC_PLL_GetFreqDomain_SYS

(

void

)

Return PLL clock frequency used for system domain.

Return values

PLL	clock frequency (in Hz)

Definition at line 1532 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
     SYSCLK = PLL_VCO / PLLR
  */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
}

RCC_PLLSAI1_GetFreqDomain_48M()

uint32_t RCC_PLLSAI1_GetFreqDomain_48M

(

void

)

Return PLLSAI1 clock frequency used for 48Mhz domain.

Return values

PLLSAI1

clock frequency (in Hz)

Definition at line 1744 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
#else
  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
#endif
  /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1Q */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
}

RCC_PLLSAI1_GetFreqDomain_ADC()

uint32_t RCC_PLLSAI1_GetFreqDomain_ADC

(

void

)

Return PLLSAI1 clock frequency used for ADC domain.

Return values

PLLSAI1

clock frequency (in Hz)

Definition at line 1788 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
#else
  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
#endif
  /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1R */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
}

RCC_PLLSAI1_GetFreqDomain_SAI()

uint32_t RCC_PLLSAI1_GetFreqDomain_SAI

(

void

)

Return PLLSAI1 clock frequency used for SAI domain.

Return values

PLLSAI1

clock frequency (in Hz)

Definition at line 1700 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
#else
  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
#endif
  /* SAI Domain clock  = PLLSAI1_VCO / PLLSAI1P */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
}

RCC_PLLSAI2_GetFreqDomain_ADC()

uint32_t RCC_PLLSAI2_GetFreqDomain_ADC

(

void

)

Return PLLSAI2 clock frequency used for ADC domain.

Return values

PLLSAI2

clock frequency (in Hz)

Definition at line 1927 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq = 0U, pllsource = 0U;

  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
  /* 48M Domain clock  = PLLSAI2_VCO / PLLSAI2R */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
  return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
}

RCC_PLLSAI2_GetFreqDomain_DSI()

uint32_t RCC_PLLSAI2_GetFreqDomain_DSI

(

void

)

Return PLL clock frequency used for DSI clock.

Return values

PLL	clock frequency (in Hz)

Definition at line 1657 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
  /* DSICLK = PLLSAI2_VCO / PLLSAI2R */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }

  return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
}

RCC_PLLSAI2_GetFreqDomain_LTDC()

uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC

(

void

)

Return PLLSAI2 clock frequency used for LTDC domain.

Return values

PLLSAI2

clock frequency (in Hz)

Definition at line 1884 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
  /* LTDC Domain clock  = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }

  return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
                                         LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());
}

RCC_PLLSAI2_GetFreqDomain_SAI()

uint32_t RCC_PLLSAI2_GetFreqDomain_SAI

(

void

)

Return PLLSAI2 clock frequency used for SAI domain.

Return values

PLLSAI2

clock frequency (in Hz)

Definition at line 1834 of file stm32l4xx_ll_rcc.c.

{
  uint32_t pllinputfreq, pllsource;

#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
#else
  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
#endif
  /* SAI Domain clock  = PLLSAI2_VCO / PLLSAI2P */
  pllsource = LL_RCC_PLL_GetMainSource();

  switch (pllsource)
  {
    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;

    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */
      pllinputfreq = HSI_VALUE;
      break;

    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */
      pllinputfreq = HSE_VALUE;
      break;

    default:
      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
                                    ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
                                     LL_RCC_MSI_GetRange() :
                                     LL_RCC_MSI_GetRangeAfterStandby()));
      break;
  }
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
  return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
#else
  return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
#endif
}