UTILS Private functions

Functions
static uint32_t	UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
	Function to check that PLL can be modified. More...
static ErrorStatus	UTILS_SetFlashLatency (uint32_t HCLK_Frequency)
	Update number of Flash wait states in line with new frequency and current voltage range. More...
static ErrorStatus	UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	Function to enable PLL and switch system clock to PLL. More...
static ErrorStatus	UTILS_PLL_IsBusy (void)
	Function to check that PLL can be modified. More...

Detailed Description

Function Documentation

UTILS_EnablePLLAndSwitchSystem()

static ErrorStatus UTILS_EnablePLLAndSwitchSystem ( uint32_t  SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *  UTILS_ClkInitStruct  )

static

Function to enable PLL and switch system clock to PLL.

Parameters

SYSCLK_Frequency	SYSCLK frequency
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: No problem to switch system to PLL ERROR: Problem to switch system to PLL

Definition at line 805 of file stm32l4xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;
  uint32_t hclk_frequency;

  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));

  /* Calculate HCLK frequency */
  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);

  /* Increasing the number of wait states because of higher CPU frequency */
  if(SystemCoreClock < hclk_frequency)
  {
    /* Set FLASH latency to highest latency */
    status = UTILS_SetFlashLatency(hclk_frequency);
  }

  /* Update system clock configuration */
  if(status == SUCCESS)
  {
    /* Enable PLL */
    LL_RCC_PLL_Enable();
    LL_RCC_PLL_EnableDomain_SYS();
    while (LL_RCC_PLL_IsReady() != 1U)
    {
      /* Wait for PLL ready */
    }

    /* Sysclk activation on the main PLL */
    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
    {
      /* Wait for system clock switch to PLL */
    }

    /* Set APB1 & APB2 prescaler*/
    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if(SystemCoreClock > hclk_frequency)
  {
    /* Set FLASH latency to lowest latency */
    status = UTILS_SetFlashLatency(hclk_frequency);
  }

  /* Update SystemCoreClock variable */
  if(status == SUCCESS)
  {
    LL_SetSystemCoreClock(hclk_frequency);
  }

  return status;
}

UTILS_GetPLLOutputFrequency()

static uint32_t UTILS_GetPLLOutputFrequency ( uint32_t  PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *  UTILS_PLLInitStruct  )

static

Function to check that PLL can be modified.

Parameters

PLL_InputFrequency	PLL input frequency (in Hz)
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.

Return values

PLL	output frequency (in Hz)

Definition at line 733 of file stm32l4xx_ll_utils.c.

{
  uint32_t pllfreq;

  /* Check the parameters */
  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
  assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));

  /* Check different PLL parameters according to RM                          */
  /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */
  pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));

  /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));

  /*  - PLLR: ensure that max frequency at 120000000 Hz is reached                   */
  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U);
  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));

  return pllfreq;
}

UTILS_PLL_IsBusy()

static ErrorStatus UTILS_PLL_IsBusy ( void  )

static

Function to check that PLL can be modified.

Return values

An	ErrorStatus enumeration value: SUCCESS: PLL modification can be done ERROR: PLL is busy

Definition at line 764 of file stm32l4xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;

  /* Check if PLL is busy*/
  if(LL_RCC_PLL_IsReady() != 0U)
  {
    /* PLL configuration cannot be modified */
    status = ERROR;
  }

#if defined(RCC_PLLSAI1_SUPPORT)
  /* Check if PLLSAI1 is busy*/
  if(LL_RCC_PLLSAI1_IsReady() != 0U)
  {
    /* PLLSAI1 configuration cannot be modified */
    status = ERROR;
  }
#endif /*RCC_PLLSAI1_SUPPORT*/
#if defined(RCC_PLLSAI2_SUPPORT)

  /* Check if PLLSAI2 is busy*/
  if(LL_RCC_PLLSAI2_IsReady() != 0U)
  {
    /* PLLSAI2 configuration cannot be modified */
    status = ERROR;
  }
#endif /*RCC_PLLSAI2_SUPPORT*/

  return status;
}

UTILS_SetFlashLatency()

static ErrorStatus UTILS_SetFlashLatency ( uint32_t  HCLK_Frequency )

static

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters

HCLK_Frequency

HCLK frequency

Return values

An	ErrorStatus enumeration value: SUCCESS: Latency has been modified ERROR: Latency cannot be modified

Definition at line 602 of file stm32l4xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;

  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */

  /* Frequency cannot be equal to 0 */
  if(HCLK_Frequency == 0U)
  {
    status = ERROR;
  }
  else
  {
    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
    {
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
      if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)
      {
        /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
        latency = LL_FLASH_LATENCY_5;
      }
      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
      {
        /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
        latency = LL_FLASH_LATENCY_4;
      }
      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
      {
        /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
        latency = LL_FLASH_LATENCY_3;
      }
      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
      {
        /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */
        latency = LL_FLASH_LATENCY_2;
      }
      else
      {
        if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
        {
          /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
          latency = LL_FLASH_LATENCY_1;
        }
        /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
      }
#else
      if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
      {
        /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */
        latency = LL_FLASH_LATENCY_4;
      }
      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
      {
        /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */
        latency = LL_FLASH_LATENCY_3;
      }
      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
      {
        /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */
        latency = LL_FLASH_LATENCY_2;
      }
      else
      {
        if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
        {
          /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
          latency = LL_FLASH_LATENCY_1;
        }
        /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */
      }
#endif
    }
    else /* SCALE2 */
    {
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
      if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
      {
        /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
        latency = LL_FLASH_LATENCY_2;
      }
      else
      {
        if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
        {
          /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
          latency = LL_FLASH_LATENCY_1;
        }
        /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
      }
#else
      if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
      {
        /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */
        latency = LL_FLASH_LATENCY_3;
      }
      else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
      {
        /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */
        latency = LL_FLASH_LATENCY_2;
      }
      else
      {
        if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
        {
          /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */
          latency = LL_FLASH_LATENCY_1;
        }
        /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */
      }
#endif
    }

    LL_FLASH_SetLatency(latency);

    /* Check that the new number of wait states is taken into account to access the Flash
       memory by reading the FLASH_ACR register */
    if(LL_FLASH_GetLatency() != latency)
    {
      status = ERROR;
    }
  }
  return status;
}