Header file of BUS LL module. More...

Functions
__STATIC_INLINE void	LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB1 peripherals clock. AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock. More...

__STATIC_INLINE uint32_t	LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB1 peripheral clock is enabled or not AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock. More...

__STATIC_INLINE void	LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB1 peripherals clock. AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock. More...

__STATIC_INLINE void	LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
	Force AHB1 peripherals reset. AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset. More...

__STATIC_INLINE void	LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB1 peripherals reset. AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset. More...

__STATIC_INLINE void	LL_AHB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable AHB1 peripheral clocks in Sleep and Stop modes AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep. More...

__STATIC_INLINE void	LL_AHB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable AHB1 peripheral clocks in Sleep and Stop modes AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep. More...

__STATIC_INLINE void	LL_AHB2_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB2 peripherals clock. AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock AHB2ENR AESEN LL_AHB2_GRP1_EnableClock AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock. More...

__STATIC_INLINE uint32_t	LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB2 peripheral clock is enabled or not AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock. More...

__STATIC_INLINE void	LL_AHB2_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB2 peripherals clock. AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock AHB2ENR AESEN LL_AHB2_GRP1_DisableClock AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock. More...

__STATIC_INLINE void	LL_AHB2_GRP1_ForceReset (uint32_t Periphs)
	Force AHB2 peripherals reset. AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset. More...

__STATIC_INLINE void	LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB2 peripherals reset. AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset. More...

__STATIC_INLINE void	LL_AHB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable AHB2 peripheral clocks in Sleep and Stop modes AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep. More...

__STATIC_INLINE void	LL_AHB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable AHB2 peripheral clocks in Sleep and Stop modes AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep. More...

__STATIC_INLINE void	LL_AHB3_GRP1_EnableClock (uint32_t Periphs)
	Enable AHB3 peripherals clock. AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock. More...

__STATIC_INLINE uint32_t	LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if AHB3 peripheral clock is enabled or not AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock. More...

__STATIC_INLINE void	LL_AHB3_GRP1_DisableClock (uint32_t Periphs)
	Disable AHB3 peripherals clock. AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock. More...

__STATIC_INLINE void	LL_AHB3_GRP1_ForceReset (uint32_t Periphs)
	Force AHB3 peripherals reset. AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset. More...

__STATIC_INLINE void	LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs)
	Release AHB3 peripherals reset. AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset. More...

__STATIC_INLINE void	LL_AHB3_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable AHB3 peripheral clocks in Sleep and Stop modes AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep. More...

__STATIC_INLINE void	LL_AHB3_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable AHB3 peripheral clocks in Sleep and Stop modes AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep . More...

__STATIC_INLINE void	LL_APB1_GRP1_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock. APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock APB1ENR1 PWREN LL_APB1_GRP1_EnableClock APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock. More...

__STATIC_INLINE void	LL_APB1_GRP2_EnableClock (uint32_t Periphs)
	Enable APB1 peripherals clock. APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock. More...

__STATIC_INLINE uint32_t	LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock. More...

__STATIC_INLINE uint32_t	LL_APB1_GRP2_IsEnabledClock (uint32_t Periphs)
	Check if APB1 peripheral clock is enabled or not APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock. More...

__STATIC_INLINE void	LL_APB1_GRP1_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock. APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock APB1ENR1 PWREN LL_APB1_GRP1_DisableClock APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock. More...

__STATIC_INLINE void	LL_APB1_GRP2_DisableClock (uint32_t Periphs)
	Disable APB1 peripherals clock. APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock. More...

__STATIC_INLINE void	LL_APB1_GRP1_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset. APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset. More...

__STATIC_INLINE void	LL_APB1_GRP2_ForceReset (uint32_t Periphs)
	Force APB1 peripherals reset. APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset. More...

__STATIC_INLINE void	LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset. APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset. More...

__STATIC_INLINE void	LL_APB1_GRP2_ReleaseReset (uint32_t Periphs)
	Release APB1 peripherals reset. APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset. More...

__STATIC_INLINE void	LL_APB1_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep. More...

__STATIC_INLINE void	LL_APB1_GRP2_EnableClockStopSleep (uint32_t Periphs)
	Enable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep. More...

__STATIC_INLINE void	LL_APB1_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep. More...

__STATIC_INLINE void	LL_APB1_GRP2_DisableClockStopSleep (uint32_t Periphs)
	Disable APB1 peripheral clocks in Sleep and Stop modes APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep. More...

__STATIC_INLINE void	LL_APB2_GRP1_EnableClock (uint32_t Periphs)
	Enable APB2 peripherals clock. APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock APB2ENR FWEN LL_APB2_GRP1_EnableClock APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock APB2ENR TIM1EN LL_APB2_GRP1_EnableClock APB2ENR SPI1EN LL_APB2_GRP1_EnableClock APB2ENR TIM8EN LL_APB2_GRP1_EnableClock APB2ENR USART1EN LL_APB2_GRP1_EnableClock APB2ENR TIM15EN LL_APB2_GRP1_EnableClock APB2ENR TIM16EN LL_APB2_GRP1_EnableClock APB2ENR TIM17EN LL_APB2_GRP1_EnableClock APB2ENR SAI1EN LL_APB2_GRP1_EnableClock APB2ENR SAI2EN LL_APB2_GRP1_EnableClock APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock APB2ENR LTDCEN LL_APB2_GRP1_EnableClock APB2ENR DSIEN LL_APB2_GRP1_EnableClock. More...

__STATIC_INLINE uint32_t	LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
	Check if APB2 peripheral clock is enabled or not APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock. More...

__STATIC_INLINE void	LL_APB2_GRP1_DisableClock (uint32_t Periphs)
	Disable APB2 peripherals clock. APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock APB2ENR TIM1EN LL_APB2_GRP1_DisableClock APB2ENR SPI1EN LL_APB2_GRP1_DisableClock APB2ENR TIM8EN LL_APB2_GRP1_DisableClock APB2ENR USART1EN LL_APB2_GRP1_DisableClock APB2ENR TIM15EN LL_APB2_GRP1_DisableClock APB2ENR TIM16EN LL_APB2_GRP1_DisableClock APB2ENR TIM17EN LL_APB2_GRP1_DisableClock APB2ENR SAI1EN LL_APB2_GRP1_DisableClock APB2ENR SAI2EN LL_APB2_GRP1_DisableClock APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock APB2ENR LTDCEN LL_APB2_GRP1_DisableClock APB2ENR DSIEN LL_APB2_GRP1_DisableClock. More...

__STATIC_INLINE void	LL_APB2_GRP1_ForceReset (uint32_t Periphs)
	Force APB2 peripherals reset. APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset APB2RSTR USART1RST LL_APB2_GRP1_ForceReset APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset APB2RSTR DSIRST LL_APB2_GRP1_ForceReset. More...

__STATIC_INLINE void	LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
	Release APB2 peripherals reset. APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset. More...

__STATIC_INLINE void	LL_APB2_GRP1_EnableClockStopSleep (uint32_t Periphs)
	Enable APB2 peripheral clocks in Sleep and Stop modes APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep. More...

__STATIC_INLINE void	LL_APB2_GRP1_DisableClockStopSleep (uint32_t Periphs)
	Disable APB2 peripheral clocks in Sleep and Stop modes APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep. More...

Detailed Description

Header file of BUS LL module.

Author

MCD Application Team

                    ##### RCC Limitations #####
==============================================================================
  [..]
    A delay between an RCC peripheral clock enable and the effective peripheral
    enabling should be taken into account in order to manage the peripheral read/write
    from/to registers.
    (+) This delay depends on the peripheral mapping.
      (++) AHB & APB peripherals, 1 dummy read is necessary

  [..]
    Workarounds:
    (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
        inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

Attention

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32l4xx_ll_bus.h.

Functions

Detailed Description

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